drivers/spi/spi-atmel.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_data/atmel.h>
  23 #include <linux/platform_data/dma-atmel.h>
  24 #include <linux/of.h>
  25
  26 #include <linux/io.h>
  27 #include <linux/gpio.h>
  28
  29 /* SPI register offsets */
  30 #define SPI_CR                                  0x0000
  31 #define SPI_MR                                  0x0004
  32 #define SPI_RDR                                 0x0008
  33 #define SPI_TDR                                 0x000c
  34 #define SPI_SR                                  0x0010
  35 #define SPI_IER                                 0x0014
  36 #define SPI_IDR                                 0x0018
  37 #define SPI_IMR                                 0x001c
  38 #define SPI_CSR0                                0x0030
  39 #define SPI_CSR1                                0x0034
  40 #define SPI_CSR2                                0x0038
  41 #define SPI_CSR3                                0x003c
  42 #define SPI_VERSION                             0x00fc
  43 #define SPI_RPR                                 0x0100
  44 #define SPI_RCR                                 0x0104
  45 #define SPI_TPR                                 0x0108
  46 #define SPI_TCR                                 0x010c
  47 #define SPI_RNPR                                0x0110
  48 #define SPI_RNCR                                0x0114
  49 #define SPI_TNPR                                0x0118
  50 #define SPI_TNCR                                0x011c
  51 #define SPI_PTCR                                0x0120
  52 #define SPI_PTSR                                0x0124
  53
  54 /* Bitfields in CR */
  55 #define SPI_SPIEN_OFFSET                        0
  56 #define SPI_SPIEN_SIZE                          1
  57 #define SPI_SPIDIS_OFFSET                       1
  58 #define SPI_SPIDIS_SIZE                         1
  59 #define SPI_SWRST_OFFSET                        7
  60 #define SPI_SWRST_SIZE                          1
  61 #define SPI_LASTXFER_OFFSET                     24
  62 #define SPI_LASTXFER_SIZE                       1
  63
  64 /* Bitfields in MR */
  65 #define SPI_MSTR_OFFSET                         0
  66 #define SPI_MSTR_SIZE                           1
  67 #define SPI_PS_OFFSET                           1
  68 #define SPI_PS_SIZE                             1
  69 #define SPI_PCSDEC_OFFSET                       2
  70 #define SPI_PCSDEC_SIZE                         1
  71 #define SPI_FDIV_OFFSET                         3
  72 #define SPI_FDIV_SIZE                           1
  73 #define SPI_MODFDIS_OFFSET                      4
  74 #define SPI_MODFDIS_SIZE                        1
  75 #define SPI_WDRBT_OFFSET                        5
  76 #define SPI_WDRBT_SIZE                          1
  77 #define SPI_LLB_OFFSET                          7
  78 #define SPI_LLB_SIZE                            1
  79 #define SPI_PCS_OFFSET                          16
  80 #define SPI_PCS_SIZE                            4
  81 #define SPI_DLYBCS_OFFSET                       24
  82 #define SPI_DLYBCS_SIZE                         8
  83
  84 /* Bitfields in RDR */
  85 #define SPI_RD_OFFSET                           0
  86 #define SPI_RD_SIZE                             16
  87
  88 /* Bitfields in TDR */
  89 #define SPI_TD_OFFSET                           0
  90 #define SPI_TD_SIZE                             16
  91
  92 /* Bitfields in SR */
  93 #define SPI_RDRF_OFFSET                         0
  94 #define SPI_RDRF_SIZE                           1
  95 #define SPI_TDRE_OFFSET                         1
  96 #define SPI_TDRE_SIZE                           1
  97 #define SPI_MODF_OFFSET                         2
  98 #define SPI_MODF_SIZE                           1
  99 #define SPI_OVRES_OFFSET                        3
 100 #define SPI_OVRES_SIZE                          1
 101 #define SPI_ENDRX_OFFSET                        4
 102 #define SPI_ENDRX_SIZE                          1
 103 #define SPI_ENDTX_OFFSET                        5
 104 #define SPI_ENDTX_SIZE                          1
 105 #define SPI_RXBUFF_OFFSET                       6
 106 #define SPI_RXBUFF_SIZE                         1
 107 #define SPI_TXBUFE_OFFSET                       7
 108 #define SPI_TXBUFE_SIZE                         1
 109 #define SPI_NSSR_OFFSET                         8
 110 #define SPI_NSSR_SIZE                           1
 111 #define SPI_TXEMPTY_OFFSET                      9
 112 #define SPI_TXEMPTY_SIZE                        1
 113 #define SPI_SPIENS_OFFSET                       16
 114 #define SPI_SPIENS_SIZE                         1
 115
 116 /* Bitfields in CSR0 */
 117 #define SPI_CPOL_OFFSET                         0
 118 #define SPI_CPOL_SIZE                           1
 119 #define SPI_NCPHA_OFFSET                        1
 120 #define SPI_NCPHA_SIZE                          1
 121 #define SPI_CSAAT_OFFSET                        3
 122 #define SPI_CSAAT_SIZE                          1
 123 #define SPI_BITS_OFFSET                         4
 124 #define SPI_BITS_SIZE                           4
 125 #define SPI_SCBR_OFFSET                         8
 126 #define SPI_SCBR_SIZE                           8
 127 #define SPI_DLYBS_OFFSET                        16
 128 #define SPI_DLYBS_SIZE                          8
 129 #define SPI_DLYBCT_OFFSET                       24
 130 #define SPI_DLYBCT_SIZE                         8
 131
 132 /* Bitfields in RCR */
 133 #define SPI_RXCTR_OFFSET                        0
 134 #define SPI_RXCTR_SIZE                          16
 135
 136 /* Bitfields in TCR */
 137 #define SPI_TXCTR_OFFSET                        0
 138 #define SPI_TXCTR_SIZE                          16
 139
 140 /* Bitfields in RNCR */
 141 #define SPI_RXNCR_OFFSET                        0
 142 #define SPI_RXNCR_SIZE                          16
 143
 144 /* Bitfields in TNCR */
 145 #define SPI_TXNCR_OFFSET                        0
 146 #define SPI_TXNCR_SIZE                          16
 147
 148 /* Bitfields in PTCR */
 149 #define SPI_RXTEN_OFFSET                        0
 150 #define SPI_RXTEN_SIZE                          1
 151 #define SPI_RXTDIS_OFFSET                       1
 152 #define SPI_RXTDIS_SIZE                         1
 153 #define SPI_TXTEN_OFFSET                        8
 154 #define SPI_TXTEN_SIZE                          1
 155 #define SPI_TXTDIS_OFFSET                       9
 156 #define SPI_TXTDIS_SIZE                         1
 157
 158 /* Constants for BITS */
 159 #define SPI_BITS_8_BPT                          0
 160 #define SPI_BITS_9_BPT                          1
 161 #define SPI_BITS_10_BPT                         2
 162 #define SPI_BITS_11_BPT                         3
 163 #define SPI_BITS_12_BPT                         4
 164 #define SPI_BITS_13_BPT                         5
 165 #define SPI_BITS_14_BPT                         6
 166 #define SPI_BITS_15_BPT                         7
 167 #define SPI_BITS_16_BPT                         8
 168
 169 /* Bit manipulation macros */
 170 #define SPI_BIT(name) \
 171         (1 << SPI_##name##_OFFSET)
 172 #define SPI_BF(name, value) \
 173         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 174 #define SPI_BFEXT(name, value) \
 175         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 176 #define SPI_BFINS(name, value, old) \
 177         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 178           | SPI_BF(name, value))
 179
 180 /* Register access macros */
 181 #define spi_readl(port, reg) \
 182         __raw_readl((port)->regs + SPI_##reg)
 183 #define spi_writel(port, reg, value) \
 184         __raw_writel((value), (port)->regs + SPI_##reg)
 185
 186 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 187  * cache operations; better heuristics consider wordsize and bitrate.
 188  */
 189 #define DMA_MIN_BYTES   16
 190
 191 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 192
 193 struct atmel_spi_dma {
 194         struct dma_chan                 *chan_rx;
 195         struct dma_chan                 *chan_tx;
 196         struct scatterlist              sgrx;
 197         struct scatterlist              sgtx;
 198         struct dma_async_tx_descriptor  *data_desc_rx;
 199         struct dma_async_tx_descriptor  *data_desc_tx;
 200
 201         struct at_dma_slave     dma_slave;
 202 };
 203
 204 struct atmel_spi_caps {
 205         bool    is_spi2;
 206         bool    has_wdrbt;
 207         bool    has_dma_support;
 208 };
 209
 210 /*
 211  * The core SPI transfer engine just talks to a register bank to set up
 212  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 213  * framework provides the base clock, subdivided for each spi_device.
 214  */
 215 struct atmel_spi {
 216         spinlock_t              lock;
 217         unsigned long           flags;
 218
 219         phys_addr_t             phybase;
 220         void __iomem            *regs;
 221         int                     irq;
 222         struct clk              *clk;
 223         struct platform_device  *pdev;
 224
 225         struct spi_transfer     *current_transfer;
 226         unsigned long           current_remaining_bytes;
 227         int                     done_status;
 228
 229         struct completion       xfer_completion;
 230
 231         /* scratch buffer */
 232         void                    *buffer;
 233         dma_addr_t              buffer_dma;
 234
 235         struct atmel_spi_caps   caps;
 236
 237         bool                    use_dma;
 238         bool                    use_pdc;
 239         /* dmaengine data */
 240         struct atmel_spi_dma    dma;
 241
 242         bool                    keep_cs;
 243         bool                    cs_active;
 244 };
 245
 246 /* Controller-specific per-slave state */
 247 struct atmel_spi_device {
 248         unsigned int            npcs_pin;
 249         u32                     csr;
 250 };
 251
 252 #define BUFFER_SIZE             PAGE_SIZE
 253 #define INVALID_DMA_ADDRESS     0xffffffff
 254
 255 /*
 256  * Version 2 of the SPI controller has
 257  *  - CR.LASTXFER
 258  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 259  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 260  *  - SPI_CSRx.CSAAT
 261  *  - SPI_CSRx.SBCR allows faster clocking
 262  */
 263 static bool atmel_spi_is_v2(struct atmel_spi *as)
 264 {
 265         return as->caps.is_spi2;
 266 }
 267
 268 /*
 269  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 270  * they assume that spi slave device state will not change on deselect, so
 271  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 272  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 273  * controllers have CSAAT and friends.
 274  *
 275  * Since the CSAAT functionality is a bit weird on newer controllers as
 276  * well, we use GPIO to control nCSx pins on all controllers, updating
 277  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 278  * support active-high chipselects despite the controller's belief that
 279  * only active-low devices/systems exists.
 280  *
 281  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 282  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 283  * Master on Chip Select 0.")  No workaround exists for that ... so for
 284  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 285  * and (c) will trigger that first erratum in some cases.
 286  */
 287
 288 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 289 {
 290         struct atmel_spi_device *asd = spi->controller_state;
 291         unsigned active = spi->mode & SPI_CS_HIGH;
 292         u32 mr;
 293
 294         if (atmel_spi_is_v2(as)) {
 295                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 296                 /* For the low SPI version, there is a issue that PDC transfer
 297                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 298                  */
 299                 spi_writel(as, CSR0, asd->csr);
 300                 if (as->caps.has_wdrbt) {
 301                         spi_writel(as, MR,
 302                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 303                                         | SPI_BIT(WDRBT)
 304                                         | SPI_BIT(MODFDIS)
 305                                         | SPI_BIT(MSTR));
 306                 } else {
 307                         spi_writel(as, MR,
 308                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 309                                         | SPI_BIT(MODFDIS)
 310                                         | SPI_BIT(MSTR));
 311                 }
 312
 313                 mr = spi_readl(as, MR);
 314                 gpio_set_value(asd->npcs_pin, active);
 315         } else {
 316                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 317                 int i;
 318                 u32 csr;
 319
 320                 /* Make sure clock polarity is correct */
 321                 for (i = 0; i < spi->master->num_chipselect; i++) {
 322                         csr = spi_readl(as, CSR0 + 4 * i);
 323                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 324                                 spi_writel(as, CSR0 + 4 * i,
 325                                                 csr ^ SPI_BIT(CPOL));
 326                 }
 327
 328                 mr = spi_readl(as, MR);
 329                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 330                 if (spi->chip_select != 0)
 331                         gpio_set_value(asd->npcs_pin, active);
 332                 spi_writel(as, MR, mr);
 333         }
 334
 335         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 336                         asd->npcs_pin, active ? " (high)" : "",
 337                         mr);
 338 }
 339
 340 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 341 {
 342         struct atmel_spi_device *asd = spi->controller_state;
 343         unsigned active = spi->mode & SPI_CS_HIGH;
 344         u32 mr;
 345
 346         /* only deactivate *this* device; sometimes transfers to
 347          * another device may be active when this routine is called.
 348          */
 349         mr = spi_readl(as, MR);
 350         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 351                 mr = SPI_BFINS(PCS, 0xf, mr);
 352                 spi_writel(as, MR, mr);
 353         }
 354
 355         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 356                         asd->npcs_pin, active ? " (low)" : "",
 357                         mr);
 358
 359         if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 360                 gpio_set_value(asd->npcs_pin, !active);
 361 }
 362
 363 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 364 {
 365         spin_lock_irqsave(&as->lock, as->flags);
 366 }
 367
 368 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 369 {
 370         spin_unlock_irqrestore(&as->lock, as->flags);
 371 }
 372
 373 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 374                                 struct spi_transfer *xfer)
 375 {
 376         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 377 }
 378
 379 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 380                                 struct dma_slave_config *slave_config,
 381                                 u8 bits_per_word)
 382 {
 383         int err = 0;
 384
 385         if (bits_per_word > 8) {
 386                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 387                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 388         } else {
 389                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 390                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 391         }
 392
 393         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 394         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 395         slave_config->src_maxburst = 1;
 396         slave_config->dst_maxburst = 1;
 397         slave_config->device_fc = false;
 398
 399         slave_config->direction = DMA_MEM_TO_DEV;
 400         if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
 401                 dev_err(&as->pdev->dev,
 402                         "failed to configure tx dma channel\n");
 403                 err = -EINVAL;
 404         }
 405
 406         slave_config->direction = DMA_DEV_TO_MEM;
 407         if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
 408                 dev_err(&as->pdev->dev,
 409                         "failed to configure rx dma channel\n");
 410                 err = -EINVAL;
 411         }
 412
 413         return err;
 414 }
 415
 416 static bool filter(struct dma_chan *chan, void *pdata)
 417 {
 418         struct atmel_spi_dma *sl_pdata = pdata;
 419         struct at_dma_slave *sl;
 420
 421         if (!sl_pdata)
 422                 return false;
 423
 424         sl = &sl_pdata->dma_slave;
 425         if (sl->dma_dev == chan->device->dev) {
 426                 chan->private = sl;
 427                 return true;
 428         } else {
 429                 return false;
 430         }
 431 }
 432
 433 static int atmel_spi_configure_dma(struct atmel_spi *as)
 434 {
 435         struct dma_slave_config slave_config;
 436         struct device *dev = &as->pdev->dev;
 437         int err;
 438
 439         dma_cap_mask_t mask;
 440         dma_cap_zero(mask);
 441         dma_cap_set(DMA_SLAVE, mask);
 442
 443         as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
 444                                                            &as->dma,
 445                                                            dev, "tx");
 446         if (!as->dma.chan_tx) {
 447                 dev_err(dev,
 448                         "DMA TX channel not available, SPI unable to use DMA\n");
 449                 err = -EBUSY;
 450                 goto error;
 451         }
 452
 453         as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
 454                                                            &as->dma,
 455                                                            dev, "rx");
 456
 457         if (!as->dma.chan_rx) {
 458                 dev_err(dev,
 459                         "DMA RX channel not available, SPI unable to use DMA\n");
 460                 err = -EBUSY;
 461                 goto error;
 462         }
 463
 464         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 465         if (err)
 466                 goto error;
 467
 468         dev_info(&as->pdev->dev,
 469                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 470                         dma_chan_name(as->dma.chan_tx),
 471                         dma_chan_name(as->dma.chan_rx));
 472         return 0;
 473 error:
 474         if (as->dma.chan_rx)
 475                 dma_release_channel(as->dma.chan_rx);
 476         if (as->dma.chan_tx)
 477                 dma_release_channel(as->dma.chan_tx);
 478         return err;
 479 }
 480
 481 static void atmel_spi_stop_dma(struct atmel_spi *as)
 482 {
 483         if (as->dma.chan_rx)
 484                 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
 485                                                         DMA_TERMINATE_ALL, 0);
 486         if (as->dma.chan_tx)
 487                 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
 488                                                         DMA_TERMINATE_ALL, 0);
 489 }
 490
 491 static void atmel_spi_release_dma(struct atmel_spi *as)
 492 {
 493         if (as->dma.chan_rx)
 494                 dma_release_channel(as->dma.chan_rx);
 495         if (as->dma.chan_tx)
 496                 dma_release_channel(as->dma.chan_tx);
 497 }
 498
 499 /* This function is called by the DMA driver from tasklet context */
 500 static void dma_callback(void *data)
 501 {
 502         struct spi_master       *master = data;
 503         struct atmel_spi        *as = spi_master_get_devdata(master);
 504
 505         complete(&as->xfer_completion);
 506 }
 507
 508 /*
 509  * Next transfer using PIO.
 510  */
 511 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 512                                 struct spi_transfer *xfer)
 513 {
 514         struct atmel_spi        *as = spi_master_get_devdata(master);
 515         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 516
 517         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 518
 519         /* Make sure data is not remaining in RDR */
 520         spi_readl(as, RDR);
 521         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 522                 spi_readl(as, RDR);
 523                 cpu_relax();
 524         }
 525
 526         if (xfer->tx_buf) {
 527                 if (xfer->bits_per_word > 8)
 528                         spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 529                 else
 530                         spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 531         } else {
 532                 spi_writel(as, TDR, 0);
 533         }
 534
 535         dev_dbg(master->dev.parent,
 536                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 537                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 538                 xfer->bits_per_word);
 539
 540         /* Enable relevant interrupts */
 541         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 542 }
 543
 544 /*
 545  * Submit next transfer for DMA.
 546  */
 547 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 548                                 struct spi_transfer *xfer,
 549                                 u32 *plen)
 550 {
 551         struct atmel_spi        *as = spi_master_get_devdata(master);
 552         struct dma_chan         *rxchan = as->dma.chan_rx;
 553         struct dma_chan         *txchan = as->dma.chan_tx;
 554         struct dma_async_tx_descriptor *rxdesc;
 555         struct dma_async_tx_descriptor *txdesc;
 556         struct dma_slave_config slave_config;
 557         dma_cookie_t            cookie;
 558         u32     len = *plen;
 559
 560         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 561
 562         /* Check that the channels are available */
 563         if (!rxchan || !txchan)
 564                 return -ENODEV;
 565
 566         /* release lock for DMA operations */
 567         atmel_spi_unlock(as);
 568
 569         /* prepare the RX dma transfer */
 570         sg_init_table(&as->dma.sgrx, 1);
 571         if (xfer->rx_buf) {
 572                 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
 573         } else {
 574                 as->dma.sgrx.dma_address = as->buffer_dma;
 575                 if (len > BUFFER_SIZE)
 576                         len = BUFFER_SIZE;
 577         }
 578
 579         /* prepare the TX dma transfer */
 580         sg_init_table(&as->dma.sgtx, 1);
 581         if (xfer->tx_buf) {
 582                 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
 583         } else {
 584                 as->dma.sgtx.dma_address = as->buffer_dma;
 585                 if (len > BUFFER_SIZE)
 586                         len = BUFFER_SIZE;
 587                 memset(as->buffer, 0, len);
 588         }
 589
 590         sg_dma_len(&as->dma.sgtx) = len;
 591         sg_dma_len(&as->dma.sgrx) = len;
 592
 593         *plen = len;
 594
 595         if (atmel_spi_dma_slave_config(as, &slave_config, 8))
 596                 goto err_exit;
 597
 598         /* Send both scatterlists */
 599         rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
 600                                         &as->dma.sgrx,
 601                                         1,
 602                                         DMA_FROM_DEVICE,
 603                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
 604                                         NULL);
 605         if (!rxdesc)
 606                 goto err_dma;
 607
 608         txdesc = txchan->device->device_prep_slave_sg(txchan,
 609                                         &as->dma.sgtx,
 610                                         1,
 611                                         DMA_TO_DEVICE,
 612                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
 613                                         NULL);
 614         if (!txdesc)
 615                 goto err_dma;
 616
 617         dev_dbg(master->dev.parent,
 618                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 619                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 620                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 621
 622         /* Enable relevant interrupts */
 623         spi_writel(as, IER, SPI_BIT(OVRES));
 624
 625         /* Put the callback on the RX transfer only, that should finish last */
 626         rxdesc->callback = dma_callback;
 627         rxdesc->callback_param = master;
 628
 629         /* Submit and fire RX and TX with TX last so we're ready to read! */
 630         cookie = rxdesc->tx_submit(rxdesc);
 631         if (dma_submit_error(cookie))
 632                 goto err_dma;
 633         cookie = txdesc->tx_submit(txdesc);
 634         if (dma_submit_error(cookie))
 635                 goto err_dma;
 636         rxchan->device->device_issue_pending(rxchan);
 637         txchan->device->device_issue_pending(txchan);
 638
 639         /* take back lock */
 640         atmel_spi_lock(as);
 641         return 0;
 642
 643 err_dma:
 644         spi_writel(as, IDR, SPI_BIT(OVRES));
 645         atmel_spi_stop_dma(as);
 646 err_exit:
 647         atmel_spi_lock(as);
 648         return -ENOMEM;
 649 }
 650
 651 static void atmel_spi_next_xfer_data(struct spi_master *master,
 652                                 struct spi_transfer *xfer,
 653                                 dma_addr_t *tx_dma,
 654                                 dma_addr_t *rx_dma,
 655                                 u32 *plen)
 656 {
 657         struct atmel_spi        *as = spi_master_get_devdata(master);
 658         u32                     len = *plen;
 659
 660         /* use scratch buffer only when rx or tx data is unspecified */
 661         if (xfer->rx_buf)
 662                 *rx_dma = xfer->rx_dma + xfer->len - *plen;
 663         else {
 664                 *rx_dma = as->buffer_dma;
 665                 if (len > BUFFER_SIZE)
 666                         len = BUFFER_SIZE;
 667         }
 668
 669         if (xfer->tx_buf)
 670                 *tx_dma = xfer->tx_dma + xfer->len - *plen;
 671         else {
 672                 *tx_dma = as->buffer_dma;
 673                 if (len > BUFFER_SIZE)
 674                         len = BUFFER_SIZE;
 675                 memset(as->buffer, 0, len);
 676                 dma_sync_single_for_device(&as->pdev->dev,
 677                                 as->buffer_dma, len, DMA_TO_DEVICE);
 678         }
 679
 680         *plen = len;
 681 }
 682
 683 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 684                                     struct spi_device *spi,
 685                                     struct spi_transfer *xfer)
 686 {
 687         u32                     scbr, csr;
 688         unsigned long           bus_hz;
 689
 690         /* v1 chips start out at half the peripheral bus speed. */
 691         bus_hz = clk_get_rate(as->clk);
 692         if (!atmel_spi_is_v2(as))
 693                 bus_hz /= 2;
 694
 695         /*
 696          * Calculate the lowest divider that satisfies the
 697          * constraint, assuming div32/fdiv/mbz == 0.
 698          */
 699         if (xfer->speed_hz)
 700                 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 701         else
 702                 /*
 703                  * This can happend if max_speed is null.
 704                  * In this case, we set the lowest possible speed
 705                  */
 706                 scbr = 0xff;
 707
 708         /*
 709          * If the resulting divider doesn't fit into the
 710          * register bitfield, we can't satisfy the constraint.
 711          */
 712         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 713                 dev_err(&spi->dev,
 714                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 715                         xfer->speed_hz, scbr, bus_hz/255);
 716                 return -EINVAL;
 717         }
 718         if (scbr == 0) {
 719                 dev_err(&spi->dev,
 720                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 721                         xfer->speed_hz, scbr, bus_hz);
 722                 return -EINVAL;
 723         }
 724         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 725         csr = SPI_BFINS(SCBR, scbr, csr);
 726         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 727
 728         return 0;
 729 }
 730
 731 /*
 732  * Submit next transfer for PDC.
 733  * lock is held, spi irq is blocked
 734  */
 735 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 736                                         struct spi_message *msg,
 737                                         struct spi_transfer *xfer)
 738 {
 739         struct atmel_spi        *as = spi_master_get_devdata(master);
 740         u32                     len;
 741         dma_addr_t              tx_dma, rx_dma;
 742
 743         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 744
 745         len = as->current_remaining_bytes;
 746         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 747         as->current_remaining_bytes -= len;
 748
 749         spi_writel(as, RPR, rx_dma);
 750         spi_writel(as, TPR, tx_dma);
 751
 752         if (msg->spi->bits_per_word > 8)
 753                 len >>= 1;
 754         spi_writel(as, RCR, len);
 755         spi_writel(as, TCR, len);
 756
 757         dev_dbg(&msg->spi->dev,
 758                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 759                 xfer, xfer->len, xfer->tx_buf,
 760                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 761                 (unsigned long long)xfer->rx_dma);
 762
 763         if (as->current_remaining_bytes) {
 764                 len = as->current_remaining_bytes;
 765                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 766                 as->current_remaining_bytes -= len;
 767
 768                 spi_writel(as, RNPR, rx_dma);
 769                 spi_writel(as, TNPR, tx_dma);
 770
 771                 if (msg->spi->bits_per_word > 8)
 772                         len >>= 1;
 773                 spi_writel(as, RNCR, len);
 774                 spi_writel(as, TNCR, len);
 775
 776                 dev_dbg(&msg->spi->dev,
 777                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 778                         xfer, xfer->len, xfer->tx_buf,
 779                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 780                         (unsigned long long)xfer->rx_dma);
 781         }
 782
 783         /* REVISIT: We're waiting for ENDRX before we start the next
 784          * transfer because we need to handle some difficult timing
 785          * issues otherwise. If we wait for ENDTX in one transfer and
 786          * then starts waiting for ENDRX in the next, it's difficult
 787          * to tell the difference between the ENDRX interrupt we're
 788          * actually waiting for and the ENDRX interrupt of the
 789          * previous transfer.
 790          *
 791          * It should be doable, though. Just not now...
 792          */
 793         spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
 794         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 795 }
 796
 797 /*
 798  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 799  *  - The buffer is either valid for CPU access, else NULL
 800  *  - If the buffer is valid, so is its DMA address
 801  *
 802  * This driver manages the dma address unless message->is_dma_mapped.
 803  */
 804 static int
 805 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 806 {
 807         struct device   *dev = &as->pdev->dev;
 808
 809         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 810         if (xfer->tx_buf) {
 811                 /* tx_buf is a const void* where we need a void * for the dma
 812                  * mapping */
 813                 void *nonconst_tx = (void *)xfer->tx_buf;
 814
 815                 xfer->tx_dma = dma_map_single(dev,
 816                                 nonconst_tx, xfer->len,
 817                                 DMA_TO_DEVICE);
 818                 if (dma_mapping_error(dev, xfer->tx_dma))
 819                         return -ENOMEM;
 820         }
 821         if (xfer->rx_buf) {
 822                 xfer->rx_dma = dma_map_single(dev,
 823                                 xfer->rx_buf, xfer->len,
 824                                 DMA_FROM_DEVICE);
 825                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 826                         if (xfer->tx_buf)
 827                                 dma_unmap_single(dev,
 828                                                 xfer->tx_dma, xfer->len,
 829                                                 DMA_TO_DEVICE);
 830                         return -ENOMEM;
 831                 }
 832         }
 833         return 0;
 834 }
 835
 836 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 837                                      struct spi_transfer *xfer)
 838 {
 839         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 840                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 841                                  xfer->len, DMA_TO_DEVICE);
 842         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 843                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 844                                  xfer->len, DMA_FROM_DEVICE);
 845 }
 846
 847 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 848 {
 849         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 850 }
 851
 852 /* Called from IRQ
 853  *
 854  * Must update "current_remaining_bytes" to keep track of data
 855  * to transfer.
 856  */
 857 static void
 858 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 859 {
 860         u8              *rxp;
 861         u16             *rxp16;
 862         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
 863
 864         if (xfer->rx_buf) {
 865                 if (xfer->bits_per_word > 8) {
 866                         rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
 867                         *rxp16 = spi_readl(as, RDR);
 868                 } else {
 869                         rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
 870                         *rxp = spi_readl(as, RDR);
 871                 }
 872         } else {
 873                 spi_readl(as, RDR);
 874         }
 875         if (xfer->bits_per_word > 8) {
 876                 as->current_remaining_bytes -= 2;
 877                 if (as->current_remaining_bytes < 0)
 878                         as->current_remaining_bytes = 0;
 879         } else {
 880                 as->current_remaining_bytes--;
 881         }
 882 }
 883
 884 /* Interrupt
 885  *
 886  * No need for locking in this Interrupt handler: done_status is the
 887  * only information modified.
 888  */
 889 static irqreturn_t
 890 atmel_spi_pio_interrupt(int irq, void *dev_id)
 891 {
 892         struct spi_master       *master = dev_id;
 893         struct atmel_spi        *as = spi_master_get_devdata(master);
 894         u32                     status, pending, imr;
 895         struct spi_transfer     *xfer;
 896         int                     ret = IRQ_NONE;
 897
 898         imr = spi_readl(as, IMR);
 899         status = spi_readl(as, SR);
 900         pending = status & imr;
 901
 902         if (pending & SPI_BIT(OVRES)) {
 903                 ret = IRQ_HANDLED;
 904                 spi_writel(as, IDR, SPI_BIT(OVRES));
 905                 dev_warn(master->dev.parent, "overrun\n");
 906
 907                 /*
 908                  * When we get an overrun, we disregard the current
 909                  * transfer. Data will not be copied back from any
 910                  * bounce buffer and msg->actual_len will not be
 911                  * updated with the last xfer.
 912                  *
 913                  * We will also not process any remaning transfers in
 914                  * the message.
 915                  */
 916                 as->done_status = -EIO;
 917                 smp_wmb();
 918
 919                 /* Clear any overrun happening while cleaning up */
 920                 spi_readl(as, SR);
 921
 922                 complete(&as->xfer_completion);
 923
 924         } else if (pending & SPI_BIT(RDRF)) {
 925                 atmel_spi_lock(as);
 926
 927                 if (as->current_remaining_bytes) {
 928                         ret = IRQ_HANDLED;
 929                         xfer = as->current_transfer;
 930                         atmel_spi_pump_pio_data(as, xfer);
 931                         if (!as->current_remaining_bytes)
 932                                 spi_writel(as, IDR, pending);
 933
 934                         complete(&as->xfer_completion);
 935                 }
 936
 937                 atmel_spi_unlock(as);
 938         } else {
 939                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
 940                 ret = IRQ_HANDLED;
 941                 spi_writel(as, IDR, pending);
 942         }
 943
 944         return ret;
 945 }
 946
 947 static irqreturn_t
 948 atmel_spi_pdc_interrupt(int irq, void *dev_id)
 949 {
 950         struct spi_master       *master = dev_id;
 951         struct atmel_spi        *as = spi_master_get_devdata(master);
 952         u32                     status, pending, imr;
 953         int                     ret = IRQ_NONE;
 954
 955         imr = spi_readl(as, IMR);
 956         status = spi_readl(as, SR);
 957         pending = status & imr;
 958
 959         if (pending & SPI_BIT(OVRES)) {
 960
 961                 ret = IRQ_HANDLED;
 962
 963                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
 964                                      | SPI_BIT(OVRES)));
 965
 966                 /* Clear any overrun happening while cleaning up */
 967                 spi_readl(as, SR);
 968
 969                 as->done_status = -EIO;
 970
 971                 complete(&as->xfer_completion);
 972
 973         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 974                 ret = IRQ_HANDLED;
 975
 976                 spi_writel(as, IDR, pending);
 977
 978                 complete(&as->xfer_completion);
 979         }
 980
 981         return ret;
 982 }
 983
 984 static int atmel_spi_setup(struct spi_device *spi)
 985 {
 986         struct atmel_spi        *as;
 987         struct atmel_spi_device *asd;
 988         u32                     csr;
 989         unsigned int            bits = spi->bits_per_word;
 990         unsigned int            npcs_pin;
 991         int                     ret;
 992
 993         as = spi_master_get_devdata(spi->master);
 994
 995         if (spi->chip_select > spi->master->num_chipselect) {
 996                 dev_dbg(&spi->dev,
 997                                 "setup: invalid chipselect %u (%u defined)\n",
 998                                 spi->chip_select, spi->master->num_chipselect);
 999                 return -EINVAL;
1000         }
1001
1002         /* see notes above re chipselect */
1003         if (!atmel_spi_is_v2(as)
1004                         && spi->chip_select == 0
1005                         && (spi->mode & SPI_CS_HIGH)) {
1006                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1007                 return -EINVAL;
1008         }
1009
1010         csr = SPI_BF(BITS, bits - 8);
1011         if (spi->mode & SPI_CPOL)
1012                 csr |= SPI_BIT(CPOL);
1013         if (!(spi->mode & SPI_CPHA))
1014                 csr |= SPI_BIT(NCPHA);
1015
1016         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1017          *
1018          * DLYBCT would add delays between words, slowing down transfers.
1019          * It could potentially be useful to cope with DMA bottlenecks, but
1020          * in those cases it's probably best to just use a lower bitrate.
1021          */
1022         csr |= SPI_BF(DLYBS, 0);
1023         csr |= SPI_BF(DLYBCT, 0);
1024
1025         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1026         npcs_pin = (unsigned int)spi->controller_data;
1027
1028         if (gpio_is_valid(spi->cs_gpio))
1029                 npcs_pin = spi->cs_gpio;
1030
1031         asd = spi->controller_state;
1032         if (!asd) {
1033                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1034                 if (!asd)
1035                         return -ENOMEM;
1036
1037                 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1038                 if (ret) {
1039                         kfree(asd);
1040                         return ret;
1041                 }
1042
1043                 asd->npcs_pin = npcs_pin;
1044                 spi->controller_state = asd;
1045                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1046         }
1047
1048         asd->csr = csr;
1049
1050         dev_dbg(&spi->dev,
1051                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1052                 bits, spi->mode, spi->chip_select, csr);
1053
1054         if (!atmel_spi_is_v2(as))
1055                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1056
1057         return 0;
1058 }
1059
1060 static int atmel_spi_one_transfer(struct spi_master *master,
1061                                         struct spi_message *msg,
1062                                         struct spi_transfer *xfer)
1063 {
1064         struct atmel_spi        *as;
1065         struct spi_device       *spi = msg->spi;
1066         u8                      bits;
1067         u32                     len;
1068         struct atmel_spi_device *asd;
1069         int                     timeout;
1070         int                     ret;
1071
1072         as = spi_master_get_devdata(master);
1073
1074         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1075                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1076                 return -EINVAL;
1077         }
1078
1079         if (xfer->bits_per_word) {
1080                 asd = spi->controller_state;
1081                 bits = (asd->csr >> 4) & 0xf;
1082                 if (bits != xfer->bits_per_word - 8) {
1083                         dev_dbg(&spi->dev,
1084                         "you can't yet change bits_per_word in transfers\n");
1085                         return -ENOPROTOOPT;
1086                 }
1087         }
1088
1089         if (xfer->bits_per_word > 8) {
1090                 if (xfer->len % 2) {
1091                         dev_dbg(&spi->dev,
1092                         "buffer len should be 16 bits aligned\n");
1093                         return -EINVAL;
1094                 }
1095         }
1096
1097         /*
1098          * DMA map early, for performance (empties dcache ASAP) and
1099          * better fault reporting.
1100          */
1101         if ((!msg->is_dma_mapped)
1102                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1103                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1104                         return -ENOMEM;
1105         }
1106
1107         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1108
1109         as->done_status = 0;
1110         as->current_transfer = xfer;
1111         as->current_remaining_bytes = xfer->len;
1112         while (as->current_remaining_bytes) {
1113                 reinit_completion(&as->xfer_completion);
1114
1115                 if (as->use_pdc) {
1116                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1117                 } else if (atmel_spi_use_dma(as, xfer)) {
1118                         len = as->current_remaining_bytes;
1119                         ret = atmel_spi_next_xfer_dma_submit(master,
1120                                                                 xfer, &len);
1121                         if (ret) {
1122                                 dev_err(&spi->dev,
1123                                         "unable to use DMA, fallback to PIO\n");
1124                                 atmel_spi_next_xfer_pio(master, xfer);
1125                         } else {
1126                                 as->current_remaining_bytes -= len;
1127                         }
1128                 } else {
1129                         atmel_spi_next_xfer_pio(master, xfer);
1130                 }
1131
1132                 ret = wait_for_completion_timeout(&as->xfer_completion,
1133                                                         SPI_DMA_TIMEOUT);
1134                 if (WARN_ON(ret == 0)) {
1135                         dev_err(&spi->dev,
1136                                 "spi trasfer timeout, err %d\n", ret);
1137                         as->done_status = -EIO;
1138                 } else {
1139                         ret = 0;
1140                 }
1141
1142                 if (as->done_status)
1143                         break;
1144         }
1145
1146         if (as->done_status) {
1147                 if (as->use_pdc) {
1148                         dev_warn(master->dev.parent,
1149                                 "overrun (%u/%u remaining)\n",
1150                                 spi_readl(as, TCR), spi_readl(as, RCR));
1151
1152                         /*
1153                          * Clean up DMA registers and make sure the data
1154                          * registers are empty.
1155                          */
1156                         spi_writel(as, RNCR, 0);
1157                         spi_writel(as, TNCR, 0);
1158                         spi_writel(as, RCR, 0);
1159                         spi_writel(as, TCR, 0);
1160                         for (timeout = 1000; timeout; timeout--)
1161                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1162                                         break;
1163                         if (!timeout)
1164                                 dev_warn(master->dev.parent,
1165                                          "timeout waiting for TXEMPTY");
1166                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1167                                 spi_readl(as, RDR);
1168
1169                         /* Clear any overrun happening while cleaning up */
1170                         spi_readl(as, SR);
1171
1172                 } else if (atmel_spi_use_dma(as, xfer)) {
1173                         atmel_spi_stop_dma(as);
1174                 }
1175
1176                 if (!msg->is_dma_mapped
1177                         && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1178                         atmel_spi_dma_unmap_xfer(master, xfer);
1179
1180                 return 0;
1181
1182         } else {
1183                 /* only update length if no error */
1184                 msg->actual_length += xfer->len;
1185         }
1186
1187         if (!msg->is_dma_mapped
1188                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1189                 atmel_spi_dma_unmap_xfer(master, xfer);
1190
1191         if (xfer->delay_usecs)
1192                 udelay(xfer->delay_usecs);
1193
1194         if (xfer->cs_change) {
1195                 if (list_is_last(&xfer->transfer_list,
1196                                  &msg->transfers)) {
1197                         as->keep_cs = true;
1198                 } else {
1199                         as->cs_active = !as->cs_active;
1200                         if (as->cs_active)
1201                                 cs_activate(as, msg->spi);
1202                         else
1203                                 cs_deactivate(as, msg->spi);
1204                 }
1205         }
1206
1207         return 0;
1208 }
1209
1210 static int atmel_spi_transfer_one_message(struct spi_master *master,
1211                                                 struct spi_message *msg)
1212 {
1213         struct atmel_spi *as;
1214         struct spi_transfer *xfer;
1215         struct spi_device *spi = msg->spi;
1216         int ret = 0;
1217
1218         as = spi_master_get_devdata(master);
1219
1220         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1221                                         msg, dev_name(&spi->dev));
1222
1223         if (unlikely(list_empty(&msg->transfers)))
1224                 return -EINVAL;
1225
1226         atmel_spi_lock(as);
1227         cs_activate(as, spi);
1228
1229         as->cs_active = true;
1230         as->keep_cs = false;
1231
1232         msg->status = 0;
1233         msg->actual_length = 0;
1234
1235         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1236                 ret = atmel_spi_one_transfer(master, msg, xfer);
1237                 if (ret)
1238                         goto msg_done;
1239         }
1240
1241         if (as->use_pdc)
1242                 atmel_spi_disable_pdc_transfer(as);
1243
1244         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1245                 dev_dbg(&spi->dev,
1246                         "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
1247                         xfer, xfer->len,
1248                         xfer->tx_buf, xfer->tx_dma,
1249                         xfer->rx_buf, xfer->rx_dma);
1250         }
1251
1252 msg_done:
1253         if (!as->keep_cs)
1254                 cs_deactivate(as, msg->spi);
1255
1256         atmel_spi_unlock(as);
1257
1258         msg->status = as->done_status;
1259         spi_finalize_current_message(spi->master);
1260
1261         return ret;
1262 }
1263
1264 static void atmel_spi_cleanup(struct spi_device *spi)
1265 {
1266         struct atmel_spi_device *asd = spi->controller_state;
1267         unsigned                gpio = (unsigned) spi->controller_data;
1268
1269         if (!asd)
1270                 return;
1271
1272         spi->controller_state = NULL;
1273         gpio_free(gpio);
1274         kfree(asd);
1275 }
1276
1277 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1278 {
1279         return spi_readl(as, VERSION) & 0x00000fff;
1280 }
1281
1282 static void atmel_get_caps(struct atmel_spi *as)
1283 {
1284         unsigned int version;
1285
1286         version = atmel_get_version(as);
1287         dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1288
1289         as->caps.is_spi2 = version > 0x121;
1290         as->caps.has_wdrbt = version >= 0x210;
1291         as->caps.has_dma_support = version >= 0x212;
1292 }
1293
1294 /*-------------------------------------------------------------------------*/
1295
1296 static int atmel_spi_probe(struct platform_device *pdev)
1297 {
1298         struct resource         *regs;
1299         int                     irq;
1300         struct clk              *clk;
1301         int                     ret;
1302         struct spi_master       *master;
1303         struct atmel_spi        *as;
1304
1305         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306         if (!regs)
1307                 return -ENXIO;
1308
1309         irq = platform_get_irq(pdev, 0);
1310         if (irq < 0)
1311                 return irq;
1312
1313         clk = devm_clk_get(&pdev->dev, "spi_clk");
1314         if (IS_ERR(clk))
1315                 return PTR_ERR(clk);
1316
1317         /* setup spi core then atmel-specific driver state */
1318         ret = -ENOMEM;
1319         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1320         if (!master)
1321                 goto out_free;
1322
1323         /* the spi->mode bits understood by this driver: */
1324         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1325         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1326         master->dev.of_node = pdev->dev.of_node;
1327         master->bus_num = pdev->id;
1328         master->num_chipselect = master->dev.of_node ? 0 : 4;
1329         master->setup = atmel_spi_setup;
1330         master->transfer_one_message = atmel_spi_transfer_one_message;
1331         master->cleanup = atmel_spi_cleanup;
1332         platform_set_drvdata(pdev, master);
1333
1334         as = spi_master_get_devdata(master);
1335
1336         /*
1337          * Scratch buffer is used for throwaway rx and tx data.
1338          * It's coherent to minimize dcache pollution.
1339          */
1340         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1341                                         &as->buffer_dma, GFP_KERNEL);
1342         if (!as->buffer)
1343                 goto out_free;
1344
1345         spin_lock_init(&as->lock);
1346
1347         as->pdev = pdev;
1348         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1349         if (IS_ERR(as->regs)) {
1350                 ret = PTR_ERR(as->regs);
1351                 goto out_free_buffer;
1352         }
1353         as->phybase = regs->start;
1354         as->irq = irq;
1355         as->clk = clk;
1356
1357         init_completion(&as->xfer_completion);
1358
1359         atmel_get_caps(as);
1360
1361         as->use_dma = false;
1362         as->use_pdc = false;
1363         if (as->caps.has_dma_support) {
1364                 if (atmel_spi_configure_dma(as) == 0)
1365                         as->use_dma = true;
1366         } else {
1367                 as->use_pdc = true;
1368         }
1369
1370         if (as->caps.has_dma_support && !as->use_dma)
1371                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1372
1373         if (as->use_pdc) {
1374                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1375                                         0, dev_name(&pdev->dev), master);
1376         } else {
1377                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1378                                         0, dev_name(&pdev->dev), master);
1379         }
1380         if (ret)
1381                 goto out_unmap_regs;
1382
1383         /* Initialize the hardware */
1384         ret = clk_prepare_enable(clk);
1385         if (ret)
1386                 goto out_free_irq;
1387         spi_writel(as, CR, SPI_BIT(SWRST));
1388         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1389         if (as->caps.has_wdrbt) {
1390                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1391                                 | SPI_BIT(MSTR));
1392         } else {
1393                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1394         }
1395
1396         if (as->use_pdc)
1397                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1398         spi_writel(as, CR, SPI_BIT(SPIEN));
1399
1400         /* go! */
1401         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1402                         (unsigned long)regs->start, irq);
1403
1404         ret = devm_spi_register_master(&pdev->dev, master);
1405         if (ret)
1406                 goto out_free_dma;
1407
1408         return 0;
1409
1410 out_free_dma:
1411         if (as->use_dma)
1412                 atmel_spi_release_dma(as);
1413
1414         spi_writel(as, CR, SPI_BIT(SWRST));
1415         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1416         clk_disable_unprepare(clk);
1417 out_free_irq:
1418 out_unmap_regs:
1419 out_free_buffer:
1420         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1421                         as->buffer_dma);
1422 out_free:
1423         spi_master_put(master);
1424         return ret;
1425 }
1426
1427 static int atmel_spi_remove(struct platform_device *pdev)
1428 {
1429         struct spi_master       *master = platform_get_drvdata(pdev);
1430         struct atmel_spi        *as = spi_master_get_devdata(master);
1431
1432         /* reset the hardware and block queue progress */
1433         spin_lock_irq(&as->lock);
1434         if (as->use_dma) {
1435                 atmel_spi_stop_dma(as);
1436                 atmel_spi_release_dma(as);
1437         }
1438
1439         spi_writel(as, CR, SPI_BIT(SWRST));
1440         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1441         spi_readl(as, SR);
1442         spin_unlock_irq(&as->lock);
1443
1444         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1445                         as->buffer_dma);
1446
1447         clk_disable_unprepare(as->clk);
1448
1449         return 0;
1450 }
1451
1452 #ifdef CONFIG_PM_SLEEP
1453 static int atmel_spi_suspend(struct device *dev)
1454 {
1455         struct spi_master       *master = dev_get_drvdata(dev);
1456         struct atmel_spi        *as = spi_master_get_devdata(master);
1457         int ret;
1458
1459         /* Stop the queue running */
1460         ret = spi_master_suspend(master);
1461         if (ret) {
1462                 dev_warn(dev, "cannot suspend master\n");
1463                 return ret;
1464         }
1465
1466         clk_disable_unprepare(as->clk);
1467         return 0;
1468 }
1469
1470 static int atmel_spi_resume(struct device *dev)
1471 {
1472         struct spi_master       *master = dev_get_drvdata(dev);
1473         struct atmel_spi        *as = spi_master_get_devdata(master);
1474         int ret;
1475
1476         clk_prepare_enable(as->clk);
1477
1478         /* Start the queue running */
1479         ret = spi_master_resume(master);
1480         if (ret)
1481                 dev_err(dev, "problem starting queue (%d)\n", ret);
1482
1483         return ret;
1484 }
1485
1486 static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
1487
1488 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1489 #else
1490 #define ATMEL_SPI_PM_OPS        NULL
1491 #endif
1492
1493 #if defined(CONFIG_OF)
1494 static const struct of_device_id atmel_spi_dt_ids[] = {
1495         { .compatible = "atmel,at91rm9200-spi" },
1496         { /* sentinel */ }
1497 };
1498
1499 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1500 #endif
1501
1502 static struct platform_driver atmel_spi_driver = {
1503         .driver         = {
1504                 .name   = "atmel_spi",
1505                 .owner  = THIS_MODULE,
1506                 .pm     = ATMEL_SPI_PM_OPS,
1507                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1508         },
1509         .probe          = atmel_spi_probe,
1510         .remove         = atmel_spi_remove,
1511 };
1512 module_platform_driver(atmel_spi_driver);
1513
1514 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1515 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1516 MODULE_LICENSE("GPL");
1517 MODULE_ALIAS("platform:atmel_spi");