1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ASPEED FMC/SPI Memory Controller Driver
5 * Copyright (c) 2015-2022, IBM Corporation.
6 * Copyright (c) 2020, ASPEED Corporation.
10 #include <linux/module.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/spi-mem.h>
17 #define DEVICE_NAME "spi-aspeed-smc"
19 /* Type setting Register */
20 #define CONFIG_REG 0x0
21 #define CONFIG_TYPE_SPI 0x2
23 /* CE Control Register */
24 #define CE_CTRL_REG 0x4
26 /* CEx Control Register */
27 #define CE0_CTRL_REG 0x10
28 #define CTRL_IO_MODE_MASK GENMASK(30, 28)
29 #define CTRL_IO_SINGLE_DATA 0x0
30 #define CTRL_IO_DUAL_DATA BIT(29)
31 #define CTRL_IO_QUAD_DATA BIT(30)
32 #define CTRL_COMMAND_SHIFT 16
33 #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
34 #define CTRL_IO_DUMMY_SET(dummy) \
35 (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
36 #define CTRL_FREQ_SEL_SHIFT 8
37 #define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
38 #define CTRL_CE_STOP_ACTIVE BIT(2)
39 #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
40 #define CTRL_IO_MODE_NORMAL 0x0
41 #define CTRL_IO_MODE_READ 0x1
42 #define CTRL_IO_MODE_WRITE 0x2
43 #define CTRL_IO_MODE_USER 0x3
45 #define CTRL_IO_CMD_MASK 0xf0ff40c3
47 /* CEx Address Decoding Range Register */
48 #define CE0_SEGMENT_ADDR_REG 0x30
50 /* CEx Read timing compensation register */
51 #define CE0_TIMING_COMPENSATION_REG 0x94
53 enum aspeed_spi_ctl_reg_value {
62 struct aspeed_spi_chip {
63 struct aspeed_spi *aspi;
66 void __iomem *ahb_base;
68 u32 ctl_val[ASPEED_SPI_MAX];
72 struct aspeed_spi_data {
82 u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
83 u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
84 u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
85 int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
86 const u8 *golden_buf, u8 *test_buf);
89 #define ASPEED_SPI_MAX_NUM_CS 5
92 const struct aspeed_spi_data *data;
95 void __iomem *ahb_base;
103 struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
106 static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
108 switch (op->data.buswidth) {
110 return CTRL_IO_SINGLE_DATA;
112 return CTRL_IO_DUAL_DATA;
114 return CTRL_IO_QUAD_DATA;
116 return CTRL_IO_SINGLE_DATA;
120 static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
125 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
127 writel(ctl, chip->ctl);
131 static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
133 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
135 ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
136 writel(ctl, chip->ctl);
138 ctl &= ~CTRL_CE_STOP_ACTIVE;
139 writel(ctl, chip->ctl);
142 static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
144 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
145 CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
147 writel(ctl, chip->ctl);
149 /* Restore defaults */
150 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
153 static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
157 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
158 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
159 ioread32_rep(src, buf, len >> 2);
163 ioread8_rep(src, (u8 *)buf + offset, len);
167 static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
171 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
172 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
173 iowrite32_rep(dst, buf, len >> 2);
177 iowrite8_rep(dst, (const u8 *)buf + offset, len);
181 static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
182 u64 offset, u32 opcode)
187 switch (addr_nbytes) {
189 cmdaddr = offset & 0xFFFFFF;
190 cmdaddr |= opcode << 24;
192 temp = cpu_to_be32(cmdaddr);
193 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
196 temp = cpu_to_be32(offset);
197 aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
198 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
201 WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
207 static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
208 const struct spi_mem_op *op)
210 aspeed_spi_start_user(chip);
211 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
212 aspeed_spi_read_from_ahb(op->data.buf.in,
213 chip->ahb_base, op->data.nbytes);
214 aspeed_spi_stop_user(chip);
218 static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
219 const struct spi_mem_op *op)
221 aspeed_spi_start_user(chip);
222 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
223 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
225 aspeed_spi_stop_user(chip);
229 static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
230 const struct spi_mem_op *op,
231 u64 offset, size_t len, void *buf)
233 int io_mode = aspeed_spi_get_io_mode(op);
238 aspeed_spi_start_user(chip);
240 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
244 if (op->dummy.buswidth && op->dummy.nbytes) {
245 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
246 aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
249 aspeed_spi_set_io_mode(chip, io_mode);
251 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
252 aspeed_spi_stop_user(chip);
256 static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
257 const struct spi_mem_op *op)
261 aspeed_spi_start_user(chip);
262 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
265 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
266 aspeed_spi_stop_user(chip);
270 /* support for 1-1-1, 1-1-2 or 1-1-4 */
271 static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
273 if (op->cmd.buswidth > 1)
276 if (op->addr.nbytes != 0) {
277 if (op->addr.buswidth > 1)
279 if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
283 if (op->dummy.nbytes != 0) {
284 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
288 if (op->data.nbytes != 0 && op->data.buswidth > 4)
291 return spi_mem_default_supports_op(mem, op);
294 static const struct aspeed_spi_data ast2400_spi_data;
296 static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
298 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
299 struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
300 u32 addr_mode, addr_mode_backup;
305 "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
306 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
307 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
308 op->dummy.buswidth, op->data.buswidth,
309 op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
311 addr_mode = readl(aspi->regs + CE_CTRL_REG);
312 addr_mode_backup = addr_mode;
314 ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
315 ctl_val &= ~CTRL_IO_CMD_MASK;
317 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
319 /* 4BYTE address mode */
320 if (op->addr.nbytes) {
321 if (op->addr.nbytes == 4)
322 addr_mode |= (0x11 << chip->cs);
324 addr_mode &= ~(0x11 << chip->cs);
326 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
327 ctl_val |= CTRL_IO_ADDRESS_4B;
330 if (op->dummy.nbytes)
331 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
334 ctl_val |= aspeed_spi_get_io_mode(op);
336 if (op->data.dir == SPI_MEM_DATA_OUT)
337 ctl_val |= CTRL_IO_MODE_WRITE;
339 ctl_val |= CTRL_IO_MODE_READ;
341 if (addr_mode != addr_mode_backup)
342 writel(addr_mode, aspi->regs + CE_CTRL_REG);
343 writel(ctl_val, chip->ctl);
345 if (op->data.dir == SPI_MEM_DATA_IN) {
346 if (!op->addr.nbytes)
347 ret = aspeed_spi_read_reg(chip, op);
349 ret = aspeed_spi_read_user(chip, op, op->addr.val,
350 op->data.nbytes, op->data.buf.in);
352 if (!op->addr.nbytes)
353 ret = aspeed_spi_write_reg(chip, op);
355 ret = aspeed_spi_write_user(chip, op);
358 /* Restore defaults */
359 if (addr_mode != addr_mode_backup)
360 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
361 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
365 static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
369 ret = do_aspeed_spi_exec_op(mem, op);
371 dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
375 static const char *aspeed_spi_get_name(struct spi_mem *mem)
377 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
378 struct device *dev = aspi->dev;
380 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
383 struct aspeed_spi_window {
389 static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
390 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
392 const struct aspeed_spi_data *data = aspi->data;
396 for (cs = 0; cs < aspi->data->max_cs; cs++) {
397 reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
399 windows[cs].size = data->segment_end(aspi, reg_val) -
400 data->segment_start(aspi, reg_val);
401 windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
402 dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
403 windows[cs].offset, windows[cs].size);
408 * On the AST2600, some CE windows are closed by default at reset but
409 * U-Boot should open all.
411 static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
413 struct aspeed_spi *aspi = chip->aspi;
414 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
415 struct aspeed_spi_window *win = &windows[chip->cs];
417 /* No segment registers for the AST2400 SPI controller */
418 if (aspi->data == &ast2400_spi_data) {
420 win->size = aspi->ahb_window_size;
422 aspeed_spi_get_windows(aspi, windows);
425 chip->ahb_base = aspi->ahb_base + win->offset;
426 chip->ahb_window_size = win->size;
428 dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
429 chip->cs, aspi->ahb_base_phy + win->offset,
430 aspi->ahb_base_phy + win->offset + win->size - 1,
433 return chip->ahb_window_size ? 0 : -1;
436 static int aspeed_spi_set_window(struct aspeed_spi *aspi,
437 const struct aspeed_spi_window *win)
439 u32 start = aspi->ahb_base_phy + win->offset;
440 u32 end = start + win->size;
441 void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
442 u32 seg_val_backup = readl(seg_reg);
443 u32 seg_val = aspi->data->segment_reg(aspi, start, end);
445 if (seg_val == seg_val_backup)
448 writel(seg_val, seg_reg);
451 * Restore initial value if something goes wrong else we could
452 * loose access to the chip.
454 if (seg_val != readl(seg_reg)) {
455 dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
456 win->cs, start, end - 1, win->size >> 20);
457 writel(seg_val_backup, seg_reg);
462 dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
463 win->cs, start, end - 1, win->size >> 20);
465 dev_dbg(aspi->dev, "CE%d window closed", win->cs);
471 * Yet to be done when possible :
472 * - Align mappings on flash size (we don't have the info)
473 * - ioremap each window, not strictly necessary since the overall window
476 static const struct aspeed_spi_data ast2500_spi_data;
477 static const struct aspeed_spi_data ast2600_spi_data;
478 static const struct aspeed_spi_data ast2600_fmc_data;
480 static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
481 u32 local_offset, u32 size)
483 struct aspeed_spi *aspi = chip->aspi;
484 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
485 struct aspeed_spi_window *win = &windows[chip->cs];
488 /* No segment registers for the AST2400 SPI controller */
489 if (aspi->data == &ast2400_spi_data)
493 * Due to an HW issue on the AST2500 SPI controller, the CE0
494 * window size should be smaller than the maximum 128MB.
496 if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
498 dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
499 chip->cs, size >> 20);
503 * The decoding size of AST2600 SPI controller should set at
506 if ((aspi->data == &ast2600_spi_data || aspi->data == &ast2600_fmc_data) &&
509 dev_info(aspi->dev, "CE%d window resized to %dMB (AST2600 Decoding)",
510 chip->cs, size >> 20);
513 aspeed_spi_get_windows(aspi, windows);
515 /* Adjust this chip window */
516 win->offset += local_offset;
519 if (win->offset + win->size > aspi->ahb_window_size) {
520 win->size = aspi->ahb_window_size - win->offset;
521 dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
524 ret = aspeed_spi_set_window(aspi, win);
528 /* Update chip mapping info */
529 chip->ahb_base = aspi->ahb_base + win->offset;
530 chip->ahb_window_size = win->size;
533 * Also adjust next chip window to make sure that it does not
534 * overlap with the current window.
536 if (chip->cs < aspi->data->max_cs - 1) {
537 struct aspeed_spi_window *next = &windows[chip->cs + 1];
539 /* Change offset and size to keep the same end address */
540 if ((next->offset + next->size) > (win->offset + win->size))
541 next->size = (next->offset + next->size) - (win->offset + win->size);
544 next->offset = win->offset + win->size;
546 aspeed_spi_set_window(aspi, next);
551 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
553 static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
555 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
556 struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
557 struct spi_mem_op *op = &desc->info.op_tmpl;
562 "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n",
563 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
564 desc->info.offset, desc->info.offset + desc->info.length,
565 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
566 op->dummy.buswidth, op->data.buswidth,
567 op->addr.nbytes, op->dummy.nbytes);
569 chip->clk_freq = desc->mem->spi->max_speed_hz;
572 if (op->data.dir != SPI_MEM_DATA_IN)
575 aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
577 if (desc->info.length > chip->ahb_window_size)
578 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
579 chip->cs, chip->ahb_window_size >> 20);
581 /* Define the default IO read settings */
582 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
583 ctl_val |= aspeed_spi_get_io_mode(op) |
584 op->cmd.opcode << CTRL_COMMAND_SHIFT |
587 if (op->dummy.nbytes)
588 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
590 /* Tune 4BYTE address mode */
591 if (op->addr.nbytes) {
592 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
594 if (op->addr.nbytes == 4)
595 addr_mode |= (0x11 << chip->cs);
597 addr_mode &= ~(0x11 << chip->cs);
598 writel(addr_mode, aspi->regs + CE_CTRL_REG);
600 /* AST2400 SPI controller sets 4BYTE address mode in
601 * CE0 Control Register
603 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
604 ctl_val |= CTRL_IO_ADDRESS_4B;
607 /* READ mode is the controller default setting */
608 chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
609 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
611 ret = aspeed_spi_do_calibration(chip);
613 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
614 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
619 static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
620 u64 offset, size_t len, void *buf)
622 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
623 struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
625 /* Switch to USER command mode if mapping window is too small */
626 if (chip->ahb_window_size < offset + len) {
629 ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
633 memcpy_fromio(buf, chip->ahb_base + offset, len);
639 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
640 .supports_op = aspeed_spi_supports_op,
641 .exec_op = aspeed_spi_exec_op,
642 .get_name = aspeed_spi_get_name,
643 .dirmap_create = aspeed_spi_dirmap_create,
644 .dirmap_read = aspeed_spi_dirmap_read,
647 static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
651 reg = readl(aspi->regs + CONFIG_REG);
652 reg &= ~(0x3 << (cs * 2));
653 reg |= type << (cs * 2);
654 writel(reg, aspi->regs + CONFIG_REG);
657 static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
659 u32 we_bit = BIT(aspi->data->we0 + cs);
660 u32 reg = readl(aspi->regs + CONFIG_REG);
666 writel(reg, aspi->regs + CONFIG_REG);
669 static int aspeed_spi_setup(struct spi_device *spi)
671 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
672 const struct aspeed_spi_data *data = aspi->data;
673 unsigned int cs = spi->chip_select;
674 struct aspeed_spi_chip *chip = &aspi->chips[cs];
678 chip->ctl = aspi->regs + data->ctl0 + cs * 4;
680 /* The driver only supports SPI type flash */
682 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
684 if (aspeed_spi_chip_set_default_window(chip) < 0) {
685 dev_warn(aspi->dev, "CE%d window invalid", cs);
689 aspeed_spi_chip_enable(aspi, cs, true);
691 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
693 dev_dbg(aspi->dev, "CE%d setup done\n", cs);
697 static void aspeed_spi_cleanup(struct spi_device *spi)
699 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
700 unsigned int cs = spi->chip_select;
702 aspeed_spi_chip_enable(aspi, cs, false);
704 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
707 static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
711 for (cs = 0; cs < aspi->data->max_cs; cs++)
712 aspeed_spi_chip_enable(aspi, cs, enable);
715 static int aspeed_spi_probe(struct platform_device *pdev)
717 struct device *dev = &pdev->dev;
718 const struct aspeed_spi_data *data;
719 struct spi_controller *ctlr;
720 struct aspeed_spi *aspi;
721 struct resource *res;
724 data = of_device_get_match_data(&pdev->dev);
728 ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
732 aspi = spi_controller_get_devdata(ctlr);
733 platform_set_drvdata(pdev, aspi);
737 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
738 aspi->regs = devm_ioremap_resource(dev, res);
739 if (IS_ERR(aspi->regs))
740 return PTR_ERR(aspi->regs);
742 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
743 aspi->ahb_base = devm_ioremap_resource(dev, res);
744 if (IS_ERR(aspi->ahb_base)) {
745 dev_err(dev, "missing AHB mapping window\n");
746 return PTR_ERR(aspi->ahb_base);
749 aspi->ahb_window_size = resource_size(res);
750 aspi->ahb_base_phy = res->start;
752 aspi->clk = devm_clk_get(&pdev->dev, NULL);
753 if (IS_ERR(aspi->clk)) {
754 dev_err(dev, "missing clock\n");
755 return PTR_ERR(aspi->clk);
758 aspi->clk_freq = clk_get_rate(aspi->clk);
759 if (!aspi->clk_freq) {
760 dev_err(dev, "invalid clock\n");
764 ret = clk_prepare_enable(aspi->clk);
766 dev_err(dev, "can not enable the clock\n");
770 /* IRQ is for DMA, which the driver doesn't support yet */
772 ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
773 ctlr->bus_num = pdev->id;
774 ctlr->mem_ops = &aspeed_spi_mem_ops;
775 ctlr->setup = aspeed_spi_setup;
776 ctlr->cleanup = aspeed_spi_cleanup;
777 ctlr->num_chipselect = data->max_cs;
778 ctlr->dev.of_node = dev->of_node;
780 ret = devm_spi_register_controller(dev, ctlr);
782 dev_err(&pdev->dev, "spi_register_controller failed\n");
788 clk_disable_unprepare(aspi->clk);
792 static int aspeed_spi_remove(struct platform_device *pdev)
794 struct aspeed_spi *aspi = platform_get_drvdata(pdev);
796 aspeed_spi_enable(aspi, false);
797 clk_disable_unprepare(aspi->clk);
806 * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
807 * The address range is encoded with absolute addresses in the overall
810 static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
812 return ((reg >> 16) & 0xFF) << 23;
815 static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
817 return ((reg >> 24) & 0xFF) << 23;
820 static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
822 return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
826 * The Segment Registers of the AST2600 use a 1MB unit. The address
827 * range is encoded with offsets in the overall mapping window.
830 #define AST2600_SEG_ADDR_MASK 0x0ff00000
832 static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
835 u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
837 return aspi->ahb_base_phy + start_offset;
840 static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
843 u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
845 /* segment is disabled */
847 return aspi->ahb_base_phy;
849 return aspi->ahb_base_phy + end_offset + 0x100000;
852 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
855 /* disable zero size segments */
859 return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
860 ((end - 1) & AST2600_SEG_ADDR_MASK);
864 * Read timing compensation sequences
867 #define CALIBRATE_BUF_SIZE SZ_16K
869 static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
870 const u8 *golden_buf, u8 *test_buf)
874 for (i = 0; i < 10; i++) {
875 memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
876 if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
877 #if defined(VERBOSE_DEBUG)
878 print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
887 #define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
890 * The timing register is shared by all devices. Only update for CE0.
892 static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
893 const u8 *golden_buf, u8 *test_buf)
895 struct aspeed_spi *aspi = chip->aspi;
896 const struct aspeed_spi_data *data = aspi->data;
898 int good_pass = -1, pass_count = 0;
899 u32 shift = (hdiv - 1) << 2;
900 u32 mask = ~(0xfu << shift);
901 u32 fread_timing_val = 0;
903 /* Try HCLK delay 0..5, each one with/without delay and look for a
906 for (i = 0; i < 12; i++) {
910 fread_timing_val &= mask;
911 fread_timing_val |= FREAD_TPASS(i) << shift;
912 writel(fread_timing_val, aspi->regs + data->timing);
914 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
916 " * [%08x] %d HCLK delay, %dns DI delay : %s",
917 fread_timing_val, i / 2, (i & 1) ? 0 : 4,
918 pass ? "PASS" : "FAIL");
921 if (pass_count == 3) {
930 /* No good setting for this frequency */
934 /* We have at least one pass of margin, let's use first pass */
936 fread_timing_val &= mask;
937 fread_timing_val |= FREAD_TPASS(good_pass) << shift;
938 writel(fread_timing_val, aspi->regs + data->timing);
940 dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
941 good_pass, fread_timing_val);
945 static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
947 const u32 *tb32 = (const u32 *)test_buf;
950 /* We check if we have enough words that are neither all 0
951 * nor all 1's so the calibration can be considered valid.
953 * I use an arbitrary threshold for now of 64
956 for (i = 0; i < size; i++) {
957 if (tb32[i] != 0 && tb32[i] != 0xffffffff)
963 static const u32 aspeed_spi_hclk_divs[] = {
971 #define ASPEED_SPI_HCLK_DIV(i) \
972 (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
974 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
976 struct aspeed_spi *aspi = chip->aspi;
977 const struct aspeed_spi_data *data = aspi->data;
978 u32 ahb_freq = aspi->clk_freq;
979 u32 max_freq = chip->clk_freq;
981 u8 *golden_buf = NULL;
983 int i, rc, best_div = -1;
985 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
989 * use the related low frequency to get check calibration data
990 * and get golden data.
992 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
993 writel(ctl_val, chip->ctl);
995 test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
999 golden_buf = test_buf + CALIBRATE_BUF_SIZE;
1001 memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
1002 if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
1003 dev_info(aspi->dev, "Calibration area too uniform, using low speed");
1007 #if defined(VERBOSE_DEBUG)
1008 print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
1012 /* Now we iterate the HCLK dividers until we find our breaking point */
1013 for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
1016 freq = ahb_freq / i;
1017 if (freq > max_freq)
1020 /* Set the timing */
1021 tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
1022 writel(tv, chip->ctl);
1023 dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
1024 rc = data->calibrate(chip, i, golden_buf, test_buf);
1029 /* Nothing found ? */
1031 dev_warn(aspi->dev, "No good frequency, using dumb slow");
1033 dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
1035 /* Record the freq */
1036 for (i = 0; i < ASPEED_SPI_MAX; i++)
1037 chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
1038 ASPEED_SPI_HCLK_DIV(best_div);
1042 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
1047 #define TIMING_DELAY_DI BIT(3)
1048 #define TIMING_DELAY_HCYCLE_MAX 5
1049 #define TIMING_REG_AST2600(chip) \
1050 ((chip)->aspi->regs + (chip)->aspi->data->timing + \
1053 static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
1054 const u8 *golden_buf, u8 *test_buf)
1056 struct aspeed_spi *aspi = chip->aspi;
1058 u32 shift = (hdiv - 2) << 3;
1059 u32 mask = ~(0xfu << shift);
1060 u32 fread_timing_val = 0;
1062 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
1066 fread_timing_val &= mask;
1067 fread_timing_val |= hcycle << shift;
1069 /* no DI input delay first */
1070 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1071 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1073 " * [%08x] %d HCLK delay, DI delay none : %s",
1074 fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
1078 /* Add DI input delays */
1079 fread_timing_val &= mask;
1080 fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
1082 for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
1083 fread_timing_val &= ~(0xf << (4 + shift));
1084 fread_timing_val |= delay_ns << (4 + shift);
1086 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1087 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1089 " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
1090 fread_timing_val, hcycle, (delay_ns + 1) / 2,
1091 (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
1093 * TODO: This is optimistic. We should look
1094 * for a working interval and save the middle
1095 * value in the read timing register.
1102 /* No good setting for this frequency */
1107 * Platform definitions
1109 static const struct aspeed_spi_data ast2400_fmc_data = {
1113 .ctl0 = CE0_CTRL_REG,
1114 .timing = CE0_TIMING_COMPENSATION_REG,
1115 .hclk_mask = 0xfffff0ff,
1117 .calibrate = aspeed_spi_calibrate,
1118 .segment_start = aspeed_spi_segment_start,
1119 .segment_end = aspeed_spi_segment_end,
1120 .segment_reg = aspeed_spi_segment_reg,
1123 static const struct aspeed_spi_data ast2400_spi_data = {
1129 .hclk_mask = 0xfffff0ff,
1131 .calibrate = aspeed_spi_calibrate,
1132 /* No segment registers */
1135 static const struct aspeed_spi_data ast2500_fmc_data = {
1139 .ctl0 = CE0_CTRL_REG,
1140 .timing = CE0_TIMING_COMPENSATION_REG,
1141 .hclk_mask = 0xffffd0ff,
1143 .calibrate = aspeed_spi_calibrate,
1144 .segment_start = aspeed_spi_segment_start,
1145 .segment_end = aspeed_spi_segment_end,
1146 .segment_reg = aspeed_spi_segment_reg,
1149 static const struct aspeed_spi_data ast2500_spi_data = {
1153 .ctl0 = CE0_CTRL_REG,
1154 .timing = CE0_TIMING_COMPENSATION_REG,
1155 .hclk_mask = 0xffffd0ff,
1157 .calibrate = aspeed_spi_calibrate,
1158 .segment_start = aspeed_spi_segment_start,
1159 .segment_end = aspeed_spi_segment_end,
1160 .segment_reg = aspeed_spi_segment_reg,
1163 static const struct aspeed_spi_data ast2600_fmc_data = {
1166 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
1168 .ctl0 = CE0_CTRL_REG,
1169 .timing = CE0_TIMING_COMPENSATION_REG,
1170 .hclk_mask = 0xf0fff0ff,
1172 .calibrate = aspeed_spi_ast2600_calibrate,
1173 .segment_start = aspeed_spi_segment_ast2600_start,
1174 .segment_end = aspeed_spi_segment_ast2600_end,
1175 .segment_reg = aspeed_spi_segment_ast2600_reg,
1178 static const struct aspeed_spi_data ast2600_spi_data = {
1181 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
1183 .ctl0 = CE0_CTRL_REG,
1184 .timing = CE0_TIMING_COMPENSATION_REG,
1185 .hclk_mask = 0xf0fff0ff,
1187 .calibrate = aspeed_spi_ast2600_calibrate,
1188 .segment_start = aspeed_spi_segment_ast2600_start,
1189 .segment_end = aspeed_spi_segment_ast2600_end,
1190 .segment_reg = aspeed_spi_segment_ast2600_reg,
1193 static const struct of_device_id aspeed_spi_matches[] = {
1194 { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
1195 { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
1196 { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
1197 { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
1198 { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
1199 { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
1202 MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
1204 static struct platform_driver aspeed_spi_driver = {
1205 .probe = aspeed_spi_probe,
1206 .remove = aspeed_spi_remove,
1208 .name = DEVICE_NAME,
1209 .of_match_table = aspeed_spi_matches,
1213 module_platform_driver(aspeed_spi_driver);
1215 MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
1216 MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
1217 MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
1218 MODULE_LICENSE("GPL v2");