drivers/spi/spi-aspeed-smc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ASPEED FMC/SPI Controller driver
   4  *
   5  * Copyright (c) 2022 ASPEED Corporation.
   6  * Copyright (c) 2022 IBM Corporation.
   7  *
   8  * Author:
   9  *     Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
  10  *     Cedric Le Goater <clg@kaod.org>
  11  */
  12
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/bitops.h>
  19 #include <linux/bug.h>
  20 #include <linux/err.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mtd/spi-nor.h>
  24 #include <linux/sizes.h>
  25 #include <malloc.h>
  26 #include <spi.h>
  27 #include <spi-mem.h>
  28
  29 #define ASPEED_SPI_MAX_CS       5
  30
  31 #define CTRL_IO_SINGLE_DATA     0
  32 #define CTRL_IO_QUAD_DATA       BIT(30)
  33 #define CTRL_IO_DUAL_DATA       BIT(29)
  34
  35 #define CTRL_IO_MODE_USER       GENMASK(1, 0)
  36 #define CTRL_IO_MODE_CMD_READ   BIT(0)
  37 #define CTRL_IO_MODE_CMD_WRITE  BIT(1)
  38 #define CTRL_STOP_ACTIVE        BIT(2)
  39
  40 struct aspeed_spi_regs {
  41         u32 conf;                       /* 0x00 CE Type Setting */
  42         u32 ctrl;                       /* 0x04 CE Control */
  43         u32 intr_ctrl;                  /* 0x08 Interrupt Control and Status */
  44         u32 cmd_ctrl;                   /* 0x0c Command Control */
  45         u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x20 CEx Control */
  46         u32 _reserved0[3];              /* .. */
  47         u32 segment_addr[ASPEED_SPI_MAX_CS]; /* 0x30 .. 0x40 Segment Address */
  48         u32 _reserved1[3];              /* .. */
  49         u32 soft_rst_cmd_ctrl;          /* 0x50 Auto Soft-Reset Command Control */
  50         u32 _reserved2[11];             /* .. */
  51         u32 dma_ctrl;                   /* 0x80 DMA Control/Status */
  52         u32 dma_flash_addr;             /* 0x84 DMA Flash Side Address */
  53         u32 dma_dram_addr;              /* 0x88 DMA DRAM Side Address */
  54         u32 dma_len;                    /* 0x8c DMA Length Register */
  55         u32 dma_checksum;               /* 0x90 Checksum Calculation Result */
  56         u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */
  57 };
  58
  59 struct aspeed_spi_plat {
  60         u8 max_cs;
  61         void __iomem *ahb_base; /* AHB address base for all flash devices. */
  62         fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */
  63 };
  64
  65 struct aspeed_spi_flash {
  66         void __iomem *ahb_base;
  67         u32 ahb_decoded_sz;
  68         u32 ce_ctrl_user;
  69         u32 ce_ctrl_read;
  70 };
  71
  72 struct aspeed_spi_priv {
  73         u32 num_cs;
  74         struct aspeed_spi_regs *regs;
  75         struct aspeed_spi_info *info;
  76         struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS];
  77 };
  78
  79 struct aspeed_spi_info {
  80         u32 io_mode_mask;
  81         u32 max_bus_width;
  82         u32 min_decoded_sz;
  83         void (*set_4byte)(struct udevice *bus, u32 cs);
  84         u32 (*segment_start)(struct udevice *bus, u32 reg);
  85         u32 (*segment_end)(struct udevice *bus, u32 reg);
  86         u32 (*segment_reg)(u32 start, u32 end);
  87 };
  88
  89 static const struct aspeed_spi_info ast2400_spi_info;
  90 static int aspeed_spi_decoded_range_config(struct udevice *bus);
  91
  92 static u32 aspeed_spi_get_io_mode(u32 bus_width)
  93 {
  94         switch (bus_width) {
  95         case 1:
  96                 return CTRL_IO_SINGLE_DATA;
  97         case 2:
  98                 return CTRL_IO_DUAL_DATA;
  99         case 4:
 100                 return CTRL_IO_QUAD_DATA;
 101         default:
 102                 /* keep in default value */
 103                 return CTRL_IO_SINGLE_DATA;
 104         }
 105 }
 106
 107 static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg)
 108 {
 109         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 110         u32 start_offset = ((reg >> 16) & 0xff) << 23;
 111
 112         if (start_offset == 0)
 113                 return (u32)plat->ahb_base;
 114
 115         return (u32)plat->ahb_base + start_offset;
 116 }
 117
 118 static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg)
 119 {
 120         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 121         u32 end_offset = ((reg >> 24) & 0xff) << 23;
 122
 123         /* Meaningless end_offset, set to physical ahb base. */
 124         if (end_offset == 0)
 125                 return (u32)plat->ahb_base;
 126
 127         return (u32)plat->ahb_base + end_offset;
 128 }
 129
 130 static u32 ast2400_spi_segment_reg(u32 start, u32 end)
 131 {
 132         if (start == end)
 133                 return 0;
 134
 135         return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24);
 136 }
 137
 138 static void ast2400_fmc_chip_set_4byte(struct udevice *bus, u32 cs)
 139 {
 140         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 141         u32 reg_val;
 142
 143         reg_val = readl(&priv->regs->ctrl);
 144         reg_val |= 0x1 << cs;
 145         writel(reg_val, &priv->regs->ctrl);
 146 }
 147
 148 static void ast2400_spi_chip_set_4byte(struct udevice *bus, u32 cs)
 149 {
 150         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 151         struct aspeed_spi_flash *flash = &priv->flashes[cs];
 152
 153         flash->ce_ctrl_read |= BIT(13);
 154         writel(flash->ce_ctrl_read, &priv->regs->ctrl);
 155 }
 156
 157 static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg)
 158 {
 159         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 160         u32 start_offset = ((reg >> 16) & 0xff) << 23;
 161
 162         if (start_offset == 0)
 163                 return (u32)plat->ahb_base;
 164
 165         return (u32)plat->ahb_base + start_offset;
 166 }
 167
 168 static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg)
 169 {
 170         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 171         u32 end_offset = ((reg >> 24) & 0xff) << 23;
 172
 173         /* Meaningless end_offset, set to physical ahb base. */
 174         if (end_offset == 0)
 175                 return (u32)plat->ahb_base;
 176
 177         return (u32)plat->ahb_base + end_offset;
 178 }
 179
 180 static u32 ast2500_spi_segment_reg(u32 start, u32 end)
 181 {
 182         if (start == end)
 183                 return 0;
 184
 185         return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24);
 186 }
 187
 188 static void ast2500_spi_chip_set_4byte(struct udevice *bus, u32 cs)
 189 {
 190         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 191         u32 reg_val;
 192
 193         reg_val = readl(&priv->regs->ctrl);
 194         reg_val |= 0x1 << cs;
 195         writel(reg_val, &priv->regs->ctrl);
 196 }
 197
 198 static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg)
 199 {
 200         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 201         u32 start_offset = (reg << 16) & 0x0ff00000;
 202
 203         if (start_offset == 0)
 204                 return (u32)plat->ahb_base;
 205
 206         return (u32)plat->ahb_base + start_offset;
 207 }
 208
 209 static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg)
 210 {
 211         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 212         u32 end_offset = reg & 0x0ff00000;
 213
 214         /* Meaningless end_offset, set to physical ahb base. */
 215         if (end_offset == 0)
 216                 return (u32)plat->ahb_base;
 217
 218         return (u32)plat->ahb_base + end_offset + 0x100000;
 219 }
 220
 221 static u32 ast2600_spi_segment_reg(u32 start, u32 end)
 222 {
 223         if (start == end)
 224                 return 0;
 225
 226         return ((start & 0x0ff00000) >> 16) | ((end - 0x100000) & 0x0ff00000);
 227 }
 228
 229 static void ast2600_spi_chip_set_4byte(struct udevice *bus, u32 cs)
 230 {
 231         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 232         u32 reg_val;
 233
 234         reg_val = readl(&priv->regs->ctrl);
 235         reg_val |= 0x11 << cs;
 236         writel(reg_val, &priv->regs->ctrl);
 237 }
 238
 239 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf,
 240                                     size_t len)
 241 {
 242         size_t offset = 0;
 243
 244         if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) &&
 245             IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
 246                 readsl(ahb_base, buf, len >> 2);
 247                 offset = len & ~0x3;
 248                 len -= offset;
 249         }
 250
 251         readsb(ahb_base, (u8 *)buf + offset, len);
 252
 253         return 0;
 254 }
 255
 256 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf,
 257                                    size_t len)
 258 {
 259         size_t offset = 0;
 260
 261         if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) &&
 262             IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
 263                 writesl(ahb_base, buf, len >> 2);
 264                 offset = len & ~0x3;
 265                 len -= offset;
 266         }
 267
 268         writesb(ahb_base, (u8 *)buf + offset, len);
 269
 270         return 0;
 271 }
 272
 273 /*
 274  * Currently, only support 1-1-1, 1-1-2 or 1-1-4
 275  * SPI NOR flash operation format.
 276  */
 277 static bool aspeed_spi_supports_op(struct spi_slave *slave,
 278                                    const struct spi_mem_op *op)
 279 {
 280         struct udevice *bus = slave->dev->parent;
 281         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 282
 283         if (op->cmd.buswidth > 1)
 284                 return false;
 285
 286         if (op->addr.nbytes != 0) {
 287                 if (op->addr.buswidth > 1)
 288                         return false;
 289                 if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
 290                         return false;
 291         }
 292
 293         if (op->dummy.nbytes != 0) {
 294                 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
 295                         return false;
 296         }
 297
 298         if (op->data.nbytes != 0 &&
 299             op->data.buswidth > priv->info->max_bus_width)
 300                 return false;
 301
 302         if (!spi_mem_default_supports_op(slave, op))
 303                 return false;
 304
 305         return true;
 306 }
 307
 308 static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave,
 309                                         const struct spi_mem_op *op)
 310 {
 311         struct udevice *dev = slave->dev;
 312         struct udevice *bus = dev->parent;
 313         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 314         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
 315         u32 cs = slave_plat->cs;
 316         u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs];
 317         u32 ce_ctrl_val;
 318         struct aspeed_spi_flash *flash = &priv->flashes[cs];
 319         u8 dummy_data[16] = {0};
 320         u8 addr[4] = {0};
 321         int i;
 322
 323         dev_dbg(dev, "cmd:%x(%d),addr:%llx(%d),dummy:%d(%d),data_len:0x%x(%d)\n",
 324                 op->cmd.opcode, op->cmd.buswidth, op->addr.val,
 325                 op->addr.buswidth, op->dummy.nbytes, op->dummy.buswidth,
 326                 op->data.nbytes, op->data.buswidth);
 327
 328         if (priv->info == &ast2400_spi_info)
 329                 ce_ctrl_reg = (u32)&priv->regs->ctrl;
 330
 331         /*
 332          * Set controller to 4-byte address mode
 333          * if flash is in 4-byte address mode.
 334          */
 335         if (op->cmd.opcode == SPINOR_OP_EN4B)
 336                 priv->info->set_4byte(bus, cs);
 337
 338         /* Start user mode */
 339         ce_ctrl_val = flash->ce_ctrl_user;
 340         writel(ce_ctrl_val, ce_ctrl_reg);
 341         ce_ctrl_val &= (~CTRL_STOP_ACTIVE);
 342         writel(ce_ctrl_val, ce_ctrl_reg);
 343
 344         /* Send command */
 345         aspeed_spi_write_to_ahb(flash->ahb_base, &op->cmd.opcode, 1);
 346
 347         /* Send address */
 348         for (i = op->addr.nbytes; i > 0; i--) {
 349                 addr[op->addr.nbytes - i] =
 350                         ((u32)op->addr.val >> ((i - 1) * 8)) & 0xff;
 351         }
 352
 353         /* Change io_mode */
 354         ce_ctrl_val &= ~priv->info->io_mode_mask;
 355         ce_ctrl_val |= aspeed_spi_get_io_mode(op->addr.buswidth);
 356         writel(ce_ctrl_val, ce_ctrl_reg);
 357         aspeed_spi_write_to_ahb(flash->ahb_base, addr, op->addr.nbytes);
 358
 359         /* Send dummy cycles */
 360         aspeed_spi_write_to_ahb(flash->ahb_base, dummy_data, op->dummy.nbytes);
 361
 362         /* Change io_mode */
 363         ce_ctrl_val &= ~priv->info->io_mode_mask;
 364         ce_ctrl_val |= aspeed_spi_get_io_mode(op->data.buswidth);
 365         writel(ce_ctrl_val, ce_ctrl_reg);
 366
 367         /* Send data */
 368         if (op->data.dir == SPI_MEM_DATA_OUT) {
 369                 aspeed_spi_write_to_ahb(flash->ahb_base, op->data.buf.out,
 370                                         op->data.nbytes);
 371         } else {
 372                 aspeed_spi_read_from_ahb(flash->ahb_base, op->data.buf.in,
 373                                          op->data.nbytes);
 374         }
 375
 376         ce_ctrl_val |= CTRL_STOP_ACTIVE;
 377         writel(ce_ctrl_val, ce_ctrl_reg);
 378
 379         /* Restore controller setting. */
 380         writel(flash->ce_ctrl_read, ce_ctrl_reg);
 381
 382         return 0;
 383 }
 384
 385 static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
 386 {
 387         int ret = 0;
 388         struct udevice *dev = desc->slave->dev;
 389         struct udevice *bus = dev->parent;
 390         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 391         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 392         const struct aspeed_spi_info *info = priv->info;
 393         struct spi_mem_op op_tmpl = desc->info.op_tmpl;
 394         u32 i;
 395         u32 cs = slave_plat->cs;
 396         u32 reg_val;
 397         u32 ce_ctrl_reg;
 398
 399         if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
 400                 /*
 401                  * dirmap_write is not supported currently due to a HW
 402                  * limitation for command write mode: The written data
 403                  * length should be multiple of 4-byte.
 404                  */
 405                 return -EOPNOTSUPP;
 406         }
 407
 408         ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs];
 409         if (info == &ast2400_spi_info)
 410                 ce_ctrl_reg = (u32)&priv->regs->ctrl;
 411
 412         if (desc->info.length > 0x1000000)
 413                 priv->info->set_4byte(bus, cs);
 414
 415         /* AST2400 SPI1 doesn't have decoded address segment register. */
 416         if (info != &ast2400_spi_info) {
 417                 priv->flashes[cs].ahb_decoded_sz = desc->info.length;
 418
 419                 for (i = 0; i < priv->num_cs; i++) {
 420                         dev_dbg(dev, "cs: %d, sz: 0x%x\n", i,
 421                                 priv->flashes[cs].ahb_decoded_sz);
 422                 }
 423
 424                 ret = aspeed_spi_decoded_range_config(bus);
 425                 if (ret)
 426                         return ret;
 427         }
 428
 429         reg_val = aspeed_spi_get_io_mode(op_tmpl.data.buswidth) |
 430                   op_tmpl.cmd.opcode << 16 |
 431                   ((op_tmpl.dummy.nbytes) & 0x3) << 6 |
 432                   ((op_tmpl.dummy.nbytes) & 0x4) << 14 |
 433                   CTRL_IO_MODE_CMD_READ;
 434
 435         writel(reg_val, ce_ctrl_reg);
 436
 437         priv->flashes[cs].ce_ctrl_read = reg_val;
 438
 439         dev_dbg(dev, "read bus width: %d ce_ctrl_val: 0x%08x\n",
 440                 op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
 441
 442         return ret;
 443 }
 444
 445 static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
 446                                       u64 offs, size_t len, void *buf)
 447 {
 448         struct udevice *dev = desc->slave->dev;
 449         struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
 450         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 451         u32 cs = slave_plat->cs;
 452         int ret;
 453
 454         dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n",
 455                 desc->info.op_tmpl.cmd.opcode, offs, len);
 456
 457         if (priv->flashes[cs].ahb_decoded_sz < offs + len ||
 458             (offs % 4) != 0) {
 459                 ret = aspeed_spi_exec_op_user_mode(desc->slave,
 460                                                    &desc->info.op_tmpl);
 461                 if (ret != 0)
 462                         return 0;
 463         } else {
 464                 memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len);
 465         }
 466
 467         return len;
 468 }
 469
 470 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev)
 471 {
 472         struct udevice *bus = dev->parent;
 473         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 474         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 475         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 476         u32 cs = slave_plat->cs;
 477
 478         if (cs >= plat->max_cs) {
 479                 dev_err(dev, "invalid CS %u\n", cs);
 480                 return NULL;
 481         }
 482
 483         return &priv->flashes[cs];
 484 }
 485
 486 static void aspeed_spi_decoded_base_calculate(struct udevice *bus)
 487 {
 488         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 489         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 490         u32 cs;
 491
 492         priv->flashes[0].ahb_base = plat->ahb_base;
 493
 494         for (cs = 1; cs < plat->max_cs; cs++) {
 495                 priv->flashes[cs].ahb_base =
 496                                 priv->flashes[cs - 1].ahb_base +
 497                                 priv->flashes[cs - 1].ahb_decoded_sz;
 498         }
 499 }
 500
 501 static void aspeed_spi_decoded_range_set(struct udevice *bus)
 502 {
 503         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 504         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 505         u32 decoded_reg_val;
 506         u32 start_addr, end_addr;
 507         u32 cs;
 508
 509         for (cs = 0; cs < plat->max_cs; cs++) {
 510                 start_addr = (u32)priv->flashes[cs].ahb_base;
 511                 end_addr = (u32)priv->flashes[cs].ahb_base +
 512                            priv->flashes[cs].ahb_decoded_sz;
 513
 514                 decoded_reg_val = priv->info->segment_reg(start_addr, end_addr);
 515
 516                 writel(decoded_reg_val, &priv->regs->segment_addr[cs]);
 517
 518                 dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n",
 519                         cs, decoded_reg_val, start_addr, end_addr);
 520         }
 521 }
 522
 523 static int aspeed_spi_decoded_range_config(struct udevice *bus)
 524 {
 525         aspeed_spi_decoded_base_calculate(bus);
 526         aspeed_spi_decoded_range_set(bus);
 527
 528         return 0;
 529 }
 530
 531 /*
 532  * Initialize SPI controller for each chip select.
 533  * Here, only the minimum decode range is configured
 534  * in order to get device (SPI NOR flash) information
 535  * at the early stage.
 536  */
 537 static int aspeed_spi_ctrl_init(struct udevice *bus)
 538 {
 539         int ret;
 540         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 541         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 542         u32 cs;
 543         u32 reg_val;
 544         u32 decoded_sz;
 545
 546         /* Enable write capability for all CS. */
 547         reg_val = readl(&priv->regs->conf);
 548         if (priv->info == &ast2400_spi_info) {
 549                 writel(reg_val | BIT(0), &priv->regs->conf);
 550         } else {
 551                 writel(reg_val | (GENMASK(plat->max_cs - 1, 0) << 16),
 552                        &priv->regs->conf);
 553         }
 554
 555         memset(priv->flashes, 0x0,
 556                sizeof(struct aspeed_spi_flash) * ASPEED_SPI_MAX_CS);
 557
 558         /* Initial user mode. */
 559         for (cs = 0; cs < priv->num_cs; cs++) {
 560                 priv->flashes[cs].ce_ctrl_user =
 561                                 (CTRL_STOP_ACTIVE | CTRL_IO_MODE_USER);
 562         }
 563
 564         /*
 565          * SPI1 on AST2400 only supports CS0.
 566          * It is unnecessary to configure segment address register.
 567          */
 568         if (priv->info == &ast2400_spi_info) {
 569                 priv->flashes[cs].ahb_base = plat->ahb_base;
 570                 priv->flashes[cs].ahb_decoded_sz = 0x10000000;
 571                 return 0;
 572         }
 573
 574         /* Assign basic AHB decoded size for each CS. */
 575         for (cs = 0; cs < plat->max_cs; cs++) {
 576                 reg_val = readl(&priv->regs->segment_addr[cs]);
 577                 decoded_sz = priv->info->segment_end(bus, reg_val) -
 578                              priv->info->segment_start(bus, reg_val);
 579
 580                 if (decoded_sz < priv->info->min_decoded_sz)
 581                         decoded_sz = priv->info->min_decoded_sz;
 582
 583                 priv->flashes[cs].ahb_decoded_sz = decoded_sz;
 584         }
 585
 586         ret = aspeed_spi_decoded_range_config(bus);
 587
 588         return ret;
 589 }
 590
 591 static const struct aspeed_spi_info ast2400_fmc_info = {
 592         .io_mode_mask = 0x70000000,
 593         .max_bus_width = 2,
 594         .min_decoded_sz = 0x800000,
 595         .set_4byte = ast2400_fmc_chip_set_4byte,
 596         .segment_start = ast2400_spi_segment_start,
 597         .segment_end = ast2400_spi_segment_end,
 598         .segment_reg = ast2400_spi_segment_reg,
 599 };
 600
 601 static const struct aspeed_spi_info ast2400_spi_info = {
 602         .io_mode_mask = 0x70000000,
 603         .max_bus_width = 2,
 604         .min_decoded_sz = 0x800000,
 605         .set_4byte = ast2400_spi_chip_set_4byte,
 606         .segment_start = ast2400_spi_segment_start,
 607         .segment_end = ast2400_spi_segment_end,
 608         .segment_reg = ast2400_spi_segment_reg,
 609 };
 610
 611 static const struct aspeed_spi_info ast2500_fmc_info = {
 612         .io_mode_mask = 0x70000000,
 613         .max_bus_width = 2,
 614         .min_decoded_sz = 0x800000,
 615         .set_4byte = ast2500_spi_chip_set_4byte,
 616         .segment_start = ast2500_spi_segment_start,
 617         .segment_end = ast2500_spi_segment_end,
 618         .segment_reg = ast2500_spi_segment_reg,
 619 };
 620
 621 /*
 622  * There are some different between FMC and SPI controllers.
 623  * For example, DMA operation, but this isn't implemented currently.
 624  */
 625 static const struct aspeed_spi_info ast2500_spi_info = {
 626         .io_mode_mask = 0x70000000,
 627         .max_bus_width = 2,
 628         .min_decoded_sz = 0x800000,
 629         .set_4byte = ast2500_spi_chip_set_4byte,
 630         .segment_start = ast2500_spi_segment_start,
 631         .segment_end = ast2500_spi_segment_end,
 632         .segment_reg = ast2500_spi_segment_reg,
 633 };
 634
 635 static const struct aspeed_spi_info ast2600_fmc_info = {
 636         .io_mode_mask = 0xf0000000,
 637         .max_bus_width = 4,
 638         .min_decoded_sz = 0x200000,
 639         .set_4byte = ast2600_spi_chip_set_4byte,
 640         .segment_start = ast2600_spi_segment_start,
 641         .segment_end = ast2600_spi_segment_end,
 642         .segment_reg = ast2600_spi_segment_reg,
 643 };
 644
 645 static const struct aspeed_spi_info ast2600_spi_info = {
 646         .io_mode_mask = 0xf0000000,
 647         .max_bus_width = 4,
 648         .min_decoded_sz = 0x200000,
 649         .set_4byte = ast2600_spi_chip_set_4byte,
 650         .segment_start = ast2600_spi_segment_start,
 651         .segment_end = ast2600_spi_segment_end,
 652         .segment_reg = ast2600_spi_segment_reg,
 653 };
 654
 655 static int aspeed_spi_claim_bus(struct udevice *dev)
 656 {
 657         struct udevice *bus = dev->parent;
 658         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 659
 660         dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs);
 661
 662         return 0;
 663 }
 664
 665 static int aspeed_spi_release_bus(struct udevice *dev)
 666 {
 667         struct udevice *bus = dev->parent;
 668         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 669
 670         dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs);
 671
 672         if (!aspeed_spi_get_flash(dev))
 673                 return -ENODEV;
 674
 675         return 0;
 676 }
 677
 678 static int aspeed_spi_set_mode(struct udevice *bus, uint mode)
 679 {
 680         dev_dbg(bus, "%s: setting mode to %x\n", bus->name, mode);
 681
 682         return 0;
 683 }
 684
 685 static int aspeed_spi_set_speed(struct udevice *bus, uint hz)
 686 {
 687         dev_dbg(bus, "%s: setting speed to %u\n", bus->name, hz);
 688         /*
 689          * ASPEED SPI controller supports multiple CS with different
 690          * clock frequency. We cannot distinguish which CS here.
 691          * Thus, the related implementation is postponed to claim_bus.
 692          */
 693
 694         return 0;
 695 }
 696
 697 static int apseed_spi_of_to_plat(struct udevice *bus)
 698 {
 699         struct aspeed_spi_plat *plat = dev_get_plat(bus);
 700         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 701
 702         priv->regs = (void __iomem *)devfdt_get_addr_index(bus, 0);
 703         if ((u32)priv->regs == FDT_ADDR_T_NONE) {
 704                 dev_err(bus, "wrong ctrl base\n");
 705                 return -ENODEV;
 706         }
 707
 708         plat->ahb_base =
 709                 (void __iomem *)devfdt_get_addr_size_index(bus, 1, &plat->ahb_sz);
 710         if ((u32)plat->ahb_base == FDT_ADDR_T_NONE) {
 711                 dev_err(bus, "wrong AHB base\n");
 712                 return -ENODEV;
 713         }
 714
 715         plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS);
 716         if (plat->max_cs > ASPEED_SPI_MAX_CS)
 717                 return -EINVAL;
 718
 719         dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%lx\n",
 720                 (u32)priv->regs, plat->ahb_base, plat->ahb_sz);
 721         dev_dbg(bus, "max_cs = %d\n", plat->max_cs);
 722
 723         return 0;
 724 }
 725
 726 static int aspeed_spi_probe(struct udevice *bus)
 727 {
 728         int ret;
 729         struct aspeed_spi_priv *priv = dev_get_priv(bus);
 730         struct udevice *dev;
 731
 732         priv->info = (struct aspeed_spi_info *)dev_get_driver_data(bus);
 733
 734         priv->num_cs = 0;
 735         for (device_find_first_child(bus, &dev); dev;
 736              device_find_next_child(&dev)) {
 737                 priv->num_cs++;
 738         }
 739
 740         if (priv->num_cs > ASPEED_SPI_MAX_CS)
 741                 return -EINVAL;
 742
 743         ret = aspeed_spi_ctrl_init(bus);
 744
 745         return ret;
 746 }
 747
 748 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
 749         .supports_op = aspeed_spi_supports_op,
 750         .exec_op = aspeed_spi_exec_op_user_mode,
 751         .dirmap_create = aspeed_spi_dirmap_create,
 752         .dirmap_read = aspeed_spi_dirmap_read,
 753 };
 754
 755 static const struct dm_spi_ops aspeed_spi_ops = {
 756         .claim_bus = aspeed_spi_claim_bus,
 757         .release_bus = aspeed_spi_release_bus,
 758         .set_speed = aspeed_spi_set_speed,
 759         .set_mode = aspeed_spi_set_mode,
 760         .mem_ops = &aspeed_spi_mem_ops,
 761 };
 762
 763 static const struct udevice_id aspeed_spi_ids[] = {
 764         { .compatible = "aspeed,ast2400-fmc", .data = (ulong)&ast2400_fmc_info, },
 765         { .compatible = "aspeed,ast2400-spi", .data = (ulong)&ast2400_spi_info, },
 766         { .compatible = "aspeed,ast2500-fmc", .data = (ulong)&ast2500_fmc_info, },
 767         { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, },
 768         { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, },
 769         { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, },
 770         { }
 771 };
 772
 773 U_BOOT_DRIVER(aspeed_spi) = {
 774         .name = "aspeed_spi_smc",
 775         .id = UCLASS_SPI,
 776         .of_match = aspeed_spi_ids,
 777         .ops = &aspeed_spi_ops,
 778         .of_to_plat = apseed_spi_of_to_plat,
 779         .plat_auto = sizeof(struct aspeed_spi_plat),
 780         .priv_auto = sizeof(struct aspeed_spi_priv),
 781         .probe = aspeed_spi_probe,
 782 };