drivers/spi/spi-amd.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 //
   3 // AMD SPI controller driver
   4 //
   5 // Copyright (c) 2020, Advanced Micro Devices, Inc.
   6 //
   7 // Author: Sanjay R Mehta <sanju.mehta@amd.com>
   8
   9 #include <linux/acpi.h>
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/delay.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/iopoll.h>
  16
  17 #define AMD_SPI_CTRL0_REG       0x00
  18 #define AMD_SPI_EXEC_CMD        BIT(16)
  19 #define AMD_SPI_FIFO_CLEAR      BIT(20)
  20 #define AMD_SPI_BUSY            BIT(31)
  21
  22 #define AMD_SPI_OPCODE_REG      0x45
  23 #define AMD_SPI_CMD_TRIGGER_REG 0x47
  24 #define AMD_SPI_TRIGGER_CMD     BIT(7)
  25
  26 #define AMD_SPI_OPCODE_MASK     0xFF
  27
  28 #define AMD_SPI_ALT_CS_REG      0x1D
  29 #define AMD_SPI_ALT_CS_MASK     0x3
  30
  31 #define AMD_SPI_FIFO_BASE       0x80
  32 #define AMD_SPI_TX_COUNT_REG    0x48
  33 #define AMD_SPI_RX_COUNT_REG    0x4B
  34 #define AMD_SPI_STATUS_REG      0x4C
  35
  36 #define AMD_SPI_FIFO_SIZE       70
  37 #define AMD_SPI_MEM_SIZE        200
  38
  39 /* M_CMD OP codes for SPI */
  40 #define AMD_SPI_XFER_TX         1
  41 #define AMD_SPI_XFER_RX         2
  42
  43 /**
  44  * enum amd_spi_versions - SPI controller versions
  45  * @AMD_SPI_V1:         AMDI0061 hardware version
  46  * @AMD_SPI_V2:         AMDI0062 hardware version
  47  */
  48 enum amd_spi_versions {
  49         AMD_SPI_V1 = 1,
  50         AMD_SPI_V2,
  51 };
  52
  53 /**
  54  * struct amd_spi - SPI driver instance
  55  * @io_remap_addr:      Start address of the SPI controller registers
  56  * @version:            SPI controller hardware version
  57  */
  58 struct amd_spi {
  59         void __iomem *io_remap_addr;
  60         enum amd_spi_versions version;
  61 };
  62
  63 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
  64 {
  65         return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
  66 }
  67
  68 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
  69 {
  70         iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
  71 }
  72
  73 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
  74 {
  75         u8 tmp = amd_spi_readreg8(amd_spi, idx);
  76
  77         tmp = (tmp & ~clear) | set;
  78         amd_spi_writereg8(amd_spi, idx, tmp);
  79 }
  80
  81 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
  82 {
  83         return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
  84 }
  85
  86 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
  87 {
  88         iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
  89 }
  90
  91 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
  92 {
  93         u32 tmp = amd_spi_readreg32(amd_spi, idx);
  94
  95         tmp = (tmp & ~clear) | set;
  96         amd_spi_writereg32(amd_spi, idx, tmp);
  97 }
  98
  99 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
 100 {
 101         amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
 102 }
 103
 104 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
 105 {
 106         amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
 107 }
 108
 109 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
 110 {
 111         amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
 112 }
 113
 114 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
 115 {
 116         switch (amd_spi->version) {
 117         case AMD_SPI_V1:
 118                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
 119                                        AMD_SPI_OPCODE_MASK);
 120                 return 0;
 121         case AMD_SPI_V2:
 122                 amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
 123                 return 0;
 124         default:
 125                 return -ENODEV;
 126         }
 127 }
 128
 129 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
 130 {
 131         amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
 132 }
 133
 134 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
 135 {
 136         amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
 137 }
 138
 139 static int amd_spi_busy_wait(struct amd_spi *amd_spi)
 140 {
 141         u32 val;
 142         int reg;
 143
 144         switch (amd_spi->version) {
 145         case AMD_SPI_V1:
 146                 reg = AMD_SPI_CTRL0_REG;
 147                 break;
 148         case AMD_SPI_V2:
 149                 reg = AMD_SPI_STATUS_REG;
 150                 break;
 151         default:
 152                 return -ENODEV;
 153         }
 154
 155         return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
 156                                   !(val & AMD_SPI_BUSY), 20, 2000000);
 157 }
 158
 159 static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
 160 {
 161         int ret;
 162
 163         ret = amd_spi_busy_wait(amd_spi);
 164         if (ret)
 165                 return ret;
 166
 167         switch (amd_spi->version) {
 168         case AMD_SPI_V1:
 169                 /* Set ExecuteOpCode bit in the CTRL0 register */
 170                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
 171                                        AMD_SPI_EXEC_CMD);
 172                 return 0;
 173         case AMD_SPI_V2:
 174                 /* Trigger the command execution */
 175                 amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
 176                                       AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
 177                 return 0;
 178         default:
 179                 return -ENODEV;
 180         }
 181 }
 182
 183 static int amd_spi_master_setup(struct spi_device *spi)
 184 {
 185         struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
 186
 187         amd_spi_clear_fifo_ptr(amd_spi);
 188
 189         return 0;
 190 }
 191
 192 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
 193                                     struct spi_master *master,
 194                                     struct spi_message *message)
 195 {
 196         struct spi_transfer *xfer = NULL;
 197         u8 cmd_opcode;
 198         u8 *buf = NULL;
 199         u32 m_cmd = 0;
 200         u32 i = 0;
 201         u32 tx_len = 0, rx_len = 0;
 202
 203         list_for_each_entry(xfer, &message->transfers,
 204                             transfer_list) {
 205                 if (xfer->rx_buf)
 206                         m_cmd = AMD_SPI_XFER_RX;
 207                 if (xfer->tx_buf)
 208                         m_cmd = AMD_SPI_XFER_TX;
 209
 210                 if (m_cmd & AMD_SPI_XFER_TX) {
 211                         buf = (u8 *)xfer->tx_buf;
 212                         tx_len = xfer->len - 1;
 213                         cmd_opcode = *(u8 *)xfer->tx_buf;
 214                         buf++;
 215                         amd_spi_set_opcode(amd_spi, cmd_opcode);
 216
 217                         /* Write data into the FIFO. */
 218                         for (i = 0; i < tx_len; i++) {
 219                                 iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr +
 220                                          AMD_SPI_FIFO_BASE + i));
 221                         }
 222
 223                         amd_spi_set_tx_count(amd_spi, tx_len);
 224                         amd_spi_clear_fifo_ptr(amd_spi);
 225                         /* Execute command */
 226                         amd_spi_execute_opcode(amd_spi);
 227                 }
 228                 if (m_cmd & AMD_SPI_XFER_RX) {
 229                         /*
 230                          * Store no. of bytes to be received from
 231                          * FIFO
 232                          */
 233                         rx_len = xfer->len;
 234                         buf = (u8 *)xfer->rx_buf;
 235                         amd_spi_set_rx_count(amd_spi, rx_len);
 236                         amd_spi_clear_fifo_ptr(amd_spi);
 237                         /* Execute command */
 238                         amd_spi_execute_opcode(amd_spi);
 239                         amd_spi_busy_wait(amd_spi);
 240                         /* Read data from FIFO to receive buffer  */
 241                         for (i = 0; i < rx_len; i++)
 242                                 buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
 243                 }
 244         }
 245
 246         /* Update statistics */
 247         message->actual_length = tx_len + rx_len + 1;
 248         /* complete the transaction */
 249         message->status = 0;
 250
 251         switch (amd_spi->version) {
 252         case AMD_SPI_V1:
 253                 break;
 254         case AMD_SPI_V2:
 255                 amd_spi_clear_chip(amd_spi, message->spi->chip_select);
 256                 break;
 257         default:
 258                 return -ENODEV;
 259         }
 260
 261         spi_finalize_current_message(master);
 262
 263         return 0;
 264 }
 265
 266 static int amd_spi_master_transfer(struct spi_master *master,
 267                                    struct spi_message *msg)
 268 {
 269         struct amd_spi *amd_spi = spi_master_get_devdata(master);
 270         struct spi_device *spi = msg->spi;
 271
 272         amd_spi_select_chip(amd_spi, spi->chip_select);
 273
 274         /*
 275          * Extract spi_transfers from the spi message and
 276          * program the controller.
 277          */
 278         amd_spi_fifo_xfer(amd_spi, master, msg);
 279
 280         return 0;
 281 }
 282
 283 static size_t amd_spi_max_transfer_size(struct spi_device *spi)
 284 {
 285         return AMD_SPI_FIFO_SIZE;
 286 }
 287
 288 static int amd_spi_probe(struct platform_device *pdev)
 289 {
 290         struct device *dev = &pdev->dev;
 291         struct spi_master *master;
 292         struct amd_spi *amd_spi;
 293         int err;
 294
 295         /* Allocate storage for spi_master and driver private data */
 296         master = devm_spi_alloc_master(dev, sizeof(struct amd_spi));
 297         if (!master)
 298                 return dev_err_probe(dev, -ENOMEM, "Error allocating SPI master\n");
 299
 300         amd_spi = spi_master_get_devdata(master);
 301         amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
 302         if (IS_ERR(amd_spi->io_remap_addr))
 303                 return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
 304                                      "ioremap of SPI registers failed\n");
 305
 306         dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
 307
 308         amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
 309
 310         /* Initialize the spi_master fields */
 311         master->bus_num = 0;
 312         master->num_chipselect = 4;
 313         master->mode_bits = 0;
 314         master->flags = SPI_MASTER_HALF_DUPLEX;
 315         master->setup = amd_spi_master_setup;
 316         master->transfer_one_message = amd_spi_master_transfer;
 317         master->max_transfer_size = amd_spi_max_transfer_size;
 318         master->max_message_size = amd_spi_max_transfer_size;
 319
 320         /* Register the controller with SPI framework */
 321         err = devm_spi_register_master(dev, master);
 322         if (err)
 323                 return dev_err_probe(dev, err, "error registering SPI controller\n");
 324
 325         return 0;
 326 }
 327
 328 #ifdef CONFIG_ACPI
 329 static const struct acpi_device_id spi_acpi_match[] = {
 330         { "AMDI0061", AMD_SPI_V1 },
 331         { "AMDI0062", AMD_SPI_V2 },
 332         {},
 333 };
 334 MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
 335 #endif
 336
 337 static struct platform_driver amd_spi_driver = {
 338         .driver = {
 339                 .name = "amd_spi",
 340                 .acpi_match_table = ACPI_PTR(spi_acpi_match),
 341         },
 342         .probe = amd_spi_probe,
 343 };
 344
 345 module_platform_driver(amd_spi_driver);
 346
 347 MODULE_LICENSE("Dual BSD/GPL");
 348 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
 349 MODULE_DESCRIPTION("AMD SPI Master Controller Driver");