1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Renesas Solutions Corp.
15 static void sh_spi_write(unsigned long data, unsigned long *reg)
20 static unsigned long sh_spi_read(unsigned long *reg)
25 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
29 tmp = sh_spi_read(reg);
31 sh_spi_write(tmp, reg);
34 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
38 tmp = sh_spi_read(reg);
40 sh_spi_write(tmp, reg);
43 static void clear_fifo(struct sh_spi *ss)
45 sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
46 sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
49 static int recvbuf_wait(struct sh_spi *ss)
51 while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
59 static int write_fifo_empty_wait(struct sh_spi *ss)
61 while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
69 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
71 unsigned long val = 0;
78 sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
79 sh_spi_set_bit(val, &ss->regs->cr4);
82 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
83 unsigned int max_hz, unsigned int mode)
87 if (!spi_cs_is_valid(bus, cs))
90 ss = spi_alloc_slave(struct sh_spi, bus, cs);
94 ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
97 sh_spi_write(0xfe, &ss->regs->cr1);
99 sh_spi_write(0x00, &ss->regs->cr1);
101 sh_spi_write(0x00, &ss->regs->cr3);
102 sh_spi_set_cs(ss, cs);
107 sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
113 void spi_free_slave(struct spi_slave *slave)
115 struct sh_spi *spi = to_sh_spi(slave);
120 int spi_claim_bus(struct spi_slave *slave)
125 void spi_release_bus(struct spi_slave *slave)
127 struct sh_spi *ss = to_sh_spi(slave);
129 sh_spi_write(sh_spi_read(&ss->regs->cr1) &
130 ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
133 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
134 unsigned int len, unsigned long flags)
136 int i, cur_len, ret = 0;
137 int remain = (int)len;
139 if (len >= SH_SPI_FIFO_SIZE)
140 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
143 cur_len = (remain < SH_SPI_FIFO_SIZE) ?
144 remain : SH_SPI_FIFO_SIZE;
145 for (i = 0; i < cur_len &&
146 !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
147 !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
149 sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
153 if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
154 /* Abort the transaction */
155 flags |= SPI_XFER_END;
156 sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
165 write_fifo_empty_wait(ss);
168 if (flags & SPI_XFER_END) {
169 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
170 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
172 write_fifo_empty_wait(ss);
178 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
179 unsigned int len, unsigned long flags)
183 if (len > SH_SPI_MAX_BYTE)
184 sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
186 sh_spi_write(len, &ss->regs->cr3);
188 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
189 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
191 for (i = 0; i < len; i++) {
192 if (recvbuf_wait(ss))
195 rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
197 sh_spi_write(0, &ss->regs->cr3);
202 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
203 void *din, unsigned long flags)
205 struct sh_spi *ss = to_sh_spi(slave);
206 const unsigned char *tx_data = dout;
207 unsigned char *rx_data = din;
208 unsigned int len = bitlen / 8;
211 if (flags & SPI_XFER_BEGIN)
212 sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
216 ret = sh_spi_send(ss, tx_data, len, flags);
218 if (ret == 0 && rx_data)
219 ret = sh_spi_receive(ss, rx_data, len, flags);
221 if (flags & SPI_XFER_END) {
222 sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
225 sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
233 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
235 if (!bus && cs < SH_SPI_NUM_CS)
241 void spi_cs_activate(struct spi_slave *slave)
246 void spi_cs_deactivate(struct spi_slave *slave)