2 * SH QSPI (Quad SPI) driver
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/arch/rmobile.h>
18 /* SH QSPI register bit masks <REG>_<BIT> */
19 #define SPCR_MSTR 0x08
21 #define SPSR_SPRFF 0x80
22 #define SPSR_SPTEF 0x20
23 #define SPPCR_IO3FV 0x04
24 #define SPPCR_IO2FV 0x02
25 #define SPPCR_IO1FV 0x01
26 #define SPBDCR_RXBC0 BIT(0)
27 #define SPCMD_SCKDEN BIT(15)
28 #define SPCMD_SLNDEN BIT(14)
29 #define SPCMD_SPNDEN BIT(13)
30 #define SPCMD_SSLKP BIT(7)
31 #define SPCMD_BRDV0 BIT(2)
32 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
33 SPCMD_SPNDEN | SPCMD_SSLKP | \
35 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
37 #define SPBFCR_TXRST BIT(7)
38 #define SPBFCR_RXRST BIT(6)
40 /* SH QSPI register set */
68 struct sh_qspi_slave {
69 struct spi_slave slave;
70 struct sh_qspi_regs *regs;
73 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
75 return container_of(slave, struct sh_qspi_slave, slave);
78 static void sh_qspi_init(struct sh_qspi_slave *ss)
81 /* Set master mode only */
82 writeb(SPCR_MSTR, &ss->regs->spcr);
84 /* Set SSL signal level */
85 writeb(0x00, &ss->regs->sslp);
87 /* Set MOSI signal value when transfer is in idle state */
88 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
90 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
91 writeb(0x01, &ss->regs->spbr);
93 /* Disable Dummy Data Transmission */
94 writeb(0x00, &ss->regs->spdcr);
96 /* Set clock delay value */
97 writeb(0x00, &ss->regs->spckd);
99 /* Set SSL negation delay value */
100 writeb(0x00, &ss->regs->sslnd);
102 /* Set next-access delay value */
103 writeb(0x00, &ss->regs->spnd);
105 /* Set equence command */
106 writew(SPCMD_INIT2, &ss->regs->spcmd0);
108 /* Reset transfer and receive Buffer */
109 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
111 /* Clear transfer and receive Buffer control bit */
112 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
114 /* Set equence control method. Use equence0 only */
115 writeb(0x00, &ss->regs->spscr);
117 /* Enable SPI function */
118 setbits_8(&ss->regs->spcr, SPCR_SPE);
121 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
126 void spi_cs_activate(struct spi_slave *slave)
128 struct sh_qspi_slave *ss = to_sh_qspi(slave);
130 /* Set master mode only */
131 writeb(SPCR_MSTR, &ss->regs->spcr);
134 writew(SPCMD_INIT1, &ss->regs->spcmd0);
136 /* Reset transfer and receive Buffer */
137 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
139 /* Clear transfer and receive Buffer control bit */
140 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
142 /* Set equence control method. Use equence0 only */
143 writeb(0x00, &ss->regs->spscr);
145 /* Enable SPI function */
146 setbits_8(&ss->regs->spcr, SPCR_SPE);
149 void spi_cs_deactivate(struct spi_slave *slave)
151 struct sh_qspi_slave *ss = to_sh_qspi(slave);
153 /* Disable SPI Function */
154 clrbits_8(&ss->regs->spcr, SPCR_SPE);
162 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
163 unsigned int max_hz, unsigned int mode)
165 struct sh_qspi_slave *ss;
167 if (!spi_cs_is_valid(bus, cs))
170 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
172 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
176 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
184 void spi_free_slave(struct spi_slave *slave)
186 struct sh_qspi_slave *spi = to_sh_qspi(slave);
191 int spi_claim_bus(struct spi_slave *slave)
196 void spi_release_bus(struct spi_slave *slave)
200 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
201 void *din, unsigned long flags)
203 struct sh_qspi_slave *ss = to_sh_qspi(slave);
206 u8 dtdata = 0, drdata;
207 u8 *tdata = &dtdata, *rdata = &drdata;
208 u32 *spbmul0 = &ss->regs->spbmul0;
210 if (dout == NULL && din == NULL) {
211 if (flags & SPI_XFER_END)
212 spi_cs_deactivate(slave);
217 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
223 if (flags & SPI_XFER_BEGIN) {
224 spi_cs_activate(slave);
226 /* Set 1048576 byte */
227 writel(0x100000, spbmul0);
230 if (flags & SPI_XFER_END)
231 writel(nbyte, spbmul0);
240 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
245 writeb(*tdata, (u8 *)(&ss->regs->spdr));
247 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
252 *rdata = readb((u8 *)(&ss->regs->spdr));
262 if (flags & SPI_XFER_END)
263 spi_cs_deactivate(slave);