2 * SH QSPI (Quad SPI) driver
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
15 /* SH QSPI register bit masks <REG>_<BIT> */
16 #define SPCR_MSTR 0x08
18 #define SPSR_SPRFF 0x80
19 #define SPSR_SPTEF 0x20
20 #define SPPCR_IO3FV 0x04
21 #define SPPCR_IO2FV 0x02
22 #define SPPCR_IO1FV 0x01
23 #define SPBDCR_RXBC0 (1 << 0)
24 #define SPCMD_SCKDEN (1 << 15)
25 #define SPCMD_SLNDEN (1 << 14)
26 #define SPCMD_SPNDEN (1 << 13)
27 #define SPCMD_SSLKP (1 << 7)
28 #define SPCMD_BRDV0 (1 << 2)
29 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
30 SPCMD_SPNDEN | SPCMD_SSLKP | \
32 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
34 #define SPBFCR_TXRST (1 << 7)
35 #define SPBFCR_RXRST (1 << 6)
37 /* SH QSPI register set */
52 unsigned short spcmd0;
53 unsigned short spcmd1;
54 unsigned short spcmd2;
55 unsigned short spcmd3;
58 unsigned short spbdcr;
59 unsigned long spbmul0;
60 unsigned long spbmul1;
61 unsigned long spbmul2;
62 unsigned long spbmul3;
65 struct sh_qspi_slave {
66 struct spi_slave slave;
67 struct sh_qspi_regs *regs;
70 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
72 return container_of(slave, struct sh_qspi_slave, slave);
75 static void sh_qspi_init(struct sh_qspi_slave *ss)
78 /* Set master mode only */
79 writeb(SPCR_MSTR, &ss->regs->spcr);
81 /* Set SSL signal level */
82 writeb(0x00, &ss->regs->sslp);
84 /* Set MOSI signal value when transfer is in idle state */
85 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
87 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
88 writeb(0x01, &ss->regs->spbr);
90 /* Disable Dummy Data Transmission */
91 writeb(0x00, &ss->regs->spdcr);
93 /* Set clock delay value */
94 writeb(0x00, &ss->regs->spckd);
96 /* Set SSL negation delay value */
97 writeb(0x00, &ss->regs->sslnd);
99 /* Set next-access delay value */
100 writeb(0x00, &ss->regs->spnd);
102 /* Set equence command */
103 writew(SPCMD_INIT2, &ss->regs->spcmd0);
105 /* Reset transfer and receive Buffer */
106 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
108 /* Clear transfer and receive Buffer control bit */
109 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
111 /* Set equence control method. Use equence0 only */
112 writeb(0x00, &ss->regs->spscr);
114 /* Enable SPI function */
115 setbits_8(&ss->regs->spcr, SPCR_SPE);
118 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
123 void spi_cs_activate(struct spi_slave *slave)
125 struct sh_qspi_slave *ss = to_sh_qspi(slave);
127 /* Set master mode only */
128 writeb(SPCR_MSTR, &ss->regs->spcr);
131 writew(SPCMD_INIT1, &ss->regs->spcmd0);
133 /* Reset transfer and receive Buffer */
134 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
136 /* Clear transfer and receive Buffer control bit */
137 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
139 /* Set equence control method. Use equence0 only */
140 writeb(0x00, &ss->regs->spscr);
142 /* Enable SPI function */
143 setbits_8(&ss->regs->spcr, SPCR_SPE);
146 void spi_cs_deactivate(struct spi_slave *slave)
148 struct sh_qspi_slave *ss = to_sh_qspi(slave);
150 /* Disable SPI Function */
151 clrbits_8(&ss->regs->spcr, SPCR_SPE);
159 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
160 unsigned int max_hz, unsigned int mode)
162 struct sh_qspi_slave *ss;
164 if (!spi_cs_is_valid(bus, cs))
167 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
169 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
173 ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
181 void spi_free_slave(struct spi_slave *slave)
183 struct sh_qspi_slave *spi = to_sh_qspi(slave);
188 int spi_claim_bus(struct spi_slave *slave)
193 void spi_release_bus(struct spi_slave *slave)
197 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
198 void *din, unsigned long flags)
200 struct sh_qspi_slave *ss = to_sh_qspi(slave);
203 unsigned char dtdata = 0, drdata;
204 unsigned char *tdata = &dtdata, *rdata = &drdata;
205 unsigned long *spbmul0 = &ss->regs->spbmul0;
207 if (dout == NULL && din == NULL) {
208 if (flags & SPI_XFER_END)
209 spi_cs_deactivate(slave);
214 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
220 if (flags & SPI_XFER_BEGIN) {
221 spi_cs_activate(slave);
223 /* Set 1048576 byte */
224 writel(0x100000, spbmul0);
227 if (flags & SPI_XFER_END)
228 writel(nbyte, spbmul0);
231 tdata = (unsigned char *)dout;
237 while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) {
245 writeb(*tdata, (unsigned char *)(&ss->regs->spdr));
247 while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) {
255 while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) {
263 *rdata = readb((unsigned char *)(&ss->regs->spdr));
273 if (flags & SPI_XFER_END)
274 spi_cs_deactivate(slave);