1 // SPDX-License-Identifier: GPL-2.0
3 * SH QSPI (Quad SPI) driver
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
9 #define LOG_CATEGORY UCLASS_SPI
16 #include <asm/arch/rmobile.h>
18 #include <linux/bitops.h>
20 /* SH QSPI register bit masks <REG>_<BIT> */
21 #define SPCR_MSTR 0x08
23 #define SPSR_SPRFF 0x80
24 #define SPSR_SPTEF 0x20
25 #define SPPCR_IO3FV 0x04
26 #define SPPCR_IO2FV 0x02
27 #define SPPCR_IO1FV 0x01
28 #define SPBDCR_RXBC0 BIT(0)
29 #define SPCMD_SCKDEN BIT(15)
30 #define SPCMD_SLNDEN BIT(14)
31 #define SPCMD_SPNDEN BIT(13)
32 #define SPCMD_SSLKP BIT(7)
33 #define SPCMD_BRDV0 BIT(2)
34 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
35 SPCMD_SPNDEN | SPCMD_SSLKP | \
37 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
39 #define SPBFCR_TXRST BIT(7)
40 #define SPBFCR_RXRST BIT(6)
41 #define SPBFCR_TXTRG 0x30
42 #define SPBFCR_RXTRG 0x07
44 /* SH QSPI register set */
72 struct sh_qspi_slave {
73 #if !CONFIG_IS_ENABLED(DM_SPI)
74 struct spi_slave slave;
76 struct sh_qspi_regs *regs;
79 static void sh_qspi_init(struct sh_qspi_slave *ss)
82 /* Set master mode only */
83 writeb(SPCR_MSTR, &ss->regs->spcr);
85 /* Set SSL signal level */
86 writeb(0x00, &ss->regs->sslp);
88 /* Set MOSI signal value when transfer is in idle state */
89 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
91 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
92 writeb(0x01, &ss->regs->spbr);
94 /* Disable Dummy Data Transmission */
95 writeb(0x00, &ss->regs->spdcr);
97 /* Set clock delay value */
98 writeb(0x00, &ss->regs->spckd);
100 /* Set SSL negation delay value */
101 writeb(0x00, &ss->regs->sslnd);
103 /* Set next-access delay value */
104 writeb(0x00, &ss->regs->spnd);
106 /* Set equence command */
107 writew(SPCMD_INIT2, &ss->regs->spcmd0);
109 /* Reset transfer and receive Buffer */
110 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
112 /* Clear transfer and receive Buffer control bit */
113 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
115 /* Set equence control method. Use equence0 only */
116 writeb(0x00, &ss->regs->spscr);
118 /* Enable SPI function */
119 setbits_8(&ss->regs->spcr, SPCR_SPE);
122 static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
124 /* Set master mode only */
125 writeb(SPCR_MSTR, &ss->regs->spcr);
128 writew(SPCMD_INIT1, &ss->regs->spcmd0);
130 /* Reset transfer and receive Buffer */
131 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
133 /* Clear transfer and receive Buffer control bit */
134 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
136 /* Set equence control method. Use equence0 only */
137 writeb(0x00, &ss->regs->spscr);
139 /* Enable SPI function */
140 setbits_8(&ss->regs->spcr, SPCR_SPE);
143 static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
145 /* Disable SPI Function */
146 clrbits_8(&ss->regs->spcr, SPCR_SPE);
149 static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
150 const void *dout, void *din, unsigned long flags)
154 u8 dtdata = 0, drdata;
155 u8 *tdata = &dtdata, *rdata = &drdata;
156 u32 *spbmul0 = &ss->regs->spbmul0;
158 if (dout == NULL && din == NULL) {
159 if (flags & SPI_XFER_END)
160 sh_qspi_cs_deactivate(ss);
165 log_warning("bitlen is not 8bit aligned %d", bitlen);
171 if (flags & SPI_XFER_BEGIN) {
172 sh_qspi_cs_activate(ss);
174 /* Set 1048576 byte */
175 writel(0x100000, spbmul0);
178 if (flags & SPI_XFER_END)
179 writel(nbyte, spbmul0);
189 * Check if there is 32 Byte chunk and if there is, transfer
190 * it in one burst, otherwise transfer on byte-by-byte basis.
192 chunk = (nbyte >= 32) ? 32 : 1;
194 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
195 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
197 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
202 for (i = 0; i < chunk; i++) {
203 writeb(*tdata, &ss->regs->spdr);
208 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
213 for (i = 0; i < chunk; i++) {
214 *rdata = readb(&ss->regs->spdr);
222 if (flags & SPI_XFER_END)
223 sh_qspi_cs_deactivate(ss);
228 #if !CONFIG_IS_ENABLED(DM_SPI)
229 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
231 return container_of(slave, struct sh_qspi_slave, slave);
234 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
239 void spi_cs_activate(struct spi_slave *slave)
241 struct sh_qspi_slave *ss = to_sh_qspi(slave);
243 sh_qspi_cs_activate(ss);
246 void spi_cs_deactivate(struct spi_slave *slave)
248 struct sh_qspi_slave *ss = to_sh_qspi(slave);
250 sh_qspi_cs_deactivate(ss);
253 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
254 unsigned int max_hz, unsigned int mode)
256 struct sh_qspi_slave *ss;
258 if (!spi_cs_is_valid(bus, cs))
261 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
263 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
267 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
275 void spi_free_slave(struct spi_slave *slave)
277 struct sh_qspi_slave *spi = to_sh_qspi(slave);
282 int spi_claim_bus(struct spi_slave *slave)
287 void spi_release_bus(struct spi_slave *slave)
291 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
292 const void *dout, void *din, unsigned long flags)
294 struct sh_qspi_slave *ss = to_sh_qspi(slave);
296 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
303 static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
304 const void *dout, void *din, unsigned long flags)
306 struct udevice *bus = dev->parent;
307 struct sh_qspi_slave *ss = dev_get_plat(bus);
309 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
312 static int sh_qspi_set_speed(struct udevice *dev, uint speed)
314 /* This is a SPI NOR controller, do nothing. */
318 static int sh_qspi_set_mode(struct udevice *dev, uint mode)
320 /* This is a SPI NOR controller, do nothing. */
324 static int sh_qspi_probe(struct udevice *dev)
326 struct sh_qspi_slave *ss = dev_get_plat(dev);
333 static int sh_qspi_of_to_plat(struct udevice *dev)
335 struct sh_qspi_slave *plat = dev_get_plat(dev);
337 plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
342 static const struct dm_spi_ops sh_qspi_ops = {
343 .xfer = sh_qspi_xfer,
344 .set_speed = sh_qspi_set_speed,
345 .set_mode = sh_qspi_set_mode,
348 static const struct udevice_id sh_qspi_ids[] = {
349 { .compatible = "renesas,qspi" },
353 U_BOOT_DRIVER(sh_qspi) = {
356 .of_match = sh_qspi_ids,
358 .of_to_plat = sh_qspi_of_to_plat,
359 .plat_auto = sizeof(struct sh_qspi_slave),
360 .probe = sh_qspi_probe,