1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip Serial Flash Controller Driver
5 * Copyright (c) 2017-2021, Rockchip Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Chris Morgan <macromorgan@hotmail.com>
8 * Jon Lin <Jon.lin@rock-chips.com>
12 #include <bouncebuf.h>
15 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/iopoll.h>
24 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
25 #define SFC_CTRL_CMD_BITS_SHIFT 8
26 #define SFC_CTRL_ADDR_BITS_SHIFT 10
27 #define SFC_CTRL_DATA_BITS_SHIFT 12
31 #define SFC_IMR_RX_FULL BIT(0)
32 #define SFC_IMR_RX_UFLOW BIT(1)
33 #define SFC_IMR_TX_OFLOW BIT(2)
34 #define SFC_IMR_TX_EMPTY BIT(3)
35 #define SFC_IMR_TRAN_FINISH BIT(4)
36 #define SFC_IMR_BUS_ERR BIT(5)
37 #define SFC_IMR_NSPI_ERR BIT(6)
38 #define SFC_IMR_DMA BIT(7)
42 #define SFC_ICLR_RX_FULL BIT(0)
43 #define SFC_ICLR_RX_UFLOW BIT(1)
44 #define SFC_ICLR_TX_OFLOW BIT(2)
45 #define SFC_ICLR_TX_EMPTY BIT(3)
46 #define SFC_ICLR_TRAN_FINISH BIT(4)
47 #define SFC_ICLR_BUS_ERR BIT(5)
48 #define SFC_ICLR_NSPI_ERR BIT(6)
49 #define SFC_ICLR_DMA BIT(7)
51 /* FIFO threshold level */
53 #define SFC_FTLR_TX_SHIFT 0
54 #define SFC_FTLR_TX_MASK 0x1f
55 #define SFC_FTLR_RX_SHIFT 8
56 #define SFC_FTLR_RX_MASK 0x1f
58 /* Reset FSM and FIFO */
60 #define SFC_RCVR_RESET BIT(0)
65 /* Address Bit number */
68 /* Interrupt status */
70 #define SFC_ISR_RX_FULL_SHIFT BIT(0)
71 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
72 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
73 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
74 #define SFC_ISR_TX_FINISH_SHIFT BIT(4)
75 #define SFC_ISR_BUS_ERR_SHIFT BIT(5)
76 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
77 #define SFC_ISR_DMA_SHIFT BIT(7)
81 #define SFC_FSR_TX_IS_FULL BIT(0)
82 #define SFC_FSR_TX_IS_EMPTY BIT(1)
83 #define SFC_FSR_RX_IS_EMPTY BIT(2)
84 #define SFC_FSR_RX_IS_FULL BIT(3)
85 #define SFC_FSR_TXLV_MASK GENMASK(12, 8)
86 #define SFC_FSR_TXLV_SHIFT 8
87 #define SFC_FSR_RXLV_MASK GENMASK(20, 16)
88 #define SFC_FSR_RXLV_SHIFT 16
92 #define SFC_SR_IS_IDLE 0x0
93 #define SFC_SR_IS_BUSY 0x1
95 /* Raw interrupt status */
97 #define SFC_RISR_RX_FULL BIT(0)
98 #define SFC_RISR_RX_UNDERFLOW BIT(1)
99 #define SFC_RISR_TX_OVERFLOW BIT(2)
100 #define SFC_RISR_TX_EMPTY BIT(3)
101 #define SFC_RISR_TRAN_FINISH BIT(4)
102 #define SFC_RISR_BUS_ERR BIT(5)
103 #define SFC_RISR_NSPI_ERR BIT(6)
104 #define SFC_RISR_DMA BIT(7)
108 #define SFC_VER_3 0x3
109 #define SFC_VER_4 0x4
110 #define SFC_VER_5 0x5
112 /* Delay line controller resiter */
113 #define SFC_DLL_CTRL0 0x3C
114 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
115 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
116 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
119 #define SFC_DMA_TRIGGER 0x80
120 #define SFC_DMA_TRIGGER_START 1
122 /* Src or Dst addr for master */
123 #define SFC_DMA_ADDR 0x84
125 /* Length control register extension 32GB */
126 #define SFC_LEN_CTRL 0x88
127 #define SFC_LEN_CTRL_TRB_SEL 1
128 #define SFC_LEN_EXT 0x8C
131 #define SFC_CMD 0x100
132 #define SFC_CMD_IDX_SHIFT 0
133 #define SFC_CMD_DUMMY_SHIFT 8
134 #define SFC_CMD_DIR_SHIFT 12
135 #define SFC_CMD_DIR_RD 0
136 #define SFC_CMD_DIR_WR 1
137 #define SFC_CMD_ADDR_SHIFT 14
138 #define SFC_CMD_ADDR_0BITS 0
139 #define SFC_CMD_ADDR_24BITS 1
140 #define SFC_CMD_ADDR_32BITS 2
141 #define SFC_CMD_ADDR_XBITS 3
142 #define SFC_CMD_TRAN_BYTES_SHIFT 16
143 #define SFC_CMD_CS_SHIFT 30
146 #define SFC_ADDR 0x104
149 #define SFC_DATA 0x108
151 /* The controller and documentation reports that it supports up to 4 CS
152 * devices (0-3), however I have only been able to test a single CS (CS 0)
153 * due to the configuration of my device.
155 #define SFC_MAX_CHIPSELECT_NUM 4
157 /* The SFC can transfer max 16KB - 1 at one time
158 * we set it to 15.5KB here for alignment.
160 #define SFC_MAX_IOSIZE_VER3 (512 * 31)
162 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
164 /* DMA is only enabled for large data transmission */
165 #define SFC_DMA_TRANS_THRETHOLD (0x40)
167 /* Maximum clock values from datasheet suggest keeping clock value under
168 * 150MHz. No minimum or average value is suggested.
170 #define SFC_MAX_SPEED (150 * 1000 * 1000)
172 struct rockchip_sfc {
174 void __iomem *regbase;
184 static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
189 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
191 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
192 !(status & SFC_RCVR_RESET),
195 printf("SFC reset never finished\n");
197 /* Still need to clear the masked interrupt from RISR */
198 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
203 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
205 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
208 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
210 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
211 return SFC_MAX_IOSIZE_VER4;
213 return SFC_MAX_IOSIZE_VER3;
216 static int rockchip_sfc_init(struct rockchip_sfc *sfc)
218 writel(0, sfc->regbase + SFC_CTRL);
219 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
220 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
225 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
227 struct rockchip_sfc *sfc = dev_get_plat(bus);
229 sfc->regbase = dev_read_addr_ptr(bus);
230 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
231 sfc->use_dma = false;
235 #if CONFIG_IS_ENABLED(CLK)
238 ret = clk_get_by_index(bus, 0, &sfc->clk);
240 printf("Could not get clock for %s: %d\n", bus->name, ret);
244 ret = clk_get_by_index(bus, 1, &sfc->hclk);
246 printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
254 static int rockchip_sfc_probe(struct udevice *bus)
256 struct rockchip_sfc *sfc = dev_get_plat(bus);
259 #if CONFIG_IS_ENABLED(CLK)
260 ret = clk_enable(&sfc->hclk);
262 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);
264 ret = clk_enable(&sfc->clk);
266 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);
269 ret = rockchip_sfc_init(sfc);
273 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
274 sfc->version = rockchip_sfc_get_version(sfc);
275 sfc->max_freq = SFC_MAX_SPEED;
281 #if CONFIG_IS_ENABLED(CLK)
282 clk_disable(&sfc->clk);
283 clk_disable(&sfc->hclk);
289 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
294 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
295 status & SFC_FSR_TXLV_MASK,
298 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
303 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
306 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
311 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
312 status & SFC_FSR_RXLV_MASK,
315 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
320 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
323 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
325 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
327 * SFC not support output DUMMY cycles right after CMD cycles, so
328 * treat it as ADDR cycles.
330 op->addr.nbytes = op->dummy.nbytes;
331 op->addr.buswidth = op->dummy.buswidth;
332 op->addr.val = 0xFFFFFFFFF;
334 op->dummy.nbytes = 0;
338 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
342 /* Wait for the DMA interrupt status */
343 tbase = get_timer(0);
344 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
345 if (get_timer(tbase) > timeout) {
346 printf("dma timeout\n");
347 rockchip_sfc_reset(sfc);
355 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
360 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
361 struct spi_slave *mem,
362 const struct spi_mem_op *op,
365 struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
366 u32 ctrl = 0, cmd = 0;
369 cmd = op->cmd.opcode;
370 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
373 if (op->addr.nbytes) {
374 if (op->addr.nbytes == 4) {
375 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
376 } else if (op->addr.nbytes == 3) {
377 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
379 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
380 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
383 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
387 if (op->dummy.nbytes) {
388 if (op->dummy.buswidth == 4)
389 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
390 else if (op->dummy.buswidth == 2)
391 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
393 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
397 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
398 writel(len, sfc->regbase + SFC_LEN_EXT);
400 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
402 if (op->data.dir == SPI_MEM_DATA_OUT)
403 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
405 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
407 if (!len && op->addr.nbytes)
408 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
410 /* set the Controller */
411 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
412 cmd |= plat->cs << SFC_CMD_CS_SHIFT;
414 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
415 op->addr.nbytes, op->addr.buswidth,
416 op->dummy.nbytes, op->dummy.buswidth);
417 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
418 ctrl, cmd, op->addr.val, len);
420 writel(ctrl, sfc->regbase + SFC_CTRL);
421 writel(cmd, sfc->regbase + SFC_CMD);
423 writel(op->addr.val, sfc->regbase + SFC_ADDR);
428 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
430 u8 bytes = len & 0x3;
438 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
441 write_words = min_t(u32, tx_level, dwords);
442 writesl(sfc->regbase + SFC_DATA, buf, write_words);
443 buf += write_words << 2;
444 dwords -= write_words;
447 /* write the rest non word aligned bytes */
449 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
452 memcpy(&tmp, buf, bytes);
453 writel(tmp, sfc->regbase + SFC_DATA);
459 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
461 u8 bytes = len & 0x3;
467 /* word aligned access only */
470 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
473 read_words = min_t(u32, rx_level, dwords);
474 readsl(sfc->regbase + SFC_DATA, buf, read_words);
475 buf += read_words << 2;
476 dwords -= read_words;
479 /* read the rest non word aligned bytes */
481 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
484 tmp = readl(sfc->regbase + SFC_DATA);
485 memcpy(buf, &tmp, bytes);
491 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
493 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
494 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
495 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
500 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
501 const struct spi_mem_op *op, u32 len)
503 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
505 if (op->data.dir == SPI_MEM_DATA_OUT)
506 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
508 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
511 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
512 const struct spi_mem_op *op, u32 len)
514 struct bounce_buffer bb;
515 unsigned int bb_flags;
519 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
521 if (op->data.dir == SPI_MEM_DATA_OUT) {
522 dma_buf = (void *)op->data.buf.out;
523 bb_flags = GEN_BB_READ;
525 dma_buf = (void *)op->data.buf.in;
526 bb_flags = GEN_BB_WRITE;
529 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
533 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
534 rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
535 bounce_buffer_stop(&bb);
540 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
545 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
546 !(status & SFC_SR_IS_BUSY),
549 dev_err(sfc->dev, "wait sfc idle timeout\n");
550 rockchip_sfc_reset(sfc);
558 static int rockchip_sfc_exec_op(struct spi_slave *mem,
559 const struct spi_mem_op *op)
561 struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
562 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
565 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
566 rockchip_sfc_xfer_setup(sfc, mem, op, len);
568 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD)
569 ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
571 ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
574 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
580 return rockchip_sfc_xfer_done(sfc, 100000);
583 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
585 struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
587 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
592 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
594 struct rockchip_sfc *sfc = dev_get_plat(bus);
596 if (speed > sfc->max_freq)
597 speed = sfc->max_freq;
599 if (speed == sfc->speed)
602 #if CONFIG_IS_ENABLED(CLK)
603 int ret = clk_set_rate(&sfc->clk, speed);
606 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
612 dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
617 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode)
622 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
623 .adjust_op_size = rockchip_sfc_adjust_op_size,
624 .exec_op = rockchip_sfc_exec_op,
627 static const struct dm_spi_ops rockchip_sfc_ops = {
628 .mem_ops = &rockchip_sfc_mem_ops,
629 .set_speed = rockchip_sfc_set_speed,
630 .set_mode = rockchip_sfc_set_mode,
633 static const struct udevice_id rockchip_sfc_ids[] = {
634 { .compatible = "rockchip,sfc"},
638 U_BOOT_DRIVER(rockchip_sfc_driver) = {
639 .name = "rockchip_sfc",
641 .of_match = rockchip_sfc_ids,
642 .ops = &rockchip_sfc_ops,
643 .of_to_plat = rockchip_sfc_ofdata_to_platdata,
644 .plat_auto = sizeof(struct rockchip_sfc),
645 .probe = rockchip_sfc_probe,