2 * spi driver for rockchip
4 * (C) Copyright 2015 Google, Inc
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <dm/pinctrl.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Change to 1 to output registers at the start of each transaction */
27 #define DEBUG_RK_SPI 0
29 struct rockchip_spi_platdata {
30 s32 frequency; /* Default clock frequency, -1 for none */
32 uint deactivate_delay_us; /* Delay to wait after deactivate */
33 uint activate_delay_us; /* Delay to wait after activate */
36 struct rockchip_spi_priv {
37 struct rockchip_spi *regs;
39 unsigned int max_freq;
41 ulong last_transaction_us; /* Time of last transaction end */
42 u8 bits_per_word; /* max 16 bits per word */
44 unsigned int speed_hz;
45 unsigned int last_speed_hz;
50 #define SPI_FIFO_DEPTH 32
52 static void rkspi_dump_regs(struct rockchip_spi *regs)
54 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
55 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
56 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
57 debug("ser: \t\t0x%08x\n", readl(®s->ser));
58 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
59 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
60 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
61 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
62 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
63 debug("sr: \t\t0x%08x\n", readl(®s->sr));
64 debug("imr: \t\t0x%08x\n", readl(®s->imr));
65 debug("isr: \t\t0x%08x\n", readl(®s->isr));
66 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
67 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
68 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
71 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
73 writel(enable ? 1 : 0, ®s->enr);
76 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
80 clk_div = clk_get_divisor(priv->input_rate, speed);
81 debug("spi speed %u, div %u\n", speed, clk_div);
83 writel(clk_div, &priv->regs->baudr);
84 priv->last_speed_hz = speed;
87 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
92 while (readl(®s->sr) & SR_BUSY) {
93 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
94 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
102 static void spi_cs_activate(struct udevice *dev, uint cs)
104 struct udevice *bus = dev->parent;
105 struct rockchip_spi_platdata *plat = bus->platdata;
106 struct rockchip_spi_priv *priv = dev_get_priv(bus);
107 struct rockchip_spi *regs = priv->regs;
109 debug("activate cs%u\n", cs);
110 writel(1 << cs, ®s->ser);
111 if (plat->activate_delay_us)
112 udelay(plat->activate_delay_us);
115 static void spi_cs_deactivate(struct udevice *dev, uint cs)
117 struct udevice *bus = dev->parent;
118 struct rockchip_spi_platdata *plat = bus->platdata;
119 struct rockchip_spi_priv *priv = dev_get_priv(bus);
120 struct rockchip_spi *regs = priv->regs;
122 debug("deactivate cs%u\n", cs);
123 writel(0, ®s->ser);
125 /* Remember time of this transaction so we can honour the bus delay */
126 if (plat->deactivate_delay_us)
127 priv->last_transaction_us = timer_get_us();
130 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
132 struct rockchip_spi_platdata *plat = bus->platdata;
133 struct rockchip_spi_priv *priv = dev_get_priv(bus);
134 const void *blob = gd->fdt_blob;
135 int node = bus->of_offset;
138 plat->base = dev_get_addr(bus);
140 ret = clk_get_by_index(bus, 0, &priv->clk);
142 debug("%s: Could not get clock for %s: %d\n", __func__,
147 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
149 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
150 "spi-deactivate-delay", 0);
151 plat->activate_delay_us = fdtdec_get_int(blob, node,
152 "spi-activate-delay", 0);
153 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
154 __func__, (uint)plat->base, plat->frequency,
155 plat->deactivate_delay_us);
160 static int rockchip_spi_probe(struct udevice *bus)
162 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
163 struct rockchip_spi_priv *priv = dev_get_priv(bus);
166 debug("%s: probe\n", __func__);
167 priv->regs = (struct rockchip_spi *)plat->base;
169 priv->last_transaction_us = timer_get_us();
170 priv->max_freq = plat->frequency;
173 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
174 * is the assumed speed for CLK_GENERAL.
176 ret = clk_set_rate(&priv->clk, 99000000);
178 debug("%s: Failed to set clock: %d\n", __func__, ret);
181 priv->input_rate = ret;
182 debug("%s: rate = %u\n", __func__, priv->input_rate);
183 priv->bits_per_word = 8;
184 priv->tmode = TMOD_TR; /* Tx & Rx */
189 static int rockchip_spi_claim_bus(struct udevice *dev)
191 struct udevice *bus = dev->parent;
192 struct rockchip_spi_priv *priv = dev_get_priv(bus);
193 struct rockchip_spi *regs = priv->regs;
197 /* Disable the SPI hardware */
198 rkspi_enable_chip(regs, 0);
200 switch (priv->bits_per_word) {
204 spi_tf = HALF_WORD_OFF;
209 spi_tf = HALF_WORD_ON;
212 debug("%s: unsupported bits: %dbits\n", __func__,
213 priv->bits_per_word);
214 return -EPROTONOSUPPORT;
217 if (priv->speed_hz != priv->last_speed_hz)
218 rkspi_set_clk(priv, priv->speed_hz);
221 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
223 /* Data Frame Size */
224 ctrlr0 |= spi_dfs << DFS_SHIFT;
226 /* set SPI mode 0..3 */
227 if (priv->mode & SPI_CPOL)
228 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
229 if (priv->mode & SPI_CPHA)
230 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
232 /* Chip Select Mode */
233 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
235 /* SSN to Sclk_out delay */
236 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
238 /* Serial Endian Mode */
239 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
242 ctrlr0 |= FBM_MSB << FBM_SHIFT;
244 /* Byte and Halfword Transform */
245 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
247 /* Rxd Sample Delay */
248 ctrlr0 |= 0 << RXDSD_SHIFT;
251 ctrlr0 |= FRF_SPI << FRF_SHIFT;
254 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
256 writel(ctrlr0, ®s->ctrlr0);
261 static int rockchip_spi_release_bus(struct udevice *dev)
263 struct udevice *bus = dev->parent;
264 struct rockchip_spi_priv *priv = dev_get_priv(bus);
266 rkspi_enable_chip(priv->regs, false);
271 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
272 const void *dout, void *din, unsigned long flags)
274 struct udevice *bus = dev->parent;
275 struct rockchip_spi_priv *priv = dev_get_priv(bus);
276 struct rockchip_spi *regs = priv->regs;
277 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
278 int len = bitlen >> 3;
279 const u8 *out = dout;
284 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
287 rkspi_dump_regs(regs);
289 /* Assert CS before transfer */
290 if (flags & SPI_XFER_BEGIN)
291 spi_cs_activate(dev, slave_plat->cs);
294 int todo = min(len, 0xffff);
296 rkspi_enable_chip(regs, false);
297 writel(todo - 1, ®s->ctrlr1);
298 rkspi_enable_chip(regs, true);
302 while (toread || towrite) {
303 u32 status = readl(®s->sr);
305 if (towrite && !(status & SR_TF_FULL)) {
306 writel(out ? *out++ : 0, regs->txdr);
309 if (toread && !(status & SR_RF_EMPT)) {
310 u32 byte = readl(regs->rxdr);
317 ret = rkspi_wait_till_not_busy(regs);
323 /* Deassert CS after transfer */
324 if (flags & SPI_XFER_END)
325 spi_cs_deactivate(dev, slave_plat->cs);
327 rkspi_enable_chip(regs, false);
332 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
334 struct rockchip_spi_priv *priv = dev_get_priv(bus);
336 if (speed > ROCKCHIP_SPI_MAX_RATE)
338 if (speed > priv->max_freq)
339 speed = priv->max_freq;
340 priv->speed_hz = speed;
345 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
347 struct rockchip_spi_priv *priv = dev_get_priv(bus);
354 static const struct dm_spi_ops rockchip_spi_ops = {
355 .claim_bus = rockchip_spi_claim_bus,
356 .release_bus = rockchip_spi_release_bus,
357 .xfer = rockchip_spi_xfer,
358 .set_speed = rockchip_spi_set_speed,
359 .set_mode = rockchip_spi_set_mode,
361 * cs_info is not needed, since we require all chip selects to be
362 * in the device tree explicitly
366 static const struct udevice_id rockchip_spi_ids[] = {
367 { .compatible = "rockchip,rk3288-spi" },
371 U_BOOT_DRIVER(rockchip_spi) = {
372 .name = "rockchip_spi",
374 .of_match = rockchip_spi_ids,
375 .ops = &rockchip_spi_ops,
376 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
377 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
378 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
379 .probe = rockchip_spi_probe,