2 * spi driver for rockchip
4 * (C) Copyright 2015 Google, Inc
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <dt-structs.h>
18 #include <linux/errno.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/periph.h>
22 #include <dm/pinctrl.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 /* Change to 1 to output registers at the start of each transaction */
28 #define DEBUG_RK_SPI 0
30 struct rockchip_spi_platdata {
31 #if CONFIG_IS_ENABLED(OF_PLATDATA)
32 struct dtd_rockchip_rk3288_spi of_plat;
34 s32 frequency; /* Default clock frequency, -1 for none */
36 uint deactivate_delay_us; /* Delay to wait after deactivate */
37 uint activate_delay_us; /* Delay to wait after activate */
40 struct rockchip_spi_priv {
41 struct rockchip_spi *regs;
43 unsigned int max_freq;
45 ulong last_transaction_us; /* Time of last transaction end */
46 u8 bits_per_word; /* max 16 bits per word */
48 unsigned int speed_hz;
49 unsigned int last_speed_hz;
54 #define SPI_FIFO_DEPTH 32
56 static void rkspi_dump_regs(struct rockchip_spi *regs)
58 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
59 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
60 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
61 debug("ser: \t\t0x%08x\n", readl(®s->ser));
62 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
63 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
64 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
65 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
66 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
67 debug("sr: \t\t0x%08x\n", readl(®s->sr));
68 debug("imr: \t\t0x%08x\n", readl(®s->imr));
69 debug("isr: \t\t0x%08x\n", readl(®s->isr));
70 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
71 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
72 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
75 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
77 writel(enable ? 1 : 0, ®s->enr);
80 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
84 clk_div = clk_get_divisor(priv->input_rate, speed);
85 debug("spi speed %u, div %u\n", speed, clk_div);
87 writel(clk_div, &priv->regs->baudr);
88 priv->last_speed_hz = speed;
91 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
96 while (readl(®s->sr) & SR_BUSY) {
97 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
98 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
106 static void spi_cs_activate(struct udevice *dev, uint cs)
108 struct udevice *bus = dev->parent;
109 struct rockchip_spi_platdata *plat = bus->platdata;
110 struct rockchip_spi_priv *priv = dev_get_priv(bus);
111 struct rockchip_spi *regs = priv->regs;
113 debug("activate cs%u\n", cs);
114 writel(1 << cs, ®s->ser);
115 if (plat->activate_delay_us)
116 udelay(plat->activate_delay_us);
119 static void spi_cs_deactivate(struct udevice *dev, uint cs)
121 struct udevice *bus = dev->parent;
122 struct rockchip_spi_platdata *plat = bus->platdata;
123 struct rockchip_spi_priv *priv = dev_get_priv(bus);
124 struct rockchip_spi *regs = priv->regs;
126 debug("deactivate cs%u\n", cs);
127 writel(0, ®s->ser);
129 /* Remember time of this transaction so we can honour the bus delay */
130 if (plat->deactivate_delay_us)
131 priv->last_transaction_us = timer_get_us();
134 #if CONFIG_IS_ENABLED(OF_PLATDATA)
135 static int conv_of_platdata(struct udevice *dev)
137 struct rockchip_spi_platdata *plat = dev->platdata;
138 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
139 struct rockchip_spi_priv *priv = dev_get_priv(dev);
142 plat->base = dtplat->reg[0];
143 plat->frequency = 20000000;
144 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
153 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
155 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
156 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
157 struct rockchip_spi_priv *priv = dev_get_priv(bus);
158 const void *blob = gd->fdt_blob;
159 int node = bus->of_offset;
162 plat->base = dev_get_addr(bus);
164 ret = clk_get_by_index(bus, 0, &priv->clk);
166 debug("%s: Could not get clock for %s: %d\n", __func__,
171 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
173 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
174 "spi-deactivate-delay", 0);
175 plat->activate_delay_us = fdtdec_get_int(blob, node,
176 "spi-activate-delay", 0);
177 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
178 __func__, (uint)plat->base, plat->frequency,
179 plat->deactivate_delay_us);
185 static int rockchip_spi_probe(struct udevice *bus)
187 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
188 struct rockchip_spi_priv *priv = dev_get_priv(bus);
191 debug("%s: probe\n", __func__);
192 #if CONFIG_IS_ENABLED(OF_PLATDATA)
193 ret = conv_of_platdata(bus);
197 priv->regs = (struct rockchip_spi *)plat->base;
199 priv->last_transaction_us = timer_get_us();
200 priv->max_freq = plat->frequency;
203 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
204 * is the assumed speed for CLK_GENERAL.
206 ret = clk_set_rate(&priv->clk, 99000000);
208 debug("%s: Failed to set clock: %d\n", __func__, ret);
211 priv->input_rate = ret;
212 debug("%s: rate = %u\n", __func__, priv->input_rate);
213 priv->bits_per_word = 8;
214 priv->tmode = TMOD_TR; /* Tx & Rx */
219 static int rockchip_spi_claim_bus(struct udevice *dev)
221 struct udevice *bus = dev->parent;
222 struct rockchip_spi_priv *priv = dev_get_priv(bus);
223 struct rockchip_spi *regs = priv->regs;
227 /* Disable the SPI hardware */
228 rkspi_enable_chip(regs, 0);
230 switch (priv->bits_per_word) {
234 spi_tf = HALF_WORD_OFF;
239 spi_tf = HALF_WORD_ON;
242 debug("%s: unsupported bits: %dbits\n", __func__,
243 priv->bits_per_word);
244 return -EPROTONOSUPPORT;
247 if (priv->speed_hz != priv->last_speed_hz)
248 rkspi_set_clk(priv, priv->speed_hz);
251 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
253 /* Data Frame Size */
254 ctrlr0 |= spi_dfs << DFS_SHIFT;
256 /* set SPI mode 0..3 */
257 if (priv->mode & SPI_CPOL)
258 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
259 if (priv->mode & SPI_CPHA)
260 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
262 /* Chip Select Mode */
263 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
265 /* SSN to Sclk_out delay */
266 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
268 /* Serial Endian Mode */
269 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
272 ctrlr0 |= FBM_MSB << FBM_SHIFT;
274 /* Byte and Halfword Transform */
275 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
277 /* Rxd Sample Delay */
278 ctrlr0 |= 0 << RXDSD_SHIFT;
281 ctrlr0 |= FRF_SPI << FRF_SHIFT;
284 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
286 writel(ctrlr0, ®s->ctrlr0);
291 static int rockchip_spi_release_bus(struct udevice *dev)
293 struct udevice *bus = dev->parent;
294 struct rockchip_spi_priv *priv = dev_get_priv(bus);
296 rkspi_enable_chip(priv->regs, false);
301 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
302 const void *dout, void *din, unsigned long flags)
304 struct udevice *bus = dev->parent;
305 struct rockchip_spi_priv *priv = dev_get_priv(bus);
306 struct rockchip_spi *regs = priv->regs;
307 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
308 int len = bitlen >> 3;
309 const u8 *out = dout;
314 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
317 rkspi_dump_regs(regs);
319 /* Assert CS before transfer */
320 if (flags & SPI_XFER_BEGIN)
321 spi_cs_activate(dev, slave_plat->cs);
324 int todo = min(len, 0xffff);
326 rkspi_enable_chip(regs, false);
327 writel(todo - 1, ®s->ctrlr1);
328 rkspi_enable_chip(regs, true);
332 while (toread || towrite) {
333 u32 status = readl(®s->sr);
335 if (towrite && !(status & SR_TF_FULL)) {
336 writel(out ? *out++ : 0, regs->txdr);
339 if (toread && !(status & SR_RF_EMPT)) {
340 u32 byte = readl(regs->rxdr);
347 ret = rkspi_wait_till_not_busy(regs);
353 /* Deassert CS after transfer */
354 if (flags & SPI_XFER_END)
355 spi_cs_deactivate(dev, slave_plat->cs);
357 rkspi_enable_chip(regs, false);
362 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
364 struct rockchip_spi_priv *priv = dev_get_priv(bus);
366 if (speed > ROCKCHIP_SPI_MAX_RATE)
368 if (speed > priv->max_freq)
369 speed = priv->max_freq;
370 priv->speed_hz = speed;
375 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
377 struct rockchip_spi_priv *priv = dev_get_priv(bus);
384 static const struct dm_spi_ops rockchip_spi_ops = {
385 .claim_bus = rockchip_spi_claim_bus,
386 .release_bus = rockchip_spi_release_bus,
387 .xfer = rockchip_spi_xfer,
388 .set_speed = rockchip_spi_set_speed,
389 .set_mode = rockchip_spi_set_mode,
391 * cs_info is not needed, since we require all chip selects to be
392 * in the device tree explicitly
396 static const struct udevice_id rockchip_spi_ids[] = {
397 { .compatible = "rockchip,rk3288-spi" },
401 U_BOOT_DRIVER(rockchip_spi) = {
402 #if CONFIG_IS_ENABLED(OF_PLATDATA)
403 .name = "rockchip_rk3288_spi",
405 .name = "rockchip_spi",
408 .of_match = rockchip_spi_ids,
409 .ops = &rockchip_spi_ops,
410 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
411 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
412 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
413 .probe = rockchip_spi_probe,