2 * spi driver for rockchip
4 * (C) Copyright 2015 Google, Inc
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <dm/pinctrl.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Change to 1 to output registers at the start of each transaction */
27 #define DEBUG_RK_SPI 0
29 struct rockchip_spi_platdata {
31 struct udevice *pinctrl;
32 s32 frequency; /* Default clock frequency, -1 for none */
34 uint deactivate_delay_us; /* Delay to wait after deactivate */
37 struct rockchip_spi_priv {
38 struct rockchip_spi *regs;
41 unsigned int max_freq;
43 ulong last_transaction_us; /* Time of last transaction end */
44 u8 bits_per_word; /* max 16 bits per word */
46 unsigned int speed_hz;
51 #define SPI_FIFO_DEPTH 32
53 static void rkspi_dump_regs(struct rockchip_spi *regs)
55 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
56 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
57 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
58 debug("ser: \t\t0x%08x\n", readl(®s->ser));
59 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
60 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
61 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
62 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
63 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
64 debug("sr: \t\t0x%08x\n", readl(®s->sr));
65 debug("imr: \t\t0x%08x\n", readl(®s->imr));
66 debug("isr: \t\t0x%08x\n", readl(®s->isr));
67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
68 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
69 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
72 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
74 writel(enable ? 1 : 0, ®s->enr);
77 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
81 clk_div = clk_get_divisor(priv->input_rate, speed);
82 debug("spi speed %u, div %u\n", speed, clk_div);
84 writel(clk_div, &priv->regs->baudr);
87 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
92 while (readl(®s->sr) & SR_BUSY) {
93 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
94 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
102 static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
104 debug("activate cs%u\n", cs);
105 writel(1 << cs, ®s->ser);
108 static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
110 debug("deactivate cs%u\n", cs);
111 writel(0, ®s->ser);
114 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
116 struct rockchip_spi_platdata *plat = bus->platdata;
117 struct rockchip_spi_priv *priv = dev_get_priv(bus);
118 const void *blob = gd->fdt_blob;
119 int node = bus->of_offset;
122 plat->base = dev_get_addr(bus);
123 ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
126 ret = pinctrl_get_periph_id(plat->pinctrl, bus);
129 debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
133 plat->periph_id = ret;
134 ret = clk_get_by_index(bus, 0, &priv->clk);
136 debug("%s: Could not get clock for %s: %d\n", __func__,
142 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
144 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
145 "spi-deactivate-delay", 0);
146 debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
147 __func__, (uint)plat->base, plat->periph_id, plat->frequency,
148 plat->deactivate_delay_us);
153 static int rockchip_spi_probe(struct udevice *bus)
155 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
156 struct rockchip_spi_priv *priv = dev_get_priv(bus);
159 debug("%s: probe\n", __func__);
160 priv->regs = (struct rockchip_spi *)plat->base;
162 priv->last_transaction_us = timer_get_us();
163 priv->max_freq = plat->frequency;
166 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
167 * is the assumed speed for CLK_GENERAL.
169 ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
171 debug("%s: Failed to set clock: %d\n", __func__, ret);
174 priv->input_rate = ret;
175 debug("%s: rate = %u\n", __func__, priv->input_rate);
176 priv->bits_per_word = 8;
177 priv->tmode = TMOD_TR; /* Tx & Rx */
182 static int rockchip_spi_claim_bus(struct udevice *dev)
184 struct udevice *bus = dev->parent;
185 struct rockchip_spi_priv *priv = dev_get_priv(bus);
186 struct rockchip_spi *regs = priv->regs;
189 #if !CONFIG_IS_ENABLED(PINCTRL_FULL)
190 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
191 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
195 /* Disable the SPI hardware */
196 rkspi_enable_chip(regs, 0);
198 switch (priv->bits_per_word) {
202 spi_tf = HALF_WORD_OFF;
207 spi_tf = HALF_WORD_ON;
210 debug("%s: unsupported bits: %dbits\n", __func__,
211 priv->bits_per_word);
212 return -EPROTONOSUPPORT;
215 rkspi_set_clk(priv, priv->speed_hz);
218 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
220 /* Data Frame Size */
221 ctrlr0 |= spi_dfs & DFS_MASK << DFS_SHIFT;
223 /* set SPI mode 0..3 */
224 if (priv->mode & SPI_CPOL)
225 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
226 if (priv->mode & SPI_CPHA)
227 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
229 /* Chip Select Mode */
230 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
232 /* SSN to Sclk_out delay */
233 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
235 /* Serial Endian Mode */
236 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
239 ctrlr0 |= FBM_MSB << FBM_SHIFT;
241 /* Byte and Halfword Transform */
242 ctrlr0 |= (spi_tf & HALF_WORD_MASK) << HALF_WORD_TX_SHIFT;
244 /* Rxd Sample Delay */
245 ctrlr0 |= 0 << RXDSD_SHIFT;
248 ctrlr0 |= FRF_SPI << FRF_SHIFT;
251 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
253 writel(ctrlr0, ®s->ctrlr0);
254 #if !CONFIG_IS_ENABLED(PINCTRL_FULL)
255 ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
257 debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
265 static int rockchip_spi_release_bus(struct udevice *dev)
270 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
271 const void *dout, void *din, unsigned long flags)
273 struct udevice *bus = dev->parent;
274 struct rockchip_spi_priv *priv = dev_get_priv(bus);
275 struct rockchip_spi *regs = priv->regs;
276 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
277 int len = bitlen >> 3;
278 const u8 *out = dout;
283 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
286 rkspi_dump_regs(regs);
288 /* Assert CS before transfer */
289 if (flags & SPI_XFER_BEGIN)
290 spi_cs_activate(regs, slave_plat->cs);
293 int todo = min(len, 0xffff);
295 rkspi_enable_chip(regs, true);
296 writel(todo - 1, ®s->ctrlr1);
297 rkspi_enable_chip(regs, true);
301 while (toread || towrite) {
302 u32 status = readl(®s->sr);
304 if (towrite && !(status & SR_TF_FULL)) {
305 writel(out ? *out++ : 0, regs->txdr);
308 if (toread && !(status & SR_RF_EMPT)) {
309 u32 byte = readl(regs->rxdr);
316 ret = rkspi_wait_till_not_busy(regs);
322 /* Deassert CS after transfer */
323 if (flags & SPI_XFER_END)
324 spi_cs_deactivate(regs, slave_plat->cs);
326 rkspi_enable_chip(regs, false);
331 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
333 struct rockchip_spi_priv *priv = dev_get_priv(bus);
335 if (speed > ROCKCHIP_SPI_MAX_RATE)
337 if (speed > priv->max_freq)
338 speed = priv->max_freq;
339 priv->speed_hz = speed;
344 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
346 struct rockchip_spi_priv *priv = dev_get_priv(bus);
353 static const struct dm_spi_ops rockchip_spi_ops = {
354 .claim_bus = rockchip_spi_claim_bus,
355 .release_bus = rockchip_spi_release_bus,
356 .xfer = rockchip_spi_xfer,
357 .set_speed = rockchip_spi_set_speed,
358 .set_mode = rockchip_spi_set_mode,
360 * cs_info is not needed, since we require all chip selects to be
361 * in the device tree explicitly
365 static const struct udevice_id rockchip_spi_ids[] = {
366 { .compatible = "rockchip,rk3288-spi" },
370 U_BOOT_DRIVER(rockchip_spi) = {
371 .name = "rockchip_spi",
373 .of_match = rockchip_spi_ids,
374 .ops = &rockchip_spi_ops,
375 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
376 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
377 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
378 .probe = rockchip_spi_probe,