1 // SPDX-License-Identifier: GPL-2.0+
4 * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
7 * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
9 * Driver for ARM PL022 SPI Controller.
15 #include <dm/platform_data/spi_pl022.h>
17 #include <asm/global_data.h>
24 #define SSP_CPSR 0x010
25 #define SSP_IMSC 0x014
29 #define SSP_DMACR 0x024
30 #define SSP_CSR 0x030 /* vendor extension */
31 #define SSP_ITCR 0x080
32 #define SSP_ITIP 0x084
33 #define SSP_ITOP 0x088
36 #define SSP_PID0 0xFE0
37 #define SSP_PID1 0xFE4
38 #define SSP_PID2 0xFE8
39 #define SSP_PID3 0xFEC
41 #define SSP_CID0 0xFF0
42 #define SSP_CID1 0xFF4
43 #define SSP_CID2 0xFF8
44 #define SSP_CID3 0xFFC
46 /* SSP Control Register 0 - SSP_CR0 */
47 #define SSP_CR0_SPO (0x1 << 6)
48 #define SSP_CR0_SPH (0x1 << 7)
49 #define SSP_CR0_BIT_MODE(x) ((x) - 1)
50 #define SSP_SCR_MIN (0x00)
51 #define SSP_SCR_MAX (0xFF)
52 #define SSP_SCR_SHFT 8
53 #define DFLT_CLKRATE 2
55 /* SSP Control Register 1 - SSP_CR1 */
56 #define SSP_CR1_MASK_SSE (0x1 << 1)
58 #define SSP_CPSR_MIN (0x02)
59 #define SSP_CPSR_MAX (0xFE)
60 #define DFLT_PRESCALE (0x40)
62 /* SSP Status Register - SSP_SR */
63 #define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
64 #define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
65 #define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
66 #define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
67 #define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
69 struct pl022_spi_slave {
75 * ARM PL022 exists in different 'flavors'.
76 * This drivers currently support the standard variant (0x00041022), that has a
77 * 16bit wide and 8 locations deep TX/RX FIFO.
79 static int pl022_is_supported(struct pl022_spi_slave *ps)
81 /* PL022 version is 0x00041022 */
82 if ((readw(ps->base + SSP_PID0) == 0x22) &&
83 (readw(ps->base + SSP_PID1) == 0x10) &&
84 ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
85 (readw(ps->base + SSP_PID3) == 0x00))
91 static int pl022_spi_probe(struct udevice *bus)
93 struct pl022_spi_pdata *plat = dev_get_plat(bus);
94 struct pl022_spi_slave *ps = dev_get_priv(bus);
96 ps->base = ioremap(plat->addr, plat->size);
97 ps->freq = plat->freq;
99 /* Check the PL022 version */
100 if (!pl022_is_supported(ps))
103 /* 8 bits per word, high polarity and default clock rate */
104 writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
105 writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
110 static void flush(struct pl022_spi_slave *ps)
113 while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
114 readw(ps->base + SSP_DR);
115 } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
118 static int pl022_spi_claim_bus(struct udevice *dev)
120 struct udevice *bus = dev->parent;
121 struct pl022_spi_slave *ps = dev_get_priv(bus);
124 /* Enable the SPI hardware */
125 reg = readw(ps->base + SSP_CR1);
126 reg |= SSP_CR1_MASK_SSE;
127 writew(reg, ps->base + SSP_CR1);
134 static int pl022_spi_release_bus(struct udevice *dev)
136 struct udevice *bus = dev->parent;
137 struct pl022_spi_slave *ps = dev_get_priv(bus);
142 /* Disable the SPI hardware */
143 reg = readw(ps->base + SSP_CR1);
144 reg &= ~SSP_CR1_MASK_SSE;
145 writew(reg, ps->base + SSP_CR1);
150 static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
151 const void *dout, void *din, unsigned long flags)
153 struct udevice *bus = dev->parent;
154 struct pl022_spi_slave *ps = dev_get_priv(bus);
155 u32 len_tx = 0, len_rx = 0, len;
157 const u8 *txp = dout;
158 u8 *rxp = din, value;
161 /* Finish any previously submitted transfers */
165 * TODO: The controller can do non-multiple-of-8 bit
166 * transfers, but this driver currently doesn't support it.
168 * It's also not clear how such transfers are supposed to be
169 * represented as a stream of bytes...this is a limitation of
170 * the current SPI interface.
173 /* Errors always terminate an ongoing transfer */
174 flags |= SPI_XFER_END;
180 while (len_tx < len) {
181 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
182 value = txp ? *txp++ : 0;
183 writew(value, ps->base + SSP_DR);
187 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
188 value = readw(ps->base + SSP_DR);
195 while (len_rx < len_tx) {
196 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
197 value = readw(ps->base + SSP_DR);
207 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
209 return rate / (cpsdvsr * (1 + scr));
212 static int pl022_spi_set_speed(struct udevice *bus, uint speed)
214 struct pl022_spi_slave *ps = dev_get_priv(bus);
215 u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
217 u32 min, max, best_freq = 0, tmp;
221 max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
222 min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
224 if (speed > max || speed < min) {
225 pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
230 while (cpsr <= SSP_CPSR_MAX && !found) {
231 while (scr <= SSP_SCR_MAX) {
232 tmp = spi_rate(rate, cpsr, scr);
234 if (abs(speed - tmp) < abs(speed - best_freq)) {
251 writew(best_cpsr, ps->base + SSP_CPSR);
252 cr0 = readw(ps->base + SSP_CR0);
253 writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
258 static int pl022_spi_set_mode(struct udevice *bus, uint mode)
260 struct pl022_spi_slave *ps = dev_get_priv(bus);
263 reg = readw(ps->base + SSP_CR0);
264 reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
269 writew(reg, ps->base + SSP_CR0);
274 static int pl022_cs_info(struct udevice *bus, uint cs,
275 struct spi_cs_info *info)
280 static const struct dm_spi_ops pl022_spi_ops = {
281 .claim_bus = pl022_spi_claim_bus,
282 .release_bus = pl022_spi_release_bus,
283 .xfer = pl022_spi_xfer,
284 .set_speed = pl022_spi_set_speed,
285 .set_mode = pl022_spi_set_mode,
286 .cs_info = pl022_cs_info,
289 #if CONFIG_IS_ENABLED(OF_REAL)
290 static int pl022_spi_of_to_plat(struct udevice *bus)
292 struct pl022_spi_pdata *plat = dev_get_plat(bus);
293 const void *fdt = gd->fdt_blob;
294 int node = dev_of_offset(bus);
298 plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
300 ret = clk_get_by_index(bus, 0, &clkdev);
304 plat->freq = clk_get_rate(&clkdev);
309 static const struct udevice_id pl022_spi_ids[] = {
310 { .compatible = "arm,pl022-spi" },
315 U_BOOT_DRIVER(pl022_spi) = {
318 #if CONFIG_IS_ENABLED(OF_REAL)
319 .of_match = pl022_spi_ids,
320 .of_to_plat = pl022_spi_of_to_plat,
322 .ops = &pl022_spi_ops,
323 .plat_auto = sizeof(struct pl022_spi_pdata),
324 .priv_auto = sizeof(struct pl022_spi_slave),
325 .probe = pl022_spi_probe,