Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodians/u...
[platform/kernel/u-boot.git] / drivers / spi / omap3_spi.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
4  *                    Christophe Ricard <christophe.ricard@gmail.com>
5  *
6  * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
7  *
8  * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
9  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
10  *
11  * Copyright (C) 2007 Atmel Corporation
12  *
13  * Parts taken from linux/drivers/spi/omap2_mcspi.c
14  * Copyright (C) 2005, 2006 Nokia Corporation
15  *
16  * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
17  */
18
19 #include <common.h>
20 #include <dm.h>
21 #include <spi.h>
22 #include <malloc.h>
23 #include <asm/io.h>
24 #include <linux/bitops.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define OMAP4_MCSPI_REG_OFFSET  0x100
29
30 struct omap2_mcspi_platform_config {
31         unsigned int regs_offset;
32 };
33
34 /* per-register bitmasks */
35 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
36 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
37 #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE  BIT(0)
38 #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
39
40 #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
41
42 #define OMAP3_MCSPI_MODULCTRL_SINGLE    BIT(0)
43 #define OMAP3_MCSPI_MODULCTRL_MS        BIT(2)
44 #define OMAP3_MCSPI_MODULCTRL_STEST     BIT(3)
45
46 #define OMAP3_MCSPI_CHCONF_PHA          BIT(0)
47 #define OMAP3_MCSPI_CHCONF_POL          BIT(1)
48 #define OMAP3_MCSPI_CHCONF_CLKD_MASK    GENMASK(5, 2)
49 #define OMAP3_MCSPI_CHCONF_EPOL         BIT(6)
50 #define OMAP3_MCSPI_CHCONF_WL_MASK      GENMASK(11, 7)
51 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
52 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
53 #define OMAP3_MCSPI_CHCONF_TRM_MASK     GENMASK(13, 12)
54 #define OMAP3_MCSPI_CHCONF_DMAW         BIT(14)
55 #define OMAP3_MCSPI_CHCONF_DMAR         BIT(15)
56 #define OMAP3_MCSPI_CHCONF_DPE0         BIT(16)
57 #define OMAP3_MCSPI_CHCONF_DPE1         BIT(17)
58 #define OMAP3_MCSPI_CHCONF_IS           BIT(18)
59 #define OMAP3_MCSPI_CHCONF_TURBO        BIT(19)
60 #define OMAP3_MCSPI_CHCONF_FORCE        BIT(20)
61
62 #define OMAP3_MCSPI_CHSTAT_RXS          BIT(0)
63 #define OMAP3_MCSPI_CHSTAT_TXS          BIT(1)
64 #define OMAP3_MCSPI_CHSTAT_EOT          BIT(2)
65
66 #define OMAP3_MCSPI_CHCTRL_EN           BIT(0)
67 #define OMAP3_MCSPI_CHCTRL_DIS          (0 << 0)
68
69 #define OMAP3_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
70 #define MCSPI_PINDIR_D0_IN_D1_OUT       0
71 #define MCSPI_PINDIR_D0_OUT_D1_IN       1
72
73 #define OMAP3_MCSPI_MAX_FREQ            48000000
74 #define SPI_WAIT_TIMEOUT                10
75
76 /* OMAP3 McSPI registers */
77 struct mcspi_channel {
78         unsigned int chconf;            /* 0x2C, 0x40, 0x54, 0x68 */
79         unsigned int chstat;            /* 0x30, 0x44, 0x58, 0x6C */
80         unsigned int chctrl;            /* 0x34, 0x48, 0x5C, 0x70 */
81         unsigned int tx;                /* 0x38, 0x4C, 0x60, 0x74 */
82         unsigned int rx;                /* 0x3C, 0x50, 0x64, 0x78 */
83 };
84
85 struct mcspi {
86         unsigned char res1[0x10];
87         unsigned int sysconfig;         /* 0x10 */
88         unsigned int sysstatus;         /* 0x14 */
89         unsigned int irqstatus;         /* 0x18 */
90         unsigned int irqenable;         /* 0x1C */
91         unsigned int wakeupenable;      /* 0x20 */
92         unsigned int syst;              /* 0x24 */
93         unsigned int modulctrl;         /* 0x28 */
94         struct mcspi_channel channel[4];
95         /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
96         /* channel1: 0x40 - 0x50, bus 0 & 1 */
97         /* channel2: 0x54 - 0x64, bus 0 & 1 */
98         /* channel3: 0x68 - 0x78, bus 0 */
99 };
100
101 struct omap3_spi_priv {
102         struct mcspi *regs;
103         unsigned int cs;
104         unsigned int freq;
105         unsigned int mode;
106         unsigned int wordlen;
107         unsigned int pin_dir:1;
108 };
109
110 static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
111 {
112         writel(val, &priv->regs->channel[priv->cs].chconf);
113         /* Flash post writes to make immediate effect */
114         readl(&priv->regs->channel[priv->cs].chconf);
115 }
116
117 static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
118 {
119         writel(enable, &priv->regs->channel[priv->cs].chctrl);
120         /* Flash post writes to make immediate effect */
121         readl(&priv->regs->channel[priv->cs].chctrl);
122 }
123
124 static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
125                            const void *txp, unsigned long flags)
126 {
127         ulong start;
128         int i, chconf;
129
130         chconf = readl(&priv->regs->channel[priv->cs].chconf);
131
132         /* Enable the channel */
133         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
134
135         chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
136         chconf |= (priv->wordlen - 1) << 7;
137         chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
138         chconf |= OMAP3_MCSPI_CHCONF_FORCE;
139         omap3_spi_write_chconf(priv, chconf);
140
141         for (i = 0; i < len; i++) {
142                 /* wait till TX register is empty (TXS == 1) */
143                 start = get_timer(0);
144                 while (!(readl(&priv->regs->channel[priv->cs].chstat) &
145                          OMAP3_MCSPI_CHSTAT_TXS)) {
146                         if (get_timer(start) > SPI_WAIT_TIMEOUT) {
147                                 printf("SPI TXS timed out, status=0x%08x\n",
148                                         readl(&priv->regs->channel[priv->cs].chstat));
149                                 return -1;
150                         }
151                 }
152                 /* Write the data */
153                 unsigned int *tx = &priv->regs->channel[priv->cs].tx;
154                 if (priv->wordlen > 16)
155                         writel(((u32 *)txp)[i], tx);
156                 else if (priv->wordlen > 8)
157                         writel(((u16 *)txp)[i], tx);
158                 else
159                         writel(((u8 *)txp)[i], tx);
160         }
161
162         /* wait to finish of transfer */
163         while ((readl(&priv->regs->channel[priv->cs].chstat) &
164                         (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
165                         (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
166                 ;
167
168         /* Disable the channel otherwise the next immediate RX will get affected */
169         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
170
171         if (flags & SPI_XFER_END) {
172
173                 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
174                 omap3_spi_write_chconf(priv, chconf);
175         }
176         return 0;
177 }
178
179 static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
180                           void *rxp, unsigned long flags)
181 {
182         int i, chconf;
183         ulong start;
184
185         chconf = readl(&priv->regs->channel[priv->cs].chconf);
186
187         /* Enable the channel */
188         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
189
190         chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
191         chconf |= (priv->wordlen - 1) << 7;
192         chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
193         chconf |= OMAP3_MCSPI_CHCONF_FORCE;
194         omap3_spi_write_chconf(priv, chconf);
195
196         writel(0, &priv->regs->channel[priv->cs].tx);
197
198         for (i = 0; i < len; i++) {
199                 start = get_timer(0);
200                 /* Wait till RX register contains data (RXS == 1) */
201                 while (!(readl(&priv->regs->channel[priv->cs].chstat) &
202                          OMAP3_MCSPI_CHSTAT_RXS)) {
203                         if (get_timer(start) > SPI_WAIT_TIMEOUT) {
204                                 printf("SPI RXS timed out, status=0x%08x\n",
205                                         readl(&priv->regs->channel[priv->cs].chstat));
206                                 return -1;
207                         }
208                 }
209
210                 /* Disable the channel to prevent furher receiving */
211                 if (i == (len - 1))
212                         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
213
214                 /* Read the data */
215                 unsigned int *rx = &priv->regs->channel[priv->cs].rx;
216                 if (priv->wordlen > 16)
217                         ((u32 *)rxp)[i] = readl(rx);
218                 else if (priv->wordlen > 8)
219                         ((u16 *)rxp)[i] = (u16)readl(rx);
220                 else
221                         ((u8 *)rxp)[i] = (u8)readl(rx);
222         }
223
224         if (flags & SPI_XFER_END) {
225                 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
226                 omap3_spi_write_chconf(priv, chconf);
227         }
228
229         return 0;
230 }
231
232 /*McSPI Transmit Receive Mode*/
233 static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
234                           const void *txp, void *rxp, unsigned long flags)
235 {
236         ulong start;
237         int chconf, i = 0;
238
239         chconf = readl(&priv->regs->channel[priv->cs].chconf);
240
241         /*Enable SPI channel*/
242         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
243
244         /*set TRANSMIT-RECEIVE Mode*/
245         chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
246         chconf |= (priv->wordlen - 1) << 7;
247         chconf |= OMAP3_MCSPI_CHCONF_FORCE;
248         omap3_spi_write_chconf(priv, chconf);
249
250         /*Shift in and out 1 byte at time*/
251         for (i=0; i < len; i++){
252                 /* Write: wait for TX empty (TXS == 1)*/
253                 start = get_timer(0);
254                 while (!(readl(&priv->regs->channel[priv->cs].chstat) &
255                          OMAP3_MCSPI_CHSTAT_TXS)) {
256                         if (get_timer(start) > SPI_WAIT_TIMEOUT) {
257                                 printf("SPI TXS timed out, status=0x%08x\n",
258                                         readl(&priv->regs->channel[priv->cs].chstat));
259                                 return -1;
260                         }
261                 }
262                 /* Write the data */
263                 unsigned int *tx = &priv->regs->channel[priv->cs].tx;
264                 if (priv->wordlen > 16)
265                         writel(((u32 *)txp)[i], tx);
266                 else if (priv->wordlen > 8)
267                         writel(((u16 *)txp)[i], tx);
268                 else
269                         writel(((u8 *)txp)[i], tx);
270
271                 /*Read: wait for RX containing data (RXS == 1)*/
272                 start = get_timer(0);
273                 while (!(readl(&priv->regs->channel[priv->cs].chstat) &
274                          OMAP3_MCSPI_CHSTAT_RXS)) {
275                         if (get_timer(start) > SPI_WAIT_TIMEOUT) {
276                                 printf("SPI RXS timed out, status=0x%08x\n",
277                                         readl(&priv->regs->channel[priv->cs].chstat));
278                                 return -1;
279                         }
280                 }
281                 /* Read the data */
282                 unsigned int *rx = &priv->regs->channel[priv->cs].rx;
283                 if (priv->wordlen > 16)
284                         ((u32 *)rxp)[i] = readl(rx);
285                 else if (priv->wordlen > 8)
286                         ((u16 *)rxp)[i] = (u16)readl(rx);
287                 else
288                         ((u8 *)rxp)[i] = (u8)readl(rx);
289         }
290         /* Disable the channel */
291         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
292
293         /*if transfer must be terminated disable the channel*/
294         if (flags & SPI_XFER_END) {
295                 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
296                 omap3_spi_write_chconf(priv, chconf);
297         }
298
299         return 0;
300 }
301
302 static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
303                      const void *dout, void *din, unsigned long flags)
304 {
305         unsigned int    len;
306         int ret = -1;
307
308         if (priv->wordlen < 4 || priv->wordlen > 32) {
309                 printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
310                 return -1;
311         }
312
313         if (bitlen % priv->wordlen)
314                 return -1;
315
316         len = bitlen / priv->wordlen;
317
318         if (bitlen == 0) {       /* only change CS */
319                 int chconf = readl(&priv->regs->channel[priv->cs].chconf);
320
321                 if (flags & SPI_XFER_BEGIN) {
322                         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
323                         chconf |= OMAP3_MCSPI_CHCONF_FORCE;
324                         omap3_spi_write_chconf(priv, chconf);
325                 }
326                 if (flags & SPI_XFER_END) {
327                         chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
328                         omap3_spi_write_chconf(priv, chconf);
329                         omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
330                 }
331                 ret = 0;
332         } else {
333                 if (dout != NULL && din != NULL)
334                         ret = omap3_spi_txrx(priv, len, dout, din, flags);
335                 else if (dout != NULL)
336                         ret = omap3_spi_write(priv, len, dout, flags);
337                 else if (din != NULL)
338                         ret = omap3_spi_read(priv, len, din, flags);
339         }
340         return ret;
341 }
342
343 static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
344 {
345         uint32_t confr, div = 0;
346
347         confr = readl(&priv->regs->channel[priv->cs].chconf);
348
349         /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
350         if (priv->freq) {
351                 while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
352                                         > priv->freq)
353                         div++;
354         } else {
355                  div = 0xC;
356         }
357
358         /* set clock divisor */
359         confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
360         confr |= div << 2;
361
362         omap3_spi_write_chconf(priv, confr);
363 }
364
365 static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
366 {
367         uint32_t confr;
368
369         confr = readl(&priv->regs->channel[priv->cs].chconf);
370
371         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
372          * REVISIT: this controller could support SPI_3WIRE mode.
373          */
374         if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
375                 confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
376                 confr |= OMAP3_MCSPI_CHCONF_DPE0;
377         } else {
378                 confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
379                 confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
380         }
381
382         /* set SPI mode 0..3 */
383         confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
384         if (priv->mode & SPI_CPHA)
385                 confr |= OMAP3_MCSPI_CHCONF_PHA;
386         if (priv->mode & SPI_CPOL)
387                 confr |= OMAP3_MCSPI_CHCONF_POL;
388
389         /* set chipselect polarity; manage with FORCE */
390         if (!(priv->mode & SPI_CS_HIGH))
391                 confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
392         else
393                 confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
394
395         /* Transmit & receive mode */
396         confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
397
398         omap3_spi_write_chconf(priv, confr);
399 }
400
401 static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
402 {
403         unsigned int confr;
404
405         /* McSPI individual channel configuration */
406         confr = readl(&priv->regs->channel[priv->cs].chconf);
407
408         /* wordlength */
409         confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
410         confr |= (priv->wordlen - 1) << 7;
411
412         omap3_spi_write_chconf(priv, confr);
413 }
414
415 static void spi_reset(struct mcspi *regs)
416 {
417         unsigned int tmp;
418
419         writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
420         do {
421                 tmp = readl(&regs->sysstatus);
422         } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
423
424         writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
425                OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
426                OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
427
428         writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
429 }
430
431 static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
432 {
433         unsigned int conf;
434         /*
435          * setup when switching from (reset default) slave mode
436          * to single-channel master mode
437          */
438         conf = readl(&priv->regs->modulctrl);
439         conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
440         conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
441
442         writel(conf, &priv->regs->modulctrl);
443 }
444
445 static int omap3_spi_claim_bus(struct udevice *dev)
446 {
447         struct udevice *bus = dev->parent;
448         struct omap3_spi_priv *priv = dev_get_priv(bus);
449         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
450
451         priv->cs = slave_plat->cs;
452         priv->freq = slave_plat->max_hz;
453
454         _omap3_spi_claim_bus(priv);
455
456         return 0;
457 }
458
459 static int omap3_spi_release_bus(struct udevice *dev)
460 {
461         struct udevice *bus = dev->parent;
462         struct omap3_spi_priv *priv = dev_get_priv(bus);
463
464         writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
465
466         return 0;
467 }
468
469 static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
470 {
471         struct udevice *bus = dev->parent;
472         struct omap3_spi_priv *priv = dev_get_priv(bus);
473         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
474
475         priv->cs = slave_plat->cs;
476         priv->wordlen = wordlen;
477         _omap3_spi_set_wordlen(priv);
478
479         return 0;
480 }
481
482 static int omap3_spi_probe(struct udevice *dev)
483 {
484         struct omap3_spi_priv *priv = dev_get_priv(dev);
485         const void *blob = gd->fdt_blob;
486         int node = dev_of_offset(dev);
487
488         struct omap2_mcspi_platform_config* data =
489                 (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
490
491         priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
492         if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
493                 priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
494         else
495                 priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
496         priv->wordlen = SPI_DEFAULT_WORDLEN;
497
498         spi_reset(priv->regs);
499
500         return 0;
501 }
502
503 static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
504                             const void *dout, void *din, unsigned long flags)
505 {
506         struct udevice *bus = dev->parent;
507         struct omap3_spi_priv *priv = dev_get_priv(bus);
508
509         return _spi_xfer(priv, bitlen, dout, din, flags);
510 }
511
512 static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
513 {
514
515         struct omap3_spi_priv *priv = dev_get_priv(dev);
516
517         priv->freq = speed;
518         _omap3_spi_set_speed(priv);
519
520         return 0;
521 }
522
523 static int omap3_spi_set_mode(struct udevice *dev, uint mode)
524 {
525         struct omap3_spi_priv *priv = dev_get_priv(dev);
526
527         priv->mode = mode;
528
529         _omap3_spi_set_mode(priv);
530
531         return 0;
532 }
533
534 static const struct dm_spi_ops omap3_spi_ops = {
535         .claim_bus      = omap3_spi_claim_bus,
536         .release_bus    = omap3_spi_release_bus,
537         .set_wordlen    = omap3_spi_set_wordlen,
538         .xfer       = omap3_spi_xfer,
539         .set_speed      = omap3_spi_set_speed,
540         .set_mode       = omap3_spi_set_mode,
541         /*
542          * cs_info is not needed, since we require all chip selects to be
543          * in the device tree explicitly
544          */
545 };
546
547 static struct omap2_mcspi_platform_config omap2_pdata = {
548         .regs_offset = 0,
549 };
550
551 static struct omap2_mcspi_platform_config omap4_pdata = {
552         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
553 };
554
555 static const struct udevice_id omap3_spi_ids[] = {
556         { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
557         { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
558         { }
559 };
560
561 U_BOOT_DRIVER(omap3_spi) = {
562         .name   = "omap3_spi",
563         .id     = UCLASS_SPI,
564         .of_match = omap3_spi_ids,
565         .probe = omap3_spi_probe,
566         .ops    = &omap3_spi_ops,
567         .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
568 };