1 // SPDX-License-Identifier: GPL-2.0+
3 * NXP FlexSPI(FSPI) controller driver.
5 * Copyright (c) 2019 Michael Walle <michael@walle.cc>
6 * Copyright (c) 2019 NXP
8 * This driver was originally ported from the linux kernel v5.4-rc3, which had
11 * FlexSPI is a flexsible SPI host controller which supports two SPI
12 * channels and up to 4 external devices. Each channel supports
13 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
16 * FlexSPI controller is driven by the LUT(Look-up Table) registers
17 * LUT registers are a look-up-table for sequences of instructions.
18 * A valid sequence consists of four LUT registers.
19 * Maximum 32 LUT sequences can be programmed simultaneously.
21 * LUTs are being created at run-time based on the commands passed
22 * from the spi-mem framework, thus using single LUT index.
24 * Software triggered Flash read/write access by IP Bus.
26 * Memory mapped read access by AHB Bus.
28 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
31 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
32 * Boris Brezillon <bbrezillon@kernel.org>
33 * Frieder Schrempf <frieder.schrempf@kontron.de>
39 #include <dm/device_compat.h>
44 #include <linux/bitops.h>
45 #include <linux/kernel.h>
46 #include <linux/sizes.h>
47 #include <linux/iopoll.h>
48 #include <linux/bug.h>
49 #include <linux/err.h>
52 * The driver only uses one single LUT entry, that is updated on
53 * each call of exec_op(). Index 0 is preset at boot with a basic
54 * read operation, so let's use the last entry (31).
58 /* Registers used by the driver */
59 #define FSPI_MCR0 0x00
60 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
61 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
62 #define FSPI_MCR0_LEARN_EN BIT(15)
63 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
64 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
65 #define FSPI_MCR0_DOZE_EN BIT(12)
66 #define FSPI_MCR0_HSEN BIT(11)
67 #define FSPI_MCR0_SERCLKDIV BIT(8)
68 #define FSPI_MCR0_ATDF_EN BIT(7)
69 #define FSPI_MCR0_ARDF_EN BIT(6)
70 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
71 #define FSPI_MCR0_END_CFG(x) ((x) << 2)
72 #define FSPI_MCR0_MDIS BIT(1)
73 #define FSPI_MCR0_SWRST BIT(0)
75 #define FSPI_MCR1 0x04
76 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
77 #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
79 #define FSPI_MCR2 0x08
80 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
81 #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
82 #define FSPI_MCR2_CLRLRPHS BIT(14)
83 #define FSPI_MCR2_ABRDATSZ BIT(8)
84 #define FSPI_MCR2_ABRLEARN BIT(7)
85 #define FSPI_MCR2_ABR_READ BIT(6)
86 #define FSPI_MCR2_ABRWRITE BIT(5)
87 #define FSPI_MCR2_ABRDUMMY BIT(4)
88 #define FSPI_MCR2_ABR_MODE BIT(3)
89 #define FSPI_MCR2_ABRCADDR BIT(2)
90 #define FSPI_MCR2_ABRRADDR BIT(1)
91 #define FSPI_MCR2_ABR_CMD BIT(0)
93 #define FSPI_AHBCR 0x0c
94 #define FSPI_AHBCR_RDADDROPT BIT(6)
95 #define FSPI_AHBCR_PREF_EN BIT(5)
96 #define FSPI_AHBCR_BUFF_EN BIT(4)
97 #define FSPI_AHBCR_CACH_EN BIT(3)
98 #define FSPI_AHBCR_CLRTXBUF BIT(2)
99 #define FSPI_AHBCR_CLRRXBUF BIT(1)
100 #define FSPI_AHBCR_PAR_EN BIT(0)
102 #define FSPI_INTEN 0x10
103 #define FSPI_INTEN_SCLKSBWR BIT(9)
104 #define FSPI_INTEN_SCLKSBRD BIT(8)
105 #define FSPI_INTEN_DATALRNFL BIT(7)
106 #define FSPI_INTEN_IPTXWE BIT(6)
107 #define FSPI_INTEN_IPRXWA BIT(5)
108 #define FSPI_INTEN_AHBCMDERR BIT(4)
109 #define FSPI_INTEN_IPCMDERR BIT(3)
110 #define FSPI_INTEN_AHBCMDGE BIT(2)
111 #define FSPI_INTEN_IPCMDGE BIT(1)
112 #define FSPI_INTEN_IPCMDDONE BIT(0)
114 #define FSPI_INTR 0x14
115 #define FSPI_INTR_SCLKSBWR BIT(9)
116 #define FSPI_INTR_SCLKSBRD BIT(8)
117 #define FSPI_INTR_DATALRNFL BIT(7)
118 #define FSPI_INTR_IPTXWE BIT(6)
119 #define FSPI_INTR_IPRXWA BIT(5)
120 #define FSPI_INTR_AHBCMDERR BIT(4)
121 #define FSPI_INTR_IPCMDERR BIT(3)
122 #define FSPI_INTR_AHBCMDGE BIT(2)
123 #define FSPI_INTR_IPCMDGE BIT(1)
124 #define FSPI_INTR_IPCMDDONE BIT(0)
126 #define FSPI_LUTKEY 0x18
127 #define FSPI_LUTKEY_VALUE 0x5AF05AF0
129 #define FSPI_LCKCR 0x1C
131 #define FSPI_LCKER_LOCK 0x1
132 #define FSPI_LCKER_UNLOCK 0x2
134 #define FSPI_BUFXCR_INVALID_MSTRID 0xE
135 #define FSPI_AHBRX_BUF0CR0 0x20
136 #define FSPI_AHBRX_BUF1CR0 0x24
137 #define FSPI_AHBRX_BUF2CR0 0x28
138 #define FSPI_AHBRX_BUF3CR0 0x2C
139 #define FSPI_AHBRX_BUF4CR0 0x30
140 #define FSPI_AHBRX_BUF5CR0 0x34
141 #define FSPI_AHBRX_BUF6CR0 0x38
142 #define FSPI_AHBRX_BUF7CR0 0x3C
143 #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
145 #define FSPI_AHBRX_BUF0CR1 0x40
146 #define FSPI_AHBRX_BUF1CR1 0x44
147 #define FSPI_AHBRX_BUF2CR1 0x48
148 #define FSPI_AHBRX_BUF3CR1 0x4C
149 #define FSPI_AHBRX_BUF4CR1 0x50
150 #define FSPI_AHBRX_BUF5CR1 0x54
151 #define FSPI_AHBRX_BUF6CR1 0x58
152 #define FSPI_AHBRX_BUF7CR1 0x5C
154 #define FSPI_FLSHA1CR0 0x60
155 #define FSPI_FLSHA2CR0 0x64
156 #define FSPI_FLSHB1CR0 0x68
157 #define FSPI_FLSHB2CR0 0x6C
158 #define FSPI_FLSHXCR0_SZ_KB 10
159 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
161 #define FSPI_FLSHA1CR1 0x70
162 #define FSPI_FLSHA2CR1 0x74
163 #define FSPI_FLSHB1CR1 0x78
164 #define FSPI_FLSHB2CR1 0x7C
165 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
166 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
167 #define FSPI_FLSHXCR1_WA BIT(10)
168 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
169 #define FSPI_FLSHXCR1_TCSS(x) (x)
171 #define FSPI_FLSHA1CR2 0x80
172 #define FSPI_FLSHA2CR2 0x84
173 #define FSPI_FLSHB1CR2 0x88
174 #define FSPI_FLSHB2CR2 0x8C
175 #define FSPI_FLSHXCR2_CLRINSP BIT(24)
176 #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
177 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
178 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
179 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
180 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
182 #define FSPI_IPCR0 0xA0
184 #define FSPI_IPCR1 0xA4
185 #define FSPI_IPCR1_IPAREN BIT(31)
186 #define FSPI_IPCR1_SEQNUM_SHIFT 24
187 #define FSPI_IPCR1_SEQID_SHIFT 16
188 #define FSPI_IPCR1_IDATSZ(x) (x)
190 #define FSPI_IPCMD 0xB0
191 #define FSPI_IPCMD_TRG BIT(0)
193 #define FSPI_DLPR 0xB4
195 #define FSPI_IPRXFCR 0xB8
196 #define FSPI_IPRXFCR_CLR BIT(0)
197 #define FSPI_IPRXFCR_DMA_EN BIT(1)
198 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
200 #define FSPI_IPTXFCR 0xBC
201 #define FSPI_IPTXFCR_CLR BIT(0)
202 #define FSPI_IPTXFCR_DMA_EN BIT(1)
203 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
205 #define FSPI_DLLACR 0xC0
206 #define FSPI_DLLACR_OVRDEN BIT(8)
208 #define FSPI_DLLBCR 0xC4
209 #define FSPI_DLLBCR_OVRDEN BIT(8)
211 #define FSPI_STS0 0xE0
212 #define FSPI_STS0_DLPHB(x) ((x) << 8)
213 #define FSPI_STS0_DLPHA(x) ((x) << 4)
214 #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
215 #define FSPI_STS0_ARB_IDLE BIT(1)
216 #define FSPI_STS0_SEQ_IDLE BIT(0)
218 #define FSPI_STS1 0xE4
219 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
220 #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
221 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
222 #define FSPI_STS1_AHB_ERRID(x) (x)
224 #define FSPI_AHBSPNST 0xEC
225 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
226 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
227 #define FSPI_AHBSPNST_ACTIVE BIT(0)
229 #define FSPI_IPRXFSTS 0xF0
230 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
231 #define FSPI_IPRXFSTS_FILL(x) (x)
233 #define FSPI_IPTXFSTS 0xF4
234 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
235 #define FSPI_IPTXFSTS_FILL(x) (x)
237 #define FSPI_RFDR 0x100
238 #define FSPI_TFDR 0x180
240 #define FSPI_LUT_BASE 0x200
241 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
242 #define FSPI_LUT_REG(idx) \
243 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
245 /* register map end */
247 /* Instruction set for the LUT register. */
248 #define LUT_STOP 0x00
250 #define LUT_ADDR 0x02
251 #define LUT_CADDR_SDR 0x03
252 #define LUT_MODE 0x04
253 #define LUT_MODE2 0x05
254 #define LUT_MODE4 0x06
255 #define LUT_MODE8 0x07
256 #define LUT_NXP_WRITE 0x08
257 #define LUT_NXP_READ 0x09
258 #define LUT_LEARN_SDR 0x0A
259 #define LUT_DATSZ_SDR 0x0B
260 #define LUT_DUMMY 0x0C
261 #define LUT_DUMMY_RWDS_SDR 0x0D
262 #define LUT_JMP_ON_CS 0x1F
263 #define LUT_CMD_DDR 0x21
264 #define LUT_ADDR_DDR 0x22
265 #define LUT_CADDR_DDR 0x23
266 #define LUT_MODE_DDR 0x24
267 #define LUT_MODE2_DDR 0x25
268 #define LUT_MODE4_DDR 0x26
269 #define LUT_MODE8_DDR 0x27
270 #define LUT_WRITE_DDR 0x28
271 #define LUT_READ_DDR 0x29
272 #define LUT_LEARN_DDR 0x2A
273 #define LUT_DATSZ_DDR 0x2B
274 #define LUT_DUMMY_DDR 0x2C
275 #define LUT_DUMMY_RWDS_DDR 0x2D
278 * Calculate number of required PAD bits for LUT register.
280 * The pad stands for the number of IO lines [0:7].
281 * For example, the octal read needs eight IO lines,
282 * so you should use LUT_PAD(8). This macro
283 * returns 3 i.e. use eight (2^3) IP lines for read.
285 #define LUT_PAD(x) (fls(x) - 1)
288 * Macro for constructing the LUT entries with the following
291 * ---------------------------------------------------
292 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
293 * ---------------------------------------------------
296 #define INSTR_SHIFT 10
297 #define OPRND_SHIFT 16
299 /* Macros for constructing the LUT register. */
300 #define LUT_DEF(idx, ins, pad, opr) \
301 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
302 (opr)) << (((idx) % 2) * OPRND_SHIFT))
304 #define POLL_TOUT 5000
305 #define NXP_FSPI_MAX_CHIPSELECT 4
307 struct nxp_fspi_devtype_data {
310 unsigned int ahb_buf_size;
315 static const struct nxp_fspi_devtype_data lx2160a_data = {
316 .rxfifo = SZ_512, /* (64 * 64 bits) */
317 .txfifo = SZ_1K, /* (128 * 64 bits) */
318 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
320 .little_endian = true, /* little-endian */
325 void __iomem *iobase;
326 void __iomem *ahb_addr;
329 struct clk clk, clk_en;
330 const struct nxp_fspi_devtype_data *devtype_data;
334 * R/W functions for big- or little-endian registers:
335 * The FSPI controller's endianness is independent of
336 * the CPU core's endianness. So far, although the CPU
337 * core is little-endian the FSPI controller can use
338 * big-endian or little-endian.
340 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
342 if (f->devtype_data->little_endian)
348 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
350 if (f->devtype_data->little_endian)
351 return in_le32(addr);
353 return in_be32(addr);
356 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
369 static bool nxp_fspi_supports_op(struct spi_slave *slave,
370 const struct spi_mem_op *op)
376 bus = slave->dev->parent;
377 f = dev_get_priv(bus);
379 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
382 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
384 if (op->dummy.nbytes)
385 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
388 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
394 * The number of address bytes should be equal to or less than 4 bytes.
396 if (op->addr.nbytes > 4)
400 * If requested address value is greater than controller assigned
401 * memory mapped space, return error as it didn't fit in the range
402 * of assigned address space.
404 if (op->addr.val >= f->memmap_phy_size)
407 /* Max 64 dummy clock cycles supported */
408 if (op->dummy.buswidth &&
409 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
412 /* Max data length, check controller limits and alignment */
413 if (op->data.dir == SPI_MEM_DATA_IN &&
414 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
415 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
416 !IS_ALIGNED(op->data.nbytes, 8))))
419 if (op->data.dir == SPI_MEM_DATA_OUT &&
420 op->data.nbytes > f->devtype_data->txfifo)
426 /* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */
427 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
428 u32 mask, u32 delay_us,
429 u32 timeout_us, bool c)
433 if (!f->devtype_data->little_endian)
434 mask = (u32)cpu_to_be32(mask);
437 return readl_poll_sleep_timeout(base, reg, (reg & mask),
438 delay_us, timeout_us);
440 return readl_poll_sleep_timeout(base, reg, !(reg & mask),
441 delay_us, timeout_us);
445 * If the slave device content being changed by Write/Erase, need to
446 * invalidate the AHB buffer. This can be achieved by doing the reset
447 * of controller after setting MCR0[SWRESET] bit.
449 static inline void nxp_fspi_invalid(struct nxp_fspi *f)
454 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
455 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
457 /* w1c register, wait unit clear */
458 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
459 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
463 static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
464 const struct spi_mem_op *op)
466 void __iomem *base = f->iobase;
471 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
475 if (op->addr.nbytes) {
476 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
477 LUT_PAD(op->addr.buswidth),
478 op->addr.nbytes * 8);
482 /* dummy bytes, if needed */
483 if (op->dummy.nbytes) {
484 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
486 * Due to FlexSPI controller limitation number of PAD for dummy
487 * buswidth needs to be programmed as equal to data buswidth.
489 LUT_PAD(op->data.buswidth),
490 op->dummy.nbytes * 8 /
495 /* read/write data bytes */
496 if (op->data.nbytes) {
497 lutval[lutidx / 2] |= LUT_DEF(lutidx,
498 op->data.dir == SPI_MEM_DATA_IN ?
499 LUT_NXP_READ : LUT_NXP_WRITE,
500 LUT_PAD(op->data.buswidth),
505 /* stop condition. */
506 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
509 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
510 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
513 for (i = 0; i < ARRAY_SIZE(lutval); i++)
514 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
516 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
517 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
520 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
521 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
524 #if CONFIG_IS_ENABLED(CLK)
525 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
529 ret = clk_enable(&f->clk_en);
533 ret = clk_enable(&f->clk);
535 clk_disable(&f->clk_en);
542 static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
544 clk_disable(&f->clk);
545 clk_disable(&f->clk_en);
550 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
551 * register and start base address of the slave device.
554 * -------- <-- FLSHB2CR0
557 * B2 start address --> -------- <-- FLSHB1CR0
560 * B1 start address --> -------- <-- FLSHA2CR0
563 * A2 start address --> -------- <-- FLSHA1CR0
566 * A1 start address --> -------- (Lower address)
569 * Start base address defines the starting address range for given CS and
570 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
572 * But, different targets are having different combinations of number of CS,
573 * some targets only have single CS or two CS covering controller's full
574 * memory mapped space area.
575 * Thus, implementation is being done as independent of the size and number
576 * of the connected slave device.
577 * Assign controller memory mapped space size as the size to the connected
579 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
580 * chip-select Flash configuration register.
582 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
583 * memory mapped size of the controller.
584 * Value for rest of the CS FLSHxxCR0 register would be zero.
587 static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
591 /* Reset FLSHxxCR0 registers */
592 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
593 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
594 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
595 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
597 /* Assign controller memory mapped space as size, KBytes, of flash. */
598 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
600 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
603 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
606 static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
608 u32 len = op->data.nbytes;
610 /* Read out the data directly from the AHB buffer. */
611 memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
614 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
615 const struct spi_mem_op *op)
617 void __iomem *base = f->iobase;
619 u8 *buf = (u8 *)op->data.buf.out;
621 /* clear the TX FIFO. */
622 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
625 * Default value of water mark level is 8 bytes, hence in single
626 * write request controller can write max 8 bytes of data.
629 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
630 /* Wait for TXFIFO empty */
631 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
636 fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
637 fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
638 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
641 if (i < op->data.nbytes) {
644 /* Wait for TXFIFO empty */
645 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
650 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
651 memcpy(&data, buf + i + j, 4);
652 fspi_writel(f, data, base + FSPI_TFDR + j);
654 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
658 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
659 const struct spi_mem_op *op)
661 void __iomem *base = f->iobase;
663 int len = op->data.nbytes;
664 u8 *buf = (u8 *)op->data.buf.in;
667 * Default value of water mark level is 8 bytes, hence in single
668 * read request controller can read max 8 bytes of data.
670 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
671 /* Wait for RXFIFO available */
672 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
677 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
678 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
679 /* move the FIFO pointer */
680 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
687 buf = op->data.buf.in + i;
688 /* Wait for RXFIFO available */
689 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
694 len = op->data.nbytes - i;
695 for (j = 0; j < op->data.nbytes - i; j += 4) {
696 tmp = fspi_readl(f, base + FSPI_RFDR + j);
698 memcpy(buf + j, &tmp, size);
703 /* invalid the RXFIFO */
704 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
705 /* move the FIFO pointer */
706 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
709 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
711 void __iomem *base = f->iobase;
716 reg = fspi_readl(f, base + FSPI_IPRXFCR);
717 /* invalid RXFIFO first */
718 reg &= ~FSPI_IPRXFCR_DMA_EN;
719 reg = reg | FSPI_IPRXFCR_CLR;
720 fspi_writel(f, reg, base + FSPI_IPRXFCR);
722 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
724 * Always start the sequence at the same index since we update
725 * the LUT at each exec_op() call. And also specify the DATA
726 * length, since it's has not been specified in the LUT.
728 fspi_writel(f, op->data.nbytes |
729 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
730 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
733 /* Trigger the LUT now. */
734 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
736 /* Wait for the completion. */
737 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
738 FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
740 /* Invoke IP data read, if request is of data read. */
741 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
742 nxp_fspi_read_rxfifo(f, op);
747 static int nxp_fspi_exec_op(struct spi_slave *slave,
748 const struct spi_mem_op *op)
754 bus = slave->dev->parent;
755 f = dev_get_priv(bus);
757 /* Wait for controller being ready. */
758 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
759 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
762 nxp_fspi_prepare_lut(f, op);
764 * If we have large chunks of data, we read them through the AHB bus
765 * by accessing the mapped memory. In all other cases we use
766 * IP commands to access the flash.
768 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
769 op->data.dir == SPI_MEM_DATA_IN) {
770 nxp_fspi_read_ahb(f, op);
772 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
773 nxp_fspi_fill_txfifo(f, op);
775 err = nxp_fspi_do_op(f, op);
778 /* Invalidate the data in the AHB buffer. */
784 static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
785 struct spi_mem_op *op)
790 bus = slave->dev->parent;
791 f = dev_get_priv(bus);
793 if (op->data.dir == SPI_MEM_DATA_OUT) {
794 if (op->data.nbytes > f->devtype_data->txfifo)
795 op->data.nbytes = f->devtype_data->txfifo;
797 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
798 op->data.nbytes = f->devtype_data->ahb_buf_size;
799 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
800 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
806 static int nxp_fspi_default_setup(struct nxp_fspi *f)
808 void __iomem *base = f->iobase;
812 #if CONFIG_IS_ENABLED(CLK)
813 /* disable and unprepare clock to avoid glitch pass to controller */
814 nxp_fspi_clk_disable_unprep(f);
816 /* the default frequency, we will change it later if necessary. */
817 ret = clk_set_rate(&f->clk, 20000000);
821 ret = nxp_fspi_clk_prep_enable(f);
826 /* Reset the module */
827 /* w1c register, wait unit clear */
828 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
829 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
832 /* Disable the module */
833 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
835 /* Reset the DLL register to default value */
836 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
837 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
840 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
844 * Disable same device enable bit and configure all slave devices
847 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
848 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
849 fspi_writel(f, reg, base + FSPI_MCR2);
851 /* AHB configuration for access buffer 0~7. */
852 for (i = 0; i < 7; i++)
853 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
856 * Set ADATSZ with the maximum AHB buffer size to improve the read
859 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
860 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
862 /* prefetch and no start address alignment limitation */
863 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
866 /* AHB Read - Set lut sequence ID for all CS. */
867 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
868 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
869 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
870 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
875 static int nxp_fspi_probe(struct udevice *bus)
877 struct nxp_fspi *f = dev_get_priv(bus);
880 (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
881 nxp_fspi_default_setup(f);
886 static int nxp_fspi_claim_bus(struct udevice *dev)
890 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
893 f = dev_get_priv(bus);
895 nxp_fspi_select_mem(f, slave_plat->cs);
900 static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
902 #if CONFIG_IS_ENABLED(CLK)
903 struct nxp_fspi *f = dev_get_priv(bus);
906 nxp_fspi_clk_disable_unprep(f);
908 ret = clk_set_rate(&f->clk, speed);
912 ret = nxp_fspi_clk_prep_enable(f);
919 static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
925 static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
927 struct nxp_fspi *f = dev_get_priv(bus);
928 #if CONFIG_IS_ENABLED(CLK)
933 fdt_addr_t iobase_size;
939 iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
940 if (iobase == FDT_ADDR_T_NONE) {
941 dev_err(bus, "fspi_base regs missing\n");
944 f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
946 ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
947 if (ahb_addr == FDT_ADDR_T_NONE) {
948 dev_err(bus, "fspi_mmap regs missing\n");
951 f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
952 f->memmap_phy_size = ahb_size;
954 #if CONFIG_IS_ENABLED(CLK)
955 ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
957 dev_err(bus, "failed to get fspi_en clock\n");
961 ret = clk_get_by_name(bus, "fspi", &f->clk);
963 dev_err(bus, "failed to get fspi clock\n");
968 dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
973 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
974 .adjust_op_size = nxp_fspi_adjust_op_size,
975 .supports_op = nxp_fspi_supports_op,
976 .exec_op = nxp_fspi_exec_op,
979 static const struct dm_spi_ops nxp_fspi_ops = {
980 .claim_bus = nxp_fspi_claim_bus,
981 .set_speed = nxp_fspi_set_speed,
982 .set_mode = nxp_fspi_set_mode,
983 .mem_ops = &nxp_fspi_mem_ops,
986 static const struct udevice_id nxp_fspi_ids[] = {
987 { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
991 U_BOOT_DRIVER(nxp_fspi) = {
994 .of_match = nxp_fspi_ids,
995 .ops = &nxp_fspi_ops,
996 .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
997 .priv_auto = sizeof(struct nxp_fspi),
998 .probe = nxp_fspi_probe,