2 * Freescale i.MX28 SPI driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * NOTE: This driver only supports the SPI-controller chipselects,
23 * GPIO driven chipselects are not supported.
29 #include <asm/errno.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/imx-regs.h>
33 #include <asm/arch/sys_proto.h>
35 #define MXS_SPI_MAX_TIMEOUT 1000000
36 #define MXS_SPI_PORT_OFFSET 0x2000
37 #define MXS_SSP_CHIPSELECT_MASK 0x00300000
38 #define MXS_SSP_CHIPSELECT_SHIFT 20
40 struct mxs_spi_slave {
41 struct spi_slave slave;
44 struct mx28_ssp_regs *regs;
47 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
49 return container_of(slave, struct mxs_spi_slave, slave);
56 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
58 /* MXS SPI: 4 ports and 3 chip selects maximum */
59 if (bus > 3 || cs > 2)
65 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
66 unsigned int max_hz, unsigned int mode)
68 struct mxs_spi_slave *mxs_slave;
70 struct mx28_ssp_regs *ssp_regs;
73 if (!spi_cs_is_valid(bus, cs)) {
74 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
78 mxs_slave = malloc(sizeof(struct mxs_spi_slave));
82 addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
84 mxs_slave->slave.bus = bus;
85 mxs_slave->slave.cs = cs;
86 mxs_slave->max_khz = max_hz / 1000;
87 mxs_slave->mode = mode;
88 mxs_slave->regs = (struct mx28_ssp_regs *)addr;
89 ssp_regs = mxs_slave->regs;
91 reg = readl(&ssp_regs->hw_ssp_ctrl0);
92 reg &= ~(MXS_SSP_CHIPSELECT_MASK);
93 reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
95 writel(reg, &ssp_regs->hw_ssp_ctrl0);
96 return &mxs_slave->slave;
99 void spi_free_slave(struct spi_slave *slave)
101 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
105 int spi_claim_bus(struct spi_slave *slave)
107 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
108 struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
111 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
113 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
115 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
116 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
117 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
118 writel(reg, &ssp_regs->hw_ssp_ctrl1);
120 writel(0, &ssp_regs->hw_ssp_cmd0);
122 mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
127 void spi_release_bus(struct spi_slave *slave)
131 static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
133 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
134 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
137 static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
139 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
140 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
143 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
144 const void *dout, void *din, unsigned long flags)
146 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
147 struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
148 int len = bitlen / 8;
149 const char *tx = dout;
154 if (flags & SPI_XFER_END) {
164 if (flags & SPI_XFER_BEGIN)
165 mxs_spi_start_xfer(ssp_regs);
168 /* We transfer 1 byte */
169 writel(1, &ssp_regs->hw_ssp_xfer_size);
171 if ((flags & SPI_XFER_END) && !len)
172 mxs_spi_end_xfer(ssp_regs);
175 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
177 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
179 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
181 if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
182 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
183 printf("MXS SPI: Timeout waiting for start\n");
188 writel(*tx++, &ssp_regs->hw_ssp_data);
190 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
193 if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
194 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
195 printf("MXS SPI: Timeout waiting for data\n");
199 *rx = readl(&ssp_regs->hw_ssp_data);
203 if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
204 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
205 printf("MXS SPI: Timeout waiting for finish\n");