1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 SPI driver
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
11 * NOTE: This driver only supports the SPI-controller chipselects,
12 * GPIO driven chipselects are not supported.
21 #include <asm/cache.h>
22 #include <linux/bitops.h>
23 #include <linux/errno.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-imx/dma.h>
30 #define MXS_SPI_MAX_TIMEOUT 1000000
31 #define MXS_SPI_PORT_OFFSET 0x2000
32 #define MXS_SSP_CHIPSELECT_MASK 0x00300000
33 #define MXS_SSP_CHIPSELECT_SHIFT 20
35 #define MXSSSP_SMALL_TRANSFER 512
37 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
39 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
40 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
43 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
45 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
46 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
49 #if !CONFIG_IS_ENABLED(DM_SPI)
50 struct mxs_spi_slave {
51 struct spi_slave slave;
54 struct mxs_ssp_regs *regs;
57 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
59 return container_of(slave, struct mxs_spi_slave, slave);
64 #include <dt-structs.h>
67 #define dtd_fsl_imx_spi dtd_fsl_imx28_spi
68 #else /* CONFIG_MX23 */
69 #define dtd_fsl_imx_spi dtd_fsl_imx23_spi
72 struct mxs_spi_platdata {
73 #if CONFIG_IS_ENABLED(OF_PLATDATA)
74 struct dtd_fsl_imx_spi dtplat;
76 s32 frequency; /* Default clock frequency, -1 for none */
77 fdt_addr_t base; /* SPI IP block base address */
78 int num_cs; /* Number of CSes supported */
79 int dma_id; /* ID of the DMA channel */
80 int clk_id; /* ID of the SSP clock */
84 struct mxs_ssp_regs *regs;
85 unsigned int dma_channel;
86 unsigned int max_freq;
92 #if !CONFIG_IS_ENABLED(DM_SPI)
93 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
94 char *data, int length, int write, unsigned long flags)
96 struct mxs_ssp_regs *ssp_regs = slave->regs;
98 static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
99 char *data, int length, int write,
102 struct mxs_ssp_regs *ssp_regs = priv->regs;
105 if (flags & SPI_XFER_BEGIN)
106 mxs_spi_start_xfer(ssp_regs);
109 /* We transfer 1 byte */
110 #if defined(CONFIG_MX23)
111 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
112 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
113 #elif defined(CONFIG_MX28)
114 writel(1, &ssp_regs->hw_ssp_xfer_size);
117 if ((flags & SPI_XFER_END) && !length)
118 mxs_spi_end_xfer(ssp_regs);
121 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
123 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
125 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
127 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
128 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
129 printf("MXS SPI: Timeout waiting for start\n");
134 writel(*data++, &ssp_regs->hw_ssp_data);
136 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
139 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
140 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
141 printf("MXS SPI: Timeout waiting for data\n");
145 *data = readl(&ssp_regs->hw_ssp_data);
149 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
150 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
151 printf("MXS SPI: Timeout waiting for finish\n");
159 #if !CONFIG_IS_ENABLED(DM_SPI)
160 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
161 char *data, int length, int write, unsigned long flags)
163 struct mxs_ssp_regs *ssp_regs = slave->regs;
165 static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
166 char *data, int length, int write,
168 { struct mxs_ssp_regs *ssp_regs = priv->regs;
170 const int xfer_max_sz = 0xff00;
171 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
172 struct mxs_dma_desc *dp;
174 uint32_t cache_data_count;
175 const uint32_t dstart = (uint32_t)data;
180 #if defined(CONFIG_MX23)
181 const int mxs_spi_pio_words = 1;
182 #elif defined(CONFIG_MX28)
183 const int mxs_spi_pio_words = 4;
186 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
188 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
190 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
191 ctrl0 |= SSP_CTRL0_DATA_XFER;
193 if (flags & SPI_XFER_BEGIN)
194 ctrl0 |= SSP_CTRL0_LOCK_CS;
196 ctrl0 |= SSP_CTRL0_READ;
198 if (length % ARCH_DMA_MINALIGN)
199 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
201 cache_data_count = length;
203 /* Flush data to DRAM so DMA can pick them up */
205 flush_dcache_range(dstart, dstart + cache_data_count);
207 /* Invalidate the area, so no writeback into the RAM races with DMA */
208 invalidate_dcache_range(dstart, dstart + cache_data_count);
210 #if !CONFIG_IS_ENABLED(DM_SPI)
211 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
213 dmach = priv->dma_channel;
218 dp->address = (dma_addr_t)dp;
219 dp->cmd.address = (dma_addr_t)data;
222 * This is correct, even though it does indeed look insane.
223 * I hereby have to, wholeheartedly, thank Freescale Inc.,
224 * for always inventing insane hardware and keeping me busy
228 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
230 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
233 * The DMA controller can transfer large chunks (64kB) at
234 * time by setting the transfer length to 0. Setting tl to
235 * 0x10000 will overflow below and make .data contain 0.
236 * Otherwise, 0xff00 is the transfer maximum.
238 if (length >= 0x10000)
241 tl = min(length, xfer_max_sz);
244 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
245 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
246 MXS_DMA_DESC_HALT_ON_TERMINATE |
247 MXS_DMA_DESC_TERMINATE_FLUSH;
253 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
255 if (flags & SPI_XFER_END) {
256 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
257 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
262 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
263 * case of MX28, write only CTRL0 in case of MX23 due
264 * to the difference in register layout. It is utterly
265 * essential that the XFER_SIZE register is written on
266 * a per-descriptor basis with the same size as is the
269 dp->cmd.pio_words[0] = ctrl0;
271 dp->cmd.pio_words[1] = 0;
272 dp->cmd.pio_words[2] = 0;
273 dp->cmd.pio_words[3] = tl;
276 mxs_dma_desc_append(dmach, dp);
281 if (mxs_dma_go(dmach))
284 /* The data arrived into DRAM, invalidate cache over them */
286 invalidate_dcache_range(dstart, dstart + cache_data_count);
291 #if !CONFIG_IS_ENABLED(DM_SPI)
292 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
293 const void *dout, void *din, unsigned long flags)
295 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
296 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
298 int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
299 const void *dout, void *din, unsigned long flags)
301 struct udevice *bus = dev_get_parent(dev);
302 struct mxs_spi_priv *priv = dev_get_priv(bus);
303 struct mxs_ssp_regs *ssp_regs = priv->regs;
305 int len = bitlen / 8;
312 if (flags & SPI_XFER_END) {
313 din = (void *)&dummy;
319 /* Half-duplex only */
335 * Check for alignment, if the buffer is aligned, do DMA transfer,
336 * PIO otherwise. This is a temporary workaround until proper bounce
337 * buffer is in place.
340 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
342 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
346 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
347 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
348 #if !CONFIG_IS_ENABLED(DM_SPI)
349 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
351 return mxs_spi_xfer_pio(priv, data, len, write, flags);
354 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
355 #if !CONFIG_IS_ENABLED(DM_SPI)
356 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
358 return mxs_spi_xfer_dma(priv, data, len, write, flags);
363 #if !CONFIG_IS_ENABLED(DM_SPI)
364 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
366 /* MXS SPI: 4 ports and 3 chip selects maximum */
367 if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
373 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
374 unsigned int max_hz, unsigned int mode)
376 struct mxs_spi_slave *mxs_slave;
378 if (!spi_cs_is_valid(bus, cs)) {
379 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
383 mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
387 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
390 mxs_slave->max_khz = max_hz / 1000;
391 mxs_slave->mode = mode;
392 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
394 return &mxs_slave->slave;
401 void spi_free_slave(struct spi_slave *slave)
403 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
408 int spi_claim_bus(struct spi_slave *slave)
410 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
411 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
414 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
416 writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
417 SSP_CTRL0_BUS_WIDTH_ONE_BIT,
418 &ssp_regs->hw_ssp_ctrl0);
420 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
421 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
422 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
423 writel(reg, &ssp_regs->hw_ssp_ctrl1);
425 writel(0, &ssp_regs->hw_ssp_cmd0);
427 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
432 void spi_release_bus(struct spi_slave *slave)
436 #else /* CONFIG_DM_SPI */
437 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
438 #define MXS_SSP_IMX23_CLKID_SSP0 33
439 #define MXS_SSP_IMX28_CLKID_SSP0 46
441 static int mxs_spi_probe(struct udevice *bus)
443 struct mxs_spi_platdata *plat = dev_get_platdata(bus);
444 struct mxs_spi_priv *priv = dev_get_priv(bus);
447 debug("%s: probe\n", __func__);
449 #if CONFIG_IS_ENABLED(OF_PLATDATA)
450 struct dtd_fsl_imx_spi *dtplat = &plat->dtplat;
451 struct phandle_1_arg *p1a = &dtplat->clocks[0];
453 priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
454 priv->dma_channel = dtplat->dmas[1];
455 priv->clk_id = p1a->arg[0];
456 priv->max_freq = dtplat->spi_max_frequency;
457 plat->num_cs = dtplat->num_cs;
459 debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n",
460 (unsigned int)priv->regs, priv->max_freq, priv->clk_id);
462 priv->regs = (struct mxs_ssp_regs *)plat->base;
463 priv->max_freq = plat->frequency;
465 priv->dma_channel = plat->dma_id;
466 priv->clk_id = plat->clk_id;
469 mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg);
471 ret = mxs_dma_init_channel(priv->dma_channel);
473 printf("%s: DMA init channel error %d\n", __func__, ret);
480 static int mxs_spi_claim_bus(struct udevice *dev)
482 struct udevice *bus = dev_get_parent(dev);
483 struct mxs_spi_priv *priv = dev_get_priv(bus);
484 struct mxs_ssp_regs *ssp_regs = priv->regs;
485 int cs = spi_chip_select(dev);
488 * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
489 * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
492 * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
493 * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
497 * SSn2 b10 (which require setting WAIT_FOR_IRQ)
499 * However, for now i.MX28 SPI driver will support up till 2 CSes
503 /* Ungate SSP clock and set active CS */
504 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
505 BIT(MXS_SSP_CHIPSELECT_SHIFT) |
506 SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
511 static int mxs_spi_release_bus(struct udevice *dev)
513 struct udevice *bus = dev_get_parent(dev);
514 struct mxs_spi_priv *priv = dev_get_priv(bus);
515 struct mxs_ssp_regs *ssp_regs = priv->regs;
518 setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
523 static int mxs_spi_set_speed(struct udevice *bus, uint speed)
525 struct mxs_spi_priv *priv = dev_get_priv(bus);
527 int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
528 #else /* CONFIG_MX23 */
529 int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
531 if (speed > priv->max_freq)
532 speed = priv->max_freq;
534 debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
535 mxs_set_ssp_busclock(clkid, speed / 1000);
540 static int mxs_spi_set_mode(struct udevice *bus, uint mode)
542 struct mxs_spi_priv *priv = dev_get_priv(bus);
543 struct mxs_ssp_regs *ssp_regs = priv->regs;
547 debug("%s: mode 0x%x\n", __func__, mode);
549 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
550 reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
551 reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
552 writel(reg, &ssp_regs->hw_ssp_ctrl1);
554 /* Single bit SPI support */
555 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
560 static const struct dm_spi_ops mxs_spi_ops = {
561 .claim_bus = mxs_spi_claim_bus,
562 .release_bus = mxs_spi_release_bus,
563 .xfer = mxs_spi_xfer,
564 .set_speed = mxs_spi_set_speed,
565 .set_mode = mxs_spi_set_mode,
567 * cs_info is not needed, since we require all chip selects to be
568 * in the device tree explicitly
572 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
573 static int mxs_ofdata_to_platdata(struct udevice *bus)
575 struct mxs_spi_platdata *plat = bus->platdata;
579 plat->base = dev_read_addr(bus);
581 dev_read_u32_default(bus, "spi-max-frequency", 40000000);
582 plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
584 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
586 printf("%s: Reading 'dmas' property failed!\n", __func__);
589 plat->dma_id = prop[1];
591 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
593 printf("%s: Reading 'clocks' property failed!\n", __func__);
596 plat->clk_id = prop[1];
598 debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
599 __func__, (uint)plat->base, plat->frequency, plat->num_cs,
600 plat->dma_id, plat->clk_id);
605 static const struct udevice_id mxs_spi_ids[] = {
606 { .compatible = "fsl,imx23-spi" },
607 { .compatible = "fsl,imx28-spi" },
612 U_BOOT_DRIVER(mxs_spi) = {
614 .name = "fsl_imx28_spi",
615 #else /* CONFIG_MX23 */
616 .name = "fsl_imx23_spi",
619 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
620 .of_match = mxs_spi_ids,
621 .ofdata_to_platdata = mxs_ofdata_to_platdata,
623 .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
625 .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
626 .probe = mxs_spi_probe,