2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/imx-common/spi.h>
18 /* i.MX27 has a completely wrong register layout and register definitions in the
19 * datasheet, the correct one is in the Freescale's Linux driver */
21 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
22 "See linux mxc_spi driver from Freescale for details."
25 static unsigned long spi_bases[] = {
26 MXC_SPI_BASE_ADDRESSES
29 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
34 #define OUT MXC_GPIO_DIRECTION_OUT
36 #define reg_read readl
37 #define reg_write(a, v) writel(v, a)
39 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
40 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
43 struct mxc_spi_slave {
44 struct spi_slave slave;
47 #if defined(MXC_ECSPI)
54 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
56 return container_of(slave, struct mxc_spi_slave, slave);
59 void spi_cs_activate(struct spi_slave *slave)
61 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
63 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
66 void spi_cs_deactivate(struct spi_slave *slave)
68 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
70 gpio_set_value(mxcs->gpio,
74 u32 get_cspi_div(u32 div)
78 for (i = 0; i < 8; i++) {
86 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
87 unsigned int max_hz, unsigned int mode)
89 unsigned int ctrl_reg;
93 clk_src = mxc_get_clock(MXC_CSPI_CLK);
95 div = DIV_ROUND_UP(clk_src, max_hz);
96 div = get_cspi_div(div);
98 debug("clk %d Hz, div %d, real clk %d Hz\n",
99 max_hz, div, clk_src / (4 << div));
101 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
102 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
103 MXC_CSPICTRL_DATARATE(div) |
111 ctrl_reg |= MXC_CSPICTRL_PHA;
113 ctrl_reg |= MXC_CSPICTRL_POL;
114 if (mode & SPI_CS_HIGH)
115 ctrl_reg |= MXC_CSPICTRL_SSPOL;
116 mxcs->ctrl_reg = ctrl_reg;
123 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
124 unsigned int max_hz, unsigned int mode)
126 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
127 s32 reg_ctrl, reg_config;
128 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
129 u32 pre_div = 0, post_div = 0;
130 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
133 printf("Error: desired clock is 0\n");
138 * Reset SPI and set all CSs to master mode, if toggling
139 * between slave and master mode we might see a glitch
142 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
143 reg_write(®s->ctrl, reg_ctrl);
144 reg_ctrl |= MXC_CSPICTRL_EN;
145 reg_write(®s->ctrl, reg_ctrl);
147 if (clk_src > max_hz) {
148 pre_div = (clk_src - 1) / max_hz;
149 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
150 post_div = fls(pre_div);
153 if (post_div >= 16) {
154 printf("Error: no divider for the freq: %d\n",
158 pre_div >>= post_div;
164 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
165 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
166 MXC_CSPICTRL_SELCHAN(cs);
167 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
168 MXC_CSPICTRL_PREDIV(pre_div);
169 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
170 MXC_CSPICTRL_POSTDIV(post_div);
172 if (mode & SPI_CS_HIGH)
175 if (mode & SPI_CPOL) {
183 reg_config = reg_read(®s->cfg);
186 * Configuration register setup
187 * The MX51 supports different setup for each SS
189 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
190 (ss_pol << (cs + MXC_CSPICON_SSPOL));
191 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
192 (sclkpol << (cs + MXC_CSPICON_POL));
193 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
194 (sclkctl << (cs + MXC_CSPICON_CTL));
195 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
196 (sclkpha << (cs + MXC_CSPICON_PHA));
198 debug("reg_ctrl = 0x%x\n", reg_ctrl);
199 reg_write(®s->ctrl, reg_ctrl);
200 debug("reg_config = 0x%x\n", reg_config);
201 reg_write(®s->cfg, reg_config);
203 /* save config register and control register */
204 mxcs->ctrl_reg = reg_ctrl;
205 mxcs->cfg_reg = reg_config;
207 /* clear interrupt reg */
208 reg_write(®s->intr, 0);
209 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
215 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
216 const u8 *dout, u8 *din, unsigned long flags)
218 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
219 int nbytes = DIV_ROUND_UP(bitlen, 8);
221 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
225 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
226 __func__, bitlen, (u32)dout, (u32)din);
228 mxcs->ctrl_reg = (mxcs->ctrl_reg &
229 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
230 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
232 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
234 reg_write(®s->cfg, mxcs->cfg_reg);
237 /* Clear interrupt register */
238 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
241 * The SPI controller works only with words,
242 * check if less than a word is sent.
243 * Access to the FIFO is only 32 bit
247 cnt = (bitlen % 32) / 8;
249 for (i = 0; i < cnt; i++) {
250 data = (data << 8) | (*dout++ & 0xFF);
253 debug("Sending SPI 0x%x\n", data);
255 reg_write(®s->txdata, data);
264 /* Buffer is not 32-bit aligned */
265 if ((unsigned long)dout & 0x03) {
267 for (i = 0; i < 4; i++)
268 data = (data << 8) | (*dout++ & 0xFF);
271 data = cpu_to_be32(data);
275 debug("Sending SPI 0x%x\n", data);
276 reg_write(®s->txdata, data);
280 /* FIFO is written, now starts the transfer setting the XCH bit */
281 reg_write(®s->ctrl, mxcs->ctrl_reg |
282 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
285 status = reg_read(®s->stat);
286 /* Wait until the TC (Transfer completed) bit is set */
287 while ((status & MXC_CSPICTRL_TC) == 0) {
288 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
289 printf("spi_xchg_single: Timeout!\n");
292 status = reg_read(®s->stat);
295 /* Transfer completed, clear any pending request */
296 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
298 nbytes = DIV_ROUND_UP(bitlen, 8);
303 data = reg_read(®s->rxdata);
304 cnt = (bitlen % 32) / 8;
305 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
306 debug("SPI Rx unaligned: 0x%x\n", data);
308 memcpy(din, &data, cnt);
316 tmp = reg_read(®s->rxdata);
317 data = cpu_to_be32(tmp);
318 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
319 cnt = min(nbytes, sizeof(data));
321 memcpy(din, &data, cnt);
331 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
332 void *din, unsigned long flags)
334 int n_bytes = DIV_ROUND_UP(bitlen, 8);
338 u8 *p_outbuf = (u8 *)dout;
339 u8 *p_inbuf = (u8 *)din;
344 if (flags & SPI_XFER_BEGIN)
345 spi_cs_activate(slave);
347 while (n_bytes > 0) {
348 if (n_bytes < MAX_SPI_BYTES)
351 blk_size = MAX_SPI_BYTES;
353 n_bits = blk_size * 8;
355 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
360 p_outbuf += blk_size;
366 if (flags & SPI_XFER_END) {
367 spi_cs_deactivate(slave);
378 * Some SPI devices require active chip-select over multiple
379 * transactions, we achieve this using a GPIO. Still, the SPI
380 * controller has to be configured to use one of its own chipselects.
381 * To use this feature you have to implement board_spi_cs_gpio() to assign
382 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
383 * You must use some unused on this SPI controller cs between 0 and 3.
385 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
386 unsigned int bus, unsigned int cs)
390 mxcs->gpio = board_spi_cs_gpio(bus, cs);
391 if (mxcs->gpio == -1)
394 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
396 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
403 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
404 unsigned int max_hz, unsigned int mode)
406 struct mxc_spi_slave *mxcs;
409 if (bus >= ARRAY_SIZE(spi_bases))
412 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
414 puts("mxc_spi: SPI Slave not allocated !\n");
418 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
420 ret = setup_cs_gpio(mxcs, bus, cs);
426 mxcs->base = spi_bases[bus];
428 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
430 printf("mxc_spi: cannot setup SPI controller\n");
437 void spi_free_slave(struct spi_slave *slave)
439 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
444 int spi_claim_bus(struct spi_slave *slave)
446 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
447 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
449 reg_write(®s->rxdata, 1);
451 reg_write(®s->ctrl, mxcs->ctrl_reg);
452 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
453 reg_write(®s->intr, 0);
458 void spi_release_bus(struct spi_slave *slave)
460 /* TODO: Shut the controller down */