1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
12 #include <asm/global_data.h>
13 #include <dm/device_compat.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/mach-imx/spi.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 /* MX35 and older is CSPI */
26 #if defined(CONFIG_MX31)
39 #define MXC_CSPICTRL_EN BIT(0)
40 #define MXC_CSPICTRL_MODE BIT(1)
41 #define MXC_CSPICTRL_XCH BIT(2)
42 #define MXC_CSPICTRL_SMC BIT(3)
43 #define MXC_CSPICTRL_POL BIT(4)
44 #define MXC_CSPICTRL_PHA BIT(5)
45 #define MXC_CSPICTRL_SSCTL BIT(6)
46 #define MXC_CSPICTRL_SSPOL BIT(7)
47 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
48 #define MXC_CSPICTRL_RXOVF BIT(6)
49 #define MXC_CSPIPERIOD_32KHZ BIT(15)
50 #define MAX_SPI_BYTES 4
51 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
52 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
53 #define MXC_CSPICTRL_TC BIT(8)
54 #define MXC_CSPICTRL_MAXBITS 0x1f
56 #else /* MX51 and newer is ECSPI */
69 #define MXC_CSPICTRL_EN BIT(0)
70 #define MXC_CSPICTRL_MODE BIT(1)
71 #define MXC_CSPICTRL_XCH BIT(2)
72 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
73 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
74 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
75 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
76 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
77 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
78 #define MXC_CSPICTRL_MAXBITS 0xfff
79 #define MXC_CSPICTRL_TC BIT(7)
80 #define MXC_CSPICTRL_RXOVF BIT(6)
81 #define MXC_CSPIPERIOD_32KHZ BIT(15)
82 #define MAX_SPI_BYTES 32
84 /* Bit position inside CTRL register to be associated with SS */
85 #define MXC_CSPICTRL_CHAN 18
87 /* Bit position inside CON register to be associated with SS */
88 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
89 #define MXC_CSPICON_POL 4 /* SCLK polarity */
90 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
91 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
95 /* i.MX27 has a completely wrong register layout and register definitions in the
96 * datasheet, the correct one is in the Freescale's Linux driver */
98 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
99 "See linux mxc_spi driver from Freescale for details."
102 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
107 #define OUT MXC_GPIO_DIRECTION_OUT
109 #define reg_read readl
110 #define reg_write(a, v) writel(v, a)
112 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
113 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
116 #define MAX_CS_COUNT 4
118 struct mxc_spi_slave {
119 struct spi_slave slave;
122 #if defined(MXC_ECSPI)
130 struct gpio_desc cs_gpios[MAX_CS_COUNT];
134 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
136 return container_of(slave, struct mxc_spi_slave, slave);
139 static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
141 #if CONFIG_IS_ENABLED(DM_SPI)
142 struct udevice *dev = mxcs->dev;
143 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
145 u32 cs = slave_plat->cs;
147 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
150 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
153 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
157 static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
159 #if CONFIG_IS_ENABLED(DM_SPI)
160 struct udevice *dev = mxcs->dev;
161 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
163 u32 cs = slave_plat->cs;
165 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
168 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
171 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
175 u32 get_cspi_div(u32 div)
179 for (i = 0; i < 8; i++) {
187 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
189 unsigned int ctrl_reg;
192 unsigned int max_hz = mxcs->max_hz;
193 unsigned int mode = mxcs->mode;
195 clk_src = mxc_get_clock(MXC_CSPI_CLK);
197 div = DIV_ROUND_UP(clk_src, max_hz);
198 div = get_cspi_div(div);
200 debug("clk %d Hz, div %d, real clk %d Hz\n",
201 max_hz, div, clk_src / (4 << div));
203 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
204 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
205 MXC_CSPICTRL_DATARATE(div) |
210 ctrl_reg |= MXC_CSPICTRL_PHA;
212 ctrl_reg |= MXC_CSPICTRL_POL;
213 if (mode & SPI_CS_HIGH)
214 ctrl_reg |= MXC_CSPICTRL_SSPOL;
215 mxcs->ctrl_reg = ctrl_reg;
222 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
224 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
225 s32 reg_ctrl, reg_config;
226 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
227 u32 pre_div = 0, post_div = 0;
228 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
229 unsigned int max_hz = mxcs->max_hz;
230 unsigned int mode = mxcs->mode;
233 * Reset SPI and set all CSs to master mode, if toggling
234 * between slave and master mode we might see a glitch
237 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
238 reg_write(®s->ctrl, reg_ctrl);
239 reg_ctrl |= MXC_CSPICTRL_EN;
240 reg_write(®s->ctrl, reg_ctrl);
242 if (clk_src > max_hz) {
243 pre_div = (clk_src - 1) / max_hz;
244 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
245 post_div = fls(pre_div);
248 if (post_div >= 16) {
249 printf("Error: no divider for the freq: %d\n",
253 pre_div >>= post_div;
259 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
260 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
261 MXC_CSPICTRL_SELCHAN(cs);
262 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
263 MXC_CSPICTRL_PREDIV(pre_div);
264 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
265 MXC_CSPICTRL_POSTDIV(post_div);
267 if (mode & SPI_CS_HIGH)
270 if (mode & SPI_CPOL) {
278 reg_config = reg_read(®s->cfg);
281 * Configuration register setup
282 * The MX51 supports different setup for each SS
284 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
285 (ss_pol << (cs + MXC_CSPICON_SSPOL));
286 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
287 (sclkpol << (cs + MXC_CSPICON_POL));
288 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
289 (sclkctl << (cs + MXC_CSPICON_CTL));
290 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
291 (sclkpha << (cs + MXC_CSPICON_PHA));
293 debug("reg_ctrl = 0x%x\n", reg_ctrl);
294 reg_write(®s->ctrl, reg_ctrl);
295 debug("reg_config = 0x%x\n", reg_config);
296 reg_write(®s->cfg, reg_config);
298 /* save config register and control register */
299 mxcs->ctrl_reg = reg_ctrl;
300 mxcs->cfg_reg = reg_config;
302 /* clear interrupt reg */
303 reg_write(®s->intr, 0);
304 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
310 int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
311 const u8 *dout, u8 *din, unsigned long flags)
313 int nbytes = DIV_ROUND_UP(bitlen, 8);
315 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
319 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
320 __func__, bitlen, (ulong)dout, (ulong)din);
322 mxcs->ctrl_reg = (mxcs->ctrl_reg &
323 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
324 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
326 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
328 reg_write(®s->cfg, mxcs->cfg_reg);
331 /* Clear interrupt register */
332 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
335 * The SPI controller works only with words,
336 * check if less than a word is sent.
337 * Access to the FIFO is only 32 bit
341 cnt = (bitlen % 32) / 8;
343 for (i = 0; i < cnt; i++) {
344 data = (data << 8) | (*dout++ & 0xFF);
347 debug("Sending SPI 0x%x\n", data);
349 reg_write(®s->txdata, data);
358 /* Buffer is not 32-bit aligned */
359 if ((unsigned long)dout & 0x03) {
361 for (i = 0; i < 4; i++)
362 data = (data << 8) | (*dout++ & 0xFF);
365 data = cpu_to_be32(data);
369 debug("Sending SPI 0x%x\n", data);
370 reg_write(®s->txdata, data);
374 /* FIFO is written, now starts the transfer setting the XCH bit */
375 reg_write(®s->ctrl, mxcs->ctrl_reg |
376 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
379 status = reg_read(®s->stat);
380 /* Wait until the TC (Transfer completed) bit is set */
381 while ((status & MXC_CSPICTRL_TC) == 0) {
382 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
383 printf("spi_xchg_single: Timeout!\n");
386 status = reg_read(®s->stat);
389 /* Transfer completed, clear any pending request */
390 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
392 nbytes = DIV_ROUND_UP(bitlen, 8);
395 data = reg_read(®s->rxdata);
396 cnt = (bitlen % 32) / 8;
397 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
398 debug("SPI Rx unaligned: 0x%x\n", data);
400 memcpy(din, &data, cnt);
408 tmp = reg_read(®s->rxdata);
409 data = cpu_to_be32(tmp);
410 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
411 cnt = min_t(u32, nbytes, sizeof(data));
413 memcpy(din, &data, cnt);
423 static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
424 unsigned int bitlen, const void *dout,
425 void *din, unsigned long flags)
427 int n_bytes = DIV_ROUND_UP(bitlen, 8);
431 u8 *p_outbuf = (u8 *)dout;
432 u8 *p_inbuf = (u8 *)din;
437 if (flags & SPI_XFER_BEGIN)
438 mxc_spi_cs_activate(mxcs);
440 while (n_bytes > 0) {
441 if (n_bytes < MAX_SPI_BYTES)
444 blk_size = MAX_SPI_BYTES;
446 n_bits = blk_size * 8;
448 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
453 p_outbuf += blk_size;
459 if (flags & SPI_XFER_END) {
460 mxc_spi_cs_deactivate(mxcs);
466 static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
468 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
471 reg_write(®s->rxdata, 1);
473 ret = spi_cfg_mxc(mxcs, cs);
475 printf("mxc_spi: cannot setup SPI controller\n");
478 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
479 reg_write(®s->intr, 0);
484 #if !CONFIG_IS_ENABLED(DM_SPI)
485 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
486 void *din, unsigned long flags)
488 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
490 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
494 * Some SPI devices require active chip-select over multiple
495 * transactions, we achieve this using a GPIO. Still, the SPI
496 * controller has to be configured to use one of its own chipselects.
497 * To use this feature you have to implement board_spi_cs_gpio() to assign
498 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
499 * You must use some unused on this SPI controller cs between 0 and 3.
501 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
502 unsigned int bus, unsigned int cs)
506 mxcs->gpio = board_spi_cs_gpio(bus, cs);
507 if (mxcs->gpio == -1)
510 gpio_request(mxcs->gpio, "spi-cs");
511 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
513 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
520 static unsigned long spi_bases[] = {
521 MXC_SPI_BASE_ADDRESSES
524 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
525 unsigned int max_hz, unsigned int mode)
527 struct mxc_spi_slave *mxcs;
530 if (bus >= ARRAY_SIZE(spi_bases))
534 printf("Error: desired clock is 0\n");
538 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
540 puts("mxc_spi: SPI Slave not allocated !\n");
544 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
546 ret = setup_cs_gpio(mxcs, bus, cs);
552 mxcs->base = spi_bases[bus];
553 mxcs->max_hz = max_hz;
559 void spi_free_slave(struct spi_slave *slave)
561 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
566 int spi_claim_bus(struct spi_slave *slave)
568 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
570 return mxc_spi_claim_bus_internal(mxcs, slave->cs);
573 void spi_release_bus(struct spi_slave *slave)
575 /* TODO: Shut the controller down */
579 static int mxc_spi_probe(struct udevice *bus)
581 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
585 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
586 ARRAY_SIZE(mxcs->cs_gpios), 0);
588 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
592 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
593 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
596 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
597 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
599 dev_err(bus, "Setting cs %d error\n", i);
604 mxcs->base = dev_read_addr(bus);
605 if (mxcs->base == FDT_ADDR_T_NONE)
608 #if CONFIG_IS_ENABLED(CLK)
610 ret = clk_get_by_index(bus, 0, &clk);
616 mxcs->max_hz = clk_get_rate(&clk);
618 int node = dev_of_offset(bus);
619 const void *blob = gd->fdt_blob;
620 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
627 static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
628 const void *dout, void *din, unsigned long flags)
630 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
633 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
636 static int mxc_spi_claim_bus(struct udevice *dev)
638 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
639 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
643 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
646 static int mxc_spi_release_bus(struct udevice *dev)
651 static int mxc_spi_set_speed(struct udevice *bus, uint speed)
653 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
655 mxcs->max_hz = speed;
660 static int mxc_spi_set_mode(struct udevice *bus, uint mode)
662 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
665 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
670 static const struct dm_spi_ops mxc_spi_ops = {
671 .claim_bus = mxc_spi_claim_bus,
672 .release_bus = mxc_spi_release_bus,
673 .xfer = mxc_spi_xfer,
674 .set_speed = mxc_spi_set_speed,
675 .set_mode = mxc_spi_set_mode,
678 static const struct udevice_id mxc_spi_ids[] = {
679 { .compatible = "fsl,imx51-ecspi" },
683 U_BOOT_DRIVER(mxc_spi) = {
686 .of_match = mxc_spi_ids,
688 .plat_auto = sizeof(struct mxc_spi_slave),
689 .probe = mxc_spi_probe,