1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Marvell International Ltd.
5 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #define MVEBU_SPI_A3700_XFER_RDY BIT(1)
22 #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
23 #define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
24 #define MVEBU_SPI_A3700_CLK_PHA BIT(6)
25 #define MVEBU_SPI_A3700_CLK_POL BIT(7)
26 #define MVEBU_SPI_A3700_FIFO_EN BIT(17)
27 #define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
28 #define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f
33 u32 ctrl; /* 0x10600 */
34 u32 cfg; /* 0x10604 */
35 u32 dout; /* 0x10608 */
36 u32 din; /* 0x1060c */
39 struct mvebu_spi_platdata {
40 struct spi_reg *spireg;
44 static void spi_cs_activate(struct spi_reg *reg, int cs)
46 setbits_le32(®->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
49 static void spi_cs_deactivate(struct spi_reg *reg, int cs)
51 clrbits_le32(®->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
55 * spi_legacy_shift_byte() - triggers the real SPI transfer
56 * @bytelen: Indicate how many bytes to transfer.
57 * @dout: Buffer address of what to send.
58 * @din: Buffer address of where to receive.
60 * This function triggers the real SPI transfer in legacy mode. It
61 * will shift out char buffer from @dout, and shift in char buffer to
64 * This function assumes that only one byte is shifted at one time.
65 * However, it is not its responisbility to set the transfer type to
66 * one-byte. Also, it does not guarantee that it will work if transfer
67 * type becomes two-byte. See spi_set_legacy() for details.
69 * In legacy mode, simply write to the SPI_DOUT register will trigger
72 * If @dout == NULL, which means no actual data needs to be sent out,
73 * then the function will shift out 0x00 in order to shift in data.
74 * The XFER_RDY flag is checked every time before accessing SPI_DOUT
75 * and SPI_DIN register.
77 * The number of transfers to be triggerred is decided by @bytelen.
80 * -ETIMEDOUT - XFER_RDY flag timeout
82 static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
83 const void *dout, void *din)
89 /* Use 0x00 as dummy dout */
90 const u8 dummy_dout = 0x0;
91 u32 pending_dout = 0x0;
93 /* dout_8: pointer of current dout */
95 /* din_8: pointer of current din */
99 ret = wait_for_bit_le32(®->ctrl,
100 MVEBU_SPI_A3700_XFER_RDY,
106 pending_dout = (u32)*dout_8;
108 pending_dout = (u32)dummy_dout;
110 /* Trigger the xfer */
111 writel(pending_dout, ®->dout);
114 ret = wait_for_bit_le32(®->ctrl,
115 MVEBU_SPI_A3700_XFER_RDY,
120 /* Read what is transferred in */
121 *din_8 = (u8)readl(®->din);
124 /* Don't increment the current pointer if NULL */
136 static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
137 const void *dout, void *din, unsigned long flags)
139 struct udevice *bus = dev->parent;
140 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
141 struct spi_reg *reg = plat->spireg;
142 unsigned int bytelen;
145 bytelen = bitlen / 8;
148 debug("This is a duplex transfer.\n");
151 if (flags & SPI_XFER_BEGIN) {
152 debug("SPI: activate cs.\n");
153 spi_cs_activate(reg, spi_chip_select(dev));
156 /* Send and/or receive */
158 ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
164 if (flags & SPI_XFER_END) {
165 ret = wait_for_bit_le32(®->ctrl,
166 MVEBU_SPI_A3700_XFER_RDY,
171 debug("SPI: deactivate cs.\n");
172 spi_cs_deactivate(reg, spi_chip_select(dev));
178 static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
180 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
181 struct spi_reg *reg = plat->spireg;
184 data = readl(®->cfg);
186 prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
188 prescale = 0x10 + (prescale + 1) / 2;
189 prescale = min(prescale, 0x1fu);
191 data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
192 data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
194 writel(data, ®->cfg);
199 static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
201 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
202 struct spi_reg *reg = plat->spireg;
206 * 0: Serial interface clock is low when inactive
207 * 1: Serial interface clock is high when inactive
210 setbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_POL);
212 clrbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_POL);
214 setbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_PHA);
216 clrbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_PHA);
221 static int mvebu_spi_probe(struct udevice *bus)
223 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
224 struct spi_reg *reg = plat->spireg;
229 * Settings SPI controller to be working in legacy mode, which
230 * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
234 /* Flush read/write FIFO */
235 data = readl(®->cfg);
236 writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, ®->cfg);
237 ret = wait_for_bit_le32(®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
242 /* Disable FIFO mode */
243 data &= ~MVEBU_SPI_A3700_FIFO_EN;
245 /* Always shift 1 byte at a time */
246 data &= ~MVEBU_SPI_A3700_BYTE_LEN;
248 writel(data, ®->cfg);
253 static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
255 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
258 plat->spireg = dev_read_addr_ptr(bus);
260 ret = clk_get_by_index(bus, 0, &plat->clk);
262 dev_err(bus, "cannot get clock\n");
269 static int mvebu_spi_remove(struct udevice *bus)
271 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
273 clk_free(&plat->clk);
278 static const struct dm_spi_ops mvebu_spi_ops = {
279 .xfer = mvebu_spi_xfer,
280 .set_speed = mvebu_spi_set_speed,
281 .set_mode = mvebu_spi_set_mode,
283 * cs_info is not needed, since we require all chip selects to be
284 * in the device tree explicitly
288 static const struct udevice_id mvebu_spi_ids[] = {
289 { .compatible = "marvell,armada-3700-spi" },
293 U_BOOT_DRIVER(mvebu_spi) = {
296 .of_match = mvebu_spi_ids,
297 .ops = &mvebu_spi_ops,
298 .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
299 .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
300 .probe = mvebu_spi_probe,
301 .remove = mvebu_spi_remove,