1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
5 * Derived from the Linux driver version drivers/spi/spi-mt7621.c
6 * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
7 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
8 * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
17 #include <linux/bitops.h>
20 #define MT7621_RX_FIFO_LEN 32
21 #define MT7621_TX_FIFO_LEN 36
23 #define MT7621_SPI_TRANS 0x00
24 #define MT7621_SPI_TRANS_START BIT(8)
25 #define MT7621_SPI_TRANS_BUSY BIT(16)
26 #define TRANS_ADDR_SZ GENMASK(20, 19)
27 #define TRANS_ADDR_SZ_SHIFT 19
28 #define TRANS_MOSI_BCNT GENMASK(3, 0)
29 #define TRANS_MOSI_BCNT_SHIFT 0
31 #define MT7621_SPI_OPCODE 0x04
32 #define MT7621_SPI_DATA0 0x08
33 #define MT7621_SPI_DATA4 0x18
34 #define MT7621_SPI_MASTER 0x28
35 #define MT7621_SPI_MOREBUF 0x2c
36 #define MT7621_SPI_POLAR 0x38
38 #define MT7621_LSB_FIRST BIT(3)
39 #define MT7621_CPOL BIT(4)
40 #define MT7621_CPHA BIT(5)
42 #define MASTER_MORE_BUFMODE BIT(2)
43 #define MASTER_RS_CLK_SEL GENMASK(27, 16)
44 #define MASTER_RS_CLK_SEL_SHIFT 16
45 #define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
47 #define MOREBUF_CMD_CNT GENMASK(29, 24)
48 #define MOREBUF_CMD_CNT_SHIFT 24
49 #define MOREBUF_MISO_CNT GENMASK(20, 12)
50 #define MOREBUF_MISO_CNT_SHIFT 12
51 #define MOREBUF_MOSI_CNT GENMASK(8, 0)
52 #define MOREBUF_MOSI_CNT_SHIFT 0
56 unsigned int sys_freq;
59 static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
61 debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
64 setbits_le32(rs->base + MT7621_SPI_MASTER,
65 MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
66 iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR);
68 iowrite32(0, rs->base + MT7621_SPI_POLAR);
69 iowrite32((2 << TRANS_ADDR_SZ_SHIFT) |
70 (1 << TRANS_MOSI_BCNT_SHIFT),
71 rs->base + MT7621_SPI_TRANS);
72 clrbits_le32(rs->base + MT7621_SPI_MASTER,
73 MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
77 static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
79 struct mt7621_spi *rs = dev_get_priv(bus);
82 debug("%s: mode=0x%08x\n", __func__, mode);
83 reg = ioread32(rs->base + MT7621_SPI_MASTER);
85 reg &= ~MT7621_LSB_FIRST;
86 if (mode & SPI_LSB_FIRST)
87 reg |= MT7621_LSB_FIRST;
89 reg &= ~(MT7621_CPHA | MT7621_CPOL);
90 switch (mode & (SPI_CPOL | SPI_CPHA)) {
100 reg |= MT7621_CPOL | MT7621_CPHA;
103 iowrite32(reg, rs->base + MT7621_SPI_MASTER);
108 static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
110 struct mt7621_spi *rs = dev_get_priv(bus);
114 debug("%s: speed=%d\n", __func__, speed);
115 rate = DIV_ROUND_UP(rs->sys_freq, speed);
116 debug("rate:%u\n", rate);
124 reg = ioread32(rs->base + MT7621_SPI_MASTER);
125 reg &= ~MASTER_RS_CLK_SEL;
126 reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
127 iowrite32(reg, rs->base + MT7621_SPI_MASTER);
132 static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
136 ret = wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
137 MT7621_SPI_TRANS_BUSY, 0, 10, 0);
139 pr_err("Timeout in %s!\n", __func__);
144 static int mt7621_spi_read(struct mt7621_spi *rs, u8 *buf, size_t len)
151 rx_len = min_t(size_t, len, MT7621_RX_FIFO_LEN);
153 iowrite32((rx_len * 8) << MOREBUF_MISO_CNT_SHIFT,
154 rs->base + MT7621_SPI_MOREBUF);
155 iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
157 ret = mt7621_spi_wait_till_ready(rs);
161 for (i = 0; i < rx_len; i++) {
163 val = ioread32(rs->base + MT7621_SPI_DATA0 + i);
174 static int mt7621_spi_write(struct mt7621_spi *rs, const u8 *buf, size_t len)
176 size_t tx_len, opcode_len, dido_len;
181 tx_len = min_t(size_t, len, MT7621_TX_FIFO_LEN);
183 opcode_len = min_t(size_t, tx_len, 4);
184 dido_len = tx_len - opcode_len;
187 for (i = 0; i < opcode_len; i++) {
192 iowrite32(val, rs->base + MT7621_SPI_OPCODE);
195 for (i = 0; i < dido_len; i++) {
196 val |= (*buf++) << ((i % 4) * 8);
198 if ((i % 4 == 3) || (i == dido_len - 1)) {
199 iowrite32(val, rs->base + MT7621_SPI_DATA0 +
205 iowrite32(((opcode_len * 8) << MOREBUF_CMD_CNT_SHIFT) |
206 ((dido_len * 8) << MOREBUF_MOSI_CNT_SHIFT),
207 rs->base + MT7621_SPI_MOREBUF);
208 iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
210 ret = mt7621_spi_wait_till_ready(rs);
220 static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
221 const void *dout, void *din, unsigned long flags)
223 struct udevice *bus = dev->parent;
224 struct mt7621_spi *rs = dev_get_priv(bus);
225 int total_size = bitlen >> 3;
228 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
232 * This driver only supports half-duplex, so complain and bail out
233 * upon full-duplex messages
236 printf("Only half-duplex SPI transfer supported\n");
240 mt7621_spi_wait_till_ready(rs);
243 * Set CS active upon start of SPI message. This message can
244 * be split upon multiple calls to this xfer function
246 if (flags & SPI_XFER_BEGIN)
247 mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
250 ret = mt7621_spi_read(rs, din, total_size);
252 ret = mt7621_spi_write(rs, dout, total_size);
254 if (flags & SPI_XFER_END)
255 mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
260 static int mt7621_spi_probe(struct udevice *dev)
262 struct mt7621_spi *rs = dev_get_priv(dev);
266 rs->base = dev_remap_addr(dev);
270 ret = clk_get_by_index(dev, 0, &clk);
272 printf("Please provide a clock!\n");
278 rs->sys_freq = clk_get_rate(&clk);
280 printf("Please provide a valid clock!\n");
287 static const struct dm_spi_ops mt7621_spi_ops = {
288 .set_mode = mt7621_spi_set_mode,
289 .set_speed = mt7621_spi_set_speed,
290 .xfer = mt7621_spi_xfer,
292 * cs_info is not needed, since we require all chip selects to be
293 * in the device tree explicitly
297 static const struct udevice_id mt7621_spi_ids[] = {
298 { .compatible = "ralink,mt7621-spi" },
302 U_BOOT_DRIVER(mt7621_spi) = {
303 .name = "mt7621_spi",
305 .of_match = mt7621_spi_ids,
306 .ops = &mt7621_spi_ops,
307 .priv_auto = sizeof(struct mt7621_spi),
308 .probe = mt7621_spi_probe,