1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs spi driver
5 * Copyright (c) 2018 Microsemi Corporation
16 #include <linux/delay.h>
20 u32 deactivate_delay_us;
21 bool cs_active; /* State flag as to whether CS is asserted */
23 u32 svalue; /* Value to start transfer with */
24 u32 clk1; /* Clock value start */
25 u32 clk2; /* Clock value 2nd phase */
28 /* Delay 24 instructions for this particular application */
29 #define hold_time_delay() mscc_vcoreiii_nop_delay(3)
31 static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
33 if (!priv->cs_active) {
34 int cpha = mode & SPI_CPHA;
40 /* Initial clock starts SCK=1 */
41 priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
44 /* Initial clock starts SCK=0 */
46 priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
49 /* Enable bitbang, SCK_OE, SDO_OE */
50 priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
51 ICPU_SW_MODE_SW_SPI_SCK_OE | /* SCK_OE */
52 ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
57 ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
58 ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
63 priv->svalue |= cs_value;
65 /* Enable the CS in HW, Initial clock value */
66 writel(priv->svalue | priv->clk2, priv->regs);
68 priv->cs_active = true;
69 debug("Activated CS%d\n", priv->cs_num);
75 static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
77 if (priv->cs_active) {
78 /* Keep driving the CLK to its current value while
79 * actively deselecting CS.
81 u32 value = readl(priv->regs);
83 value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
84 writel(value, priv->regs);
87 /* Stop driving the clock, but keep CS with nCS == 1 */
88 value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
89 writel(value, priv->regs);
91 /* Deselect hold time delay */
96 writel(0, priv->regs);
98 priv->cs_active = false;
99 debug("Deactivated CS%d\n", priv->cs_num);
105 int mscc_bb_spi_claim_bus(struct udevice *dev)
110 int mscc_bb_spi_release_bus(struct udevice *dev)
115 int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
116 const void *dout, void *din, unsigned long flags)
118 struct udevice *bus = dev_get_parent(dev);
119 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
120 struct mscc_bb_priv *priv = dev_get_priv(bus);
122 const u8 *txd = dout;
125 debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
126 dev->parent->name, dev->name, plat->cs, plat->mode, dout,
129 if (flags & SPI_XFER_BEGIN)
130 mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
133 for (i = 0; i < count; i++) {
134 u32 rx = 0, mask = 0x80, value;
137 /* Initial condition: CLK is low. */
138 value = priv->svalue;
139 if (txd && txd[i] & mask)
140 value |= ICPU_SW_MODE_SW_SPI_SDO;
142 /* Drive data while taking CLK low. The device
143 * we're accessing will sample on the
144 * following rising edge and will output data
145 * on this edge for us to be sampled at the
148 writel(value | priv->clk1, priv->regs);
150 /* Wait for t_setup. All devices do have a
151 * setup-time, so we always insert some delay
152 * here. Some devices have a very long
153 * setup-time, which can be adjusted by the
154 * user through vcoreiii_device->delay.
158 /* Drive the clock high. */
159 writel(value | priv->clk2, priv->regs);
161 /* Wait for t_hold. See comment about t_setup
166 /* We sample as close to the next falling edge
169 value = readl(priv->regs);
170 if (value & ICPU_SW_MODE_SW_SPI_SDI)
175 debug("Read 0x%02x\n", rx);
178 debug("spi_xfer: byte %d/%d\n", i + 1, count);
181 debug("spi_xfer: done\n");
183 if (flags & SPI_XFER_END)
184 mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
189 int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
191 /* Accept any speed */
195 int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
200 static const struct dm_spi_ops mscc_bb_ops = {
201 .claim_bus = mscc_bb_spi_claim_bus,
202 .release_bus = mscc_bb_spi_release_bus,
203 .xfer = mscc_bb_spi_xfer,
204 .set_speed = mscc_bb_spi_set_speed,
205 .set_mode = mscc_bb_spi_set_mode,
208 static const struct udevice_id mscc_bb_ids[] = {
209 { .compatible = "mscc,luton-bb-spi" },
213 static int mscc_bb_spi_probe(struct udevice *bus)
215 struct mscc_bb_priv *priv = dev_get_priv(bus);
217 debug("%s: loaded, priv %p\n", __func__, priv);
219 priv->regs = (void __iomem *)dev_read_addr(bus);
221 priv->deactivate_delay_us =
222 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
224 priv->cs_active = false;
229 U_BOOT_DRIVER(mscc_bb) = {
232 .of_match = mscc_bb_ids,
234 .priv_auto_alloc_size = sizeof(struct mscc_bb_priv),
235 .probe = mscc_bb_spi_probe,