1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
4 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
11 #include <asm/mpc8xxx_spi.h>
13 #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
14 #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
16 #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
17 #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
18 #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
19 #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
21 #define SPI_TIMEOUT 1000
23 struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
25 struct spi_slave *slave;
27 if (!spi_cs_is_valid(bus, cs))
30 slave = spi_alloc_slave_base(bus, cs);
35 * TODO: Some of the code in spi_init() should probably move
36 * here, or into spi_claim_bus() below.
42 void spi_free_slave(struct spi_slave *slave)
49 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
52 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
55 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
56 spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
58 spi->event = 0xffffffff; /* Clear all SPI events */
59 spi->mask = 0x00000000; /* Mask all SPI interrupts */
60 spi->com = 0; /* LST bit doesn't do anything, so disregard */
63 int spi_claim_bus(struct spi_slave *slave)
68 void spi_release_bus(struct spi_slave *slave)
72 int spi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din,
75 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
76 uint tmpdout, tmpdin, event;
77 int numBlks = DIV_ROUND_UP(bitlen, 32);
81 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
82 slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
84 if (flags & SPI_XFER_BEGIN)
85 spi_cs_activate(slave);
87 spi->event = 0xffffffff; /* Clear all SPI events */
89 /* handle data in 32-bit chunks */
92 charSize = (bitlen >= 32 ? 32 : bitlen);
94 /* Shift data so it's msb-justified */
95 tmpdout = *(u32 *) dout >> (32 - charSize);
97 /* The LEN field of the SPMODE register is set as follows:
101 * 4 < len <= 16 len - 1
105 spi->mode &= ~SPI_MODE_EN;
109 spi->mode = (spi->mode & 0xff0fffff) |
112 spi->mode = (spi->mode & 0xff0fffff) |
113 ((bitlen - 1) << 20);
115 spi->mode = (spi->mode & 0xff0fffff);
116 /* Set up the next iteration if sending > 32 bits */
121 spi->mode |= SPI_MODE_EN;
123 spi->tx = tmpdout; /* Write the data out */
124 debug("*** spi_xfer: ... %08x written\n", tmpdout);
127 * Wait for SPI transmit to get out
128 * or time out (1 second = 1000 ms)
129 * The NE event must be read and cleared first
131 for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
133 if (event & SPI_EV_NE) {
135 spi->event |= SPI_EV_NE;
138 *(u32 *) din = (tmpdin << (32 - charSize));
139 if (charSize == 32) {
140 /* Advance output buffer by 32 bits */
145 * Only bail when we've had both NE and NF events.
146 * This will cause timeouts on RO devices, so maybe
147 * in the future put an arbitrary delay after writing
148 * the device. Arbitrary delays suck, though...
150 if (isRead && (event & SPI_EV_NF))
153 if (tm >= SPI_TIMEOUT)
154 puts("*** spi_xfer: Time out during SPI transfer");
156 debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
159 if (flags & SPI_XFER_END)
160 spi_cs_deactivate(slave);