1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
4 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
14 #include <asm/mpc8xxx_spi.h>
15 #include <asm-generic/gpio.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
21 SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
22 SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
26 SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
27 SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
28 SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
29 SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
30 SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
31 SPI_MODE_MS = BIT(31 - 6), /* Always master */
32 SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
34 SPI_MODE_LEN_MASK = 0xf00000,
35 SPI_MODE_LEN_SHIFT = 20,
36 SPI_MODE_PM_SHIFT = 16,
37 SPI_MODE_PM_MASK = 0xf0000,
39 SPI_COM_LST = BIT(31 - 9),
44 struct gpio_desc gpios[16];
49 #define SPI_TIMEOUT 1000
51 static int mpc8xxx_spi_of_to_plat(struct udevice *dev)
53 struct mpc8xxx_priv *priv = dev_get_priv(dev);
57 priv->spi = (spi8xxx_t *)dev_read_addr(dev);
59 ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
60 ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
66 ret = clk_get_by_index(dev, 0, &clk);
68 dev_err(dev, "%s: clock not defined\n", __func__);
72 priv->clk_rate = clk_get_rate(&clk);
73 if (!priv->clk_rate) {
74 dev_err(dev, "%s: failed to get clock rate\n", __func__);
81 static int mpc8xxx_spi_probe(struct udevice *dev)
83 struct mpc8xxx_priv *priv = dev_get_priv(dev);
84 spi8xxx_t *spi = priv->spi;
87 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
90 out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
92 /* set len to 8 bits */
93 setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT);
95 setbits_be32(&spi->mode, SPI_MODE_EN);
97 /* Clear all SPI events */
98 setbits_be32(&priv->spi->event, 0xffffffff);
99 /* Mask all SPI interrupts */
100 clrbits_be32(&priv->spi->mask, 0xffffffff);
101 /* LST bit doesn't do anything, so disregard */
102 out_be32(&priv->spi->com, 0);
107 static void mpc8xxx_spi_cs_activate(struct udevice *dev)
109 struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
110 struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
112 dm_gpio_set_value(&priv->gpios[plat->cs], 1);
115 static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
117 struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
118 struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
120 dm_gpio_set_value(&priv->gpios[plat->cs], 0);
123 static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
124 const void *dout, void *din, ulong flags)
126 struct udevice *bus = dev->parent;
127 struct mpc8xxx_priv *priv = dev_get_priv(bus);
128 spi8xxx_t *spi = priv->spi;
129 struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
130 u32 tmpdin = 0, tmpdout = 0, n;
131 const u8 *cout = dout;
134 debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
135 bus->name, plat->cs, (uint)dout, (uint)din, bitlen);
136 if (plat->cs >= priv->cs_count) {
137 dev_err(dev, "chip select index %d too large (cs_count=%d)\n",
138 plat->cs, priv->cs_count);
142 printf("*** spi_xfer: bitlen must be multiple of 8\n");
146 if (flags & SPI_XFER_BEGIN)
147 mpc8xxx_spi_cs_activate(dev);
149 /* Clear all SPI events */
150 setbits_be32(&spi->event, 0xffffffff);
153 /* Handle data in 8-bit chunks */
160 /* Write the data out */
161 out_be32(&spi->tx, tmpdout);
163 debug("*** %s: ... %08x written\n", __func__, tmpdout);
166 * Wait for SPI transmit to get out
167 * or time out (1 second = 1000 ms)
168 * The NE event must be read and cleared first
170 start = get_timer(0);
172 u32 event = in_be32(&spi->event);
173 bool have_ne = event & SPI_EV_NE;
174 bool have_nf = event & SPI_EV_NF;
179 tmpdin = in_be32(&spi->rx);
180 setbits_be32(&spi->event, SPI_EV_NE);
186 * Only bail when we've had both NE and NF events.
187 * This will cause timeouts on RO devices, so maybe
188 * in the future put an arbitrary delay after writing
189 * the device. Arbitrary delays suck, though...
195 } while (get_timer(start) < SPI_TIMEOUT);
197 if (get_timer(start) >= SPI_TIMEOUT) {
198 debug("*** %s: Time out during SPI transfer\n",
203 debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
206 if (flags & SPI_XFER_END)
207 mpc8xxx_spi_cs_deactivate(dev);
212 static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
214 struct mpc8xxx_priv *priv = dev_get_priv(dev);
215 spi8xxx_t *spi = priv->spi;
216 u32 bits, mask, div16, pm;
220 clk = priv->clk_rate;
221 if (clk / 64 > speed) {
222 div16 = SPI_MODE_DIV16;
227 pm = (clk - 1)/(4*speed) + 1;
229 dev_err(dev, "requested speed %u too small\n", speed);
234 bits = div16 | (pm << SPI_MODE_PM_SHIFT);
235 mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK;
236 mode = in_be32(&spi->mode);
237 if ((mode & mask) != bits) {
238 /* Must clear mode[EN] while changing speed. */
239 mode &= ~(mask | SPI_MODE_EN);
240 out_be32(&spi->mode, mode);
242 out_be32(&spi->mode, mode);
244 out_be32(&spi->mode, mode);
247 debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n",
248 speed, priv->clk_rate, div16 ? "16*" : "", pm + 1,
254 static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
256 /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
257 * SPI_CPOL (for clock polarity) should work
262 static const struct dm_spi_ops mpc8xxx_spi_ops = {
263 .xfer = mpc8xxx_spi_xfer,
264 .set_speed = mpc8xxx_spi_set_speed,
265 .set_mode = mpc8xxx_spi_set_mode,
267 * cs_info is not needed, since we require all chip selects to be
268 * in the device tree explicitly
272 static const struct udevice_id mpc8xxx_spi_ids[] = {
273 { .compatible = "fsl,spi" },
277 U_BOOT_DRIVER(mpc8xxx_spi) = {
278 .name = "mpc8xxx_spi",
280 .of_match = mpc8xxx_spi_ids,
281 .ops = &mpc8xxx_spi_ops,
282 .of_to_plat = mpc8xxx_spi_of_to_plat,
283 .probe = mpc8xxx_spi_probe,
284 .priv_auto = sizeof(struct mpc8xxx_priv),