1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
4 * <nboppuri@trinetcommunication.com>,
5 * <pmpatel@trinetcommunication.com>
6 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
7 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
11 * MPC8xx CPM SPI interface.
13 * Parts of this code are probably not portable and/or specific to
14 * the board which I used for the tests. Please send fixes/complaints
23 #include <linux/delay.h>
25 #include <asm/cpm_8xx.h>
29 #define CPM_SPI_BASE_RX CPM_SPI_BASE
30 #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
32 #define MAX_BUFFER 0x104
36 struct gpio_desc gpios[16];
40 static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
45 static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed)
50 static int mpc8xx_spi_probe(struct udevice *dev)
52 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
53 cpm8xx_t __iomem *cp = &immr->im_cpm;
54 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
55 cbd_t __iomem *tbdf, *rbdf;
57 /* Disable relocation */
58 out_be16(&spi->spi_rpbase, 0x1d80);
61 /* Initialize the parameter ram.
62 * We need to make sure many things are initialized to zero
64 out_be32(&spi->spi_rstate, 0);
65 out_be32(&spi->spi_rdp, 0);
66 out_be16(&spi->spi_rbptr, 0);
67 out_be16(&spi->spi_rbc, 0);
68 out_be32(&spi->spi_rxtmp, 0);
69 out_be32(&spi->spi_tstate, 0);
70 out_be32(&spi->spi_tdp, 0);
71 out_be16(&spi->spi_tbptr, 0);
72 out_be16(&spi->spi_tbc, 0);
73 out_be32(&spi->spi_txtmp, 0);
76 /* Set up the SPI parameters in the parameter ram */
77 out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
78 out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
80 /***********IMPORTANT******************/
83 * Setting transmit and receive buffer descriptor pointers
84 * initially to rbase and tbase. Only the microcode patches
85 * documentation talks about initializing this pointer. This
86 * is missing from the sample I2C driver. If you dont
87 * initialize these pointers, the kernel hangs.
89 out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
90 out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
93 /* Init SPI Tx + Rx Parameters */
94 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
97 out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
99 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
103 /* Set SDMA configuration register */
104 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
107 /* Set to big endian. */
108 out_8(&spi->spi_tfcr, SMC_EB);
109 out_8(&spi->spi_rfcr, SMC_EB);
112 /* Set maximum receive size. */
113 out_be16(&spi->spi_mrblr, MAX_BUFFER);
116 /* tx and rx buffer descriptors */
117 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
118 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
120 clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
121 clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
124 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
125 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
130 static void mpc8xx_spi_cs_activate(struct udevice *dev)
132 struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
133 struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
135 dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
138 static void mpc8xx_spi_cs_deactivate(struct udevice *dev)
140 struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
141 struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
143 dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
146 static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
147 const void *dout, void *din, unsigned long flags)
149 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
150 cpm8xx_t __iomem *cp = &immr->im_cpm;
151 cbd_t __iomem *tbdf, *rbdf;
153 size_t count = (bitlen + 7) / 8;
155 if (count > MAX_BUFFER)
158 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
159 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
161 /* Set CS for device */
162 if (flags & SPI_XFER_BEGIN)
163 mpc8xx_spi_cs_activate(dev);
165 /* Setting tx bd status and data length */
166 out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
167 out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
168 out_be16(&tbdf->cbd_datlen, count);
170 /* Setting rx bd status and data length */
171 out_be32(&rbdf->cbd_bufaddr, (ulong)din);
172 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
173 out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
175 clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
176 SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
177 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
178 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
180 /* start spi transfer */
181 setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
183 /* --------------------------------
184 * Wait for SPI transmit to get out
185 * or time out (1 second = 1000 ms)
186 * -------------------------------- */
187 for (tm = 0; tm < 1000; ++tm) {
188 if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
191 if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
197 printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
199 /* Clear CS for device */
200 if (flags & SPI_XFER_END)
201 mpc8xx_spi_cs_deactivate(dev);
206 static int mpc8xx_spi_ofdata_to_platdata(struct udevice *dev)
208 struct mpc8xx_priv *priv = dev_get_priv(dev);
211 ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
212 ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT);
220 static const struct dm_spi_ops mpc8xx_spi_ops = {
221 .xfer = mpc8xx_spi_xfer,
222 .set_speed = mpc8xx_spi_set_speed,
223 .set_mode = mpc8xx_spi_set_mode,
226 static const struct udevice_id mpc8xx_spi_ids[] = {
227 { .compatible = "fsl,mpc8xx-spi" },
231 U_BOOT_DRIVER(mpc8xx_spi) = {
232 .name = "mpc8xx_spi",
234 .of_match = mpc8xx_spi_ids,
235 .of_to_plat = mpc8xx_spi_ofdata_to_platdata,
236 .ops = &mpc8xx_spi_ops,
237 .probe = mpc8xx_spi_probe,
238 .priv_auto = sizeof(struct mpc8xx_priv),