1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Derived from drivers/spi/mpc8xxx_spi.c
15 #include <asm/arch/soc.h>
16 #ifdef CONFIG_KIRKWOOD
17 #include <asm/arch/mpp.h>
19 #include <asm/arch-mvebu/spi.h>
21 static void _spi_cs_activate(struct kwspi_registers *reg)
23 setbits_le32(®->ctrl, KWSPI_CSN_ACT);
26 static void _spi_cs_deactivate(struct kwspi_registers *reg)
28 clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
31 static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
32 const void *dout, void *din, unsigned long flags)
34 unsigned int tmpdout, tmpdin;
37 debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
39 if (flags & SPI_XFER_BEGIN)
40 _spi_cs_activate(reg);
43 * handle data in 8-bit chunks
44 * TBD: 2byte xfer mode to be enabled
46 clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
49 debug("loopstart bitlen %d\n", bitlen);
52 /* Shift data so it's msb-justified */
54 tmpdout = *(u32 *)dout & 0xff;
56 clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
57 writel(tmpdout, ®->dout); /* Write the data out */
58 debug("*** spi_xfer: ... %08x written, bitlen %d\n",
62 * Wait for SPI transmit to get out
63 * or time out (1 second = 1000 ms)
64 * The NE event must be read and cleared first
66 for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
67 if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
69 tmpdin = readl(®->din);
70 debug("spi_xfer: din %p..%08x read\n",
74 *((u8 *)din) = (u8)tmpdin;
84 if (tm >= KWSPI_TIMEOUT)
85 printf("*** spi_xfer: Time out during SPI transfer\n");
87 debug("loopend bitlen %d\n", bitlen);
90 if (flags & SPI_XFER_END)
91 _spi_cs_deactivate(reg);
98 static struct kwspi_registers *spireg =
99 (struct kwspi_registers *)MVEBU_SPI_BASE;
101 #ifdef CONFIG_KIRKWOOD
102 static u32 cs_spi_mpp_back[2];
105 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
106 unsigned int max_hz, unsigned int mode)
108 struct spi_slave *slave;
110 #ifdef CONFIG_KIRKWOOD
111 static const u32 kwspi_mpp_config[2][2] = {
112 { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
113 { MPP7_SPI_SCn, 0 } /* if cs != 0 */
117 if (!spi_cs_is_valid(bus, cs))
120 slave = spi_alloc_slave_base(bus, cs);
124 writel(KWSPI_SMEMRDY, &spireg->ctrl);
126 /* calculate spi clock prescaller using max_hz */
127 data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
128 data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
129 data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
131 /* program spi clock prescaller using max_hz */
132 writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
133 debug("data = 0x%08x\n", data);
135 writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
136 writel(KWSPI_IRQMASK, &spireg->irq_mask);
138 #ifdef CONFIG_KIRKWOOD
139 /* program mpp registers to select SPI_CSn */
140 kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
146 void spi_free_slave(struct spi_slave *slave)
148 #ifdef CONFIG_KIRKWOOD
149 kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
154 __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
159 int spi_claim_bus(struct spi_slave *slave)
161 return board_spi_claim_bus(slave);
164 __attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
168 void spi_release_bus(struct spi_slave *slave)
170 board_spi_release_bus(slave);
173 #ifndef CONFIG_SPI_CS_IS_VALID
175 * you can define this function board specific
176 * define above CONFIG in board specific config file and
177 * provide the function in board specific src file
179 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
181 return bus == 0 && (cs == 0 || cs == 1);
189 void spi_cs_activate(struct spi_slave *slave)
191 _spi_cs_activate(spireg);
194 void spi_cs_deactivate(struct spi_slave *slave)
196 _spi_cs_deactivate(spireg);
199 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
200 const void *dout, void *din, unsigned long flags)
202 return _spi_xfer(spireg, bitlen, dout, din, flags);
207 /* Here now the DM part */
209 struct mvebu_spi_dev {
210 bool is_errata_50mhz_ac;
213 struct mvebu_spi_platdata {
214 struct kwspi_registers *spireg;
215 bool is_errata_50mhz_ac;
218 struct mvebu_spi_priv {
219 struct kwspi_registers *spireg;
222 static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
224 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
225 struct kwspi_registers *reg = plat->spireg;
228 /* calculate spi clock prescaller using max_hz */
229 data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
230 data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
231 data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
233 /* program spi clock prescaler using max_hz */
234 writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
235 debug("data = 0x%08x\n", data);
240 static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
242 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
243 struct kwspi_registers *reg = plat->spireg;
247 * Erratum description: (Erratum NO. FE-9144572) The device
248 * SPI interface supports frequencies of up to 50 MHz.
249 * However, due to this erratum, when the device core clock is
250 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
251 * clock and CPOL=CPHA=1 there might occur data corruption on
252 * reads from the SPI device.
253 * Erratum Workaround:
254 * Work in one of the following configurations:
255 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
257 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
258 * Register" before setting the interface.
260 data = readl(®->timing1);
261 data &= ~KW_SPI_TMISO_SAMPLE_MASK;
263 if (CONFIG_SYS_TCLK == 250000000 &&
266 data |= KW_SPI_TMISO_SAMPLE_2;
268 data |= KW_SPI_TMISO_SAMPLE_1;
270 writel(data, ®->timing1);
273 static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
275 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
276 struct kwspi_registers *reg = plat->spireg;
277 u32 data = readl(®->cfg);
279 data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
285 if (mode & SPI_LSB_FIRST)
286 data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
288 writel(data, ®->cfg);
290 if (plat->is_errata_50mhz_ac)
291 mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
296 static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
297 const void *dout, void *din, unsigned long flags)
299 struct udevice *bus = dev->parent;
300 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
302 return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
305 __attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
310 static int mvebu_spi_claim_bus(struct udevice *dev)
312 struct udevice *bus = dev->parent;
313 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
315 /* Configure the chip-select in the CTRL register */
316 clrsetbits_le32(&plat->spireg->ctrl,
317 KWSPI_CS_MASK << KWSPI_CS_SHIFT,
318 spi_chip_select(dev) << KWSPI_CS_SHIFT);
320 return mvebu_board_spi_claim_bus(dev);
323 __attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
328 static int mvebu_spi_release_bus(struct udevice *dev)
330 return mvebu_board_spi_release_bus(dev);
333 static int mvebu_spi_probe(struct udevice *bus)
335 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
336 struct kwspi_registers *reg = plat->spireg;
338 writel(KWSPI_SMEMRDY, ®->ctrl);
339 writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
340 writel(KWSPI_IRQMASK, ®->irq_mask);
345 static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
347 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
348 const struct mvebu_spi_dev *drvdata =
349 (struct mvebu_spi_dev *)dev_get_driver_data(bus);
351 plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
352 plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
357 static const struct dm_spi_ops mvebu_spi_ops = {
358 .claim_bus = mvebu_spi_claim_bus,
359 .release_bus = mvebu_spi_release_bus,
360 .xfer = mvebu_spi_xfer,
361 .set_speed = mvebu_spi_set_speed,
362 .set_mode = mvebu_spi_set_mode,
364 * cs_info is not needed, since we require all chip selects to be
365 * in the device tree explicitly
369 static const struct mvebu_spi_dev armada_spi_dev_data = {
370 .is_errata_50mhz_ac = false,
373 static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
374 .is_errata_50mhz_ac = false,
377 static const struct mvebu_spi_dev armada_375_spi_dev_data = {
378 .is_errata_50mhz_ac = false,
381 static const struct mvebu_spi_dev armada_380_spi_dev_data = {
382 .is_errata_50mhz_ac = true,
385 static const struct udevice_id mvebu_spi_ids[] = {
387 .compatible = "marvell,orion-spi",
388 .data = (ulong)&armada_spi_dev_data,
391 .compatible = "marvell,armada-375-spi",
392 .data = (ulong)&armada_375_spi_dev_data
395 .compatible = "marvell,armada-380-spi",
396 .data = (ulong)&armada_380_spi_dev_data
399 .compatible = "marvell,armada-xp-spi",
400 .data = (ulong)&armada_xp_spi_dev_data
405 U_BOOT_DRIVER(mvebu_spi) = {
408 .of_match = mvebu_spi_ids,
409 .ops = &mvebu_spi_ops,
410 .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
411 .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
412 .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
413 .probe = mvebu_spi_probe,