1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Derived from drivers/spi/mpc8xxx_spi.c
16 #include <asm/arch/soc.h>
17 #ifdef CONFIG_ARCH_KIRKWOOD
18 #include <asm/arch/mpp.h>
20 #include <asm/arch-mvebu/spi.h>
22 static void _spi_cs_activate(struct kwspi_registers *reg)
24 setbits_le32(®->ctrl, KWSPI_CSN_ACT);
27 static void _spi_cs_deactivate(struct kwspi_registers *reg)
29 clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
32 static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
33 const void *dout, void *din, unsigned long flags)
35 unsigned int tmpdout, tmpdin;
38 debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
40 if (flags & SPI_XFER_BEGIN)
41 _spi_cs_activate(reg);
44 * handle data in 8-bit chunks
45 * TBD: 2byte xfer mode to be enabled
47 clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
50 debug("loopstart bitlen %d\n", bitlen);
53 /* Shift data so it's msb-justified */
55 tmpdout = *(u32 *)dout & 0xff;
57 clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
58 writel(tmpdout, ®->dout); /* Write the data out */
59 debug("*** spi_xfer: ... %08x written, bitlen %d\n",
63 * Wait for SPI transmit to get out
64 * or time out (1 second = 1000 ms)
65 * The NE event must be read and cleared first
67 for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
68 if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
70 tmpdin = readl(®->din);
71 debug("spi_xfer: din %p..%08x read\n",
75 *((u8 *)din) = (u8)tmpdin;
85 if (tm >= KWSPI_TIMEOUT)
86 printf("*** spi_xfer: Time out during SPI transfer\n");
88 debug("loopend bitlen %d\n", bitlen);
91 if (flags & SPI_XFER_END)
92 _spi_cs_deactivate(reg);
97 #if !CONFIG_IS_ENABLED(DM_SPI)
99 static struct kwspi_registers *spireg =
100 (struct kwspi_registers *)MVEBU_SPI_BASE;
102 #ifdef CONFIG_ARCH_KIRKWOOD
103 static u32 cs_spi_mpp_back[2];
106 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
107 unsigned int max_hz, unsigned int mode)
109 struct spi_slave *slave;
111 #ifdef CONFIG_ARCH_KIRKWOOD
112 static const u32 kwspi_mpp_config[2][2] = {
113 { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
114 { MPP7_SPI_SCn, 0 } /* if cs != 0 */
118 if (!spi_cs_is_valid(bus, cs))
121 slave = spi_alloc_slave_base(bus, cs);
125 writel(KWSPI_SMEMRDY, &spireg->ctrl);
127 /* calculate spi clock prescaller using max_hz */
128 data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
129 data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
130 data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
132 /* program spi clock prescaller using max_hz */
133 writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
134 debug("data = 0x%08x\n", data);
136 writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
137 writel(KWSPI_IRQMASK, &spireg->irq_mask);
139 #ifdef CONFIG_ARCH_KIRKWOOD
140 /* program mpp registers to select SPI_CSn */
141 kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
147 void spi_free_slave(struct spi_slave *slave)
149 #ifdef CONFIG_ARCH_KIRKWOOD
150 kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
155 __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
160 int spi_claim_bus(struct spi_slave *slave)
162 return board_spi_claim_bus(slave);
165 __attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
169 void spi_release_bus(struct spi_slave *slave)
171 board_spi_release_bus(slave);
174 #ifndef CONFIG_SPI_CS_IS_VALID
176 * you can define this function board specific
177 * define above CONFIG in board specific config file and
178 * provide the function in board specific src file
180 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
182 return bus == 0 && (cs == 0 || cs == 1);
186 void spi_cs_activate(struct spi_slave *slave)
188 _spi_cs_activate(spireg);
191 void spi_cs_deactivate(struct spi_slave *slave)
193 _spi_cs_deactivate(spireg);
196 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
197 const void *dout, void *din, unsigned long flags)
199 return _spi_xfer(spireg, bitlen, dout, din, flags);
204 /* Here now the DM part */
206 struct mvebu_spi_dev {
207 bool is_errata_50mhz_ac;
210 struct mvebu_spi_platdata {
211 struct kwspi_registers *spireg;
212 bool is_errata_50mhz_ac;
215 struct mvebu_spi_priv {
216 struct kwspi_registers *spireg;
219 static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
221 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
222 struct kwspi_registers *reg = plat->spireg;
225 /* calculate spi clock prescaller using max_hz */
226 data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
227 data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
228 data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
230 /* program spi clock prescaler using max_hz */
231 writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
232 debug("data = 0x%08x\n", data);
237 static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
239 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
240 struct kwspi_registers *reg = plat->spireg;
244 * Erratum description: (Erratum NO. FE-9144572) The device
245 * SPI interface supports frequencies of up to 50 MHz.
246 * However, due to this erratum, when the device core clock is
247 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
248 * clock and CPOL=CPHA=1 there might occur data corruption on
249 * reads from the SPI device.
250 * Erratum Workaround:
251 * Work in one of the following configurations:
252 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
254 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
255 * Register" before setting the interface.
257 data = readl(®->timing1);
258 data &= ~KW_SPI_TMISO_SAMPLE_MASK;
260 if (CONFIG_SYS_TCLK == 250000000 &&
263 data |= KW_SPI_TMISO_SAMPLE_2;
265 data |= KW_SPI_TMISO_SAMPLE_1;
267 writel(data, ®->timing1);
270 static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
272 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
273 struct kwspi_registers *reg = plat->spireg;
274 u32 data = readl(®->cfg);
276 data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
282 if (mode & SPI_LSB_FIRST)
283 data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
285 writel(data, ®->cfg);
287 if (plat->is_errata_50mhz_ac)
288 mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
293 static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
294 const void *dout, void *din, unsigned long flags)
296 struct udevice *bus = dev->parent;
297 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
299 return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
302 __attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
307 static int mvebu_spi_claim_bus(struct udevice *dev)
309 struct udevice *bus = dev->parent;
310 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
312 /* Configure the chip-select in the CTRL register */
313 clrsetbits_le32(&plat->spireg->ctrl,
314 KWSPI_CS_MASK << KWSPI_CS_SHIFT,
315 spi_chip_select(dev) << KWSPI_CS_SHIFT);
317 return mvebu_board_spi_claim_bus(dev);
320 __attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
325 static int mvebu_spi_release_bus(struct udevice *dev)
327 return mvebu_board_spi_release_bus(dev);
330 static int mvebu_spi_probe(struct udevice *bus)
332 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
333 struct kwspi_registers *reg = plat->spireg;
335 writel(KWSPI_SMEMRDY, ®->ctrl);
336 writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
337 writel(KWSPI_IRQMASK, ®->irq_mask);
342 static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
344 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
345 const struct mvebu_spi_dev *drvdata =
346 (struct mvebu_spi_dev *)dev_get_driver_data(bus);
348 plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
349 plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
354 static const struct dm_spi_ops mvebu_spi_ops = {
355 .claim_bus = mvebu_spi_claim_bus,
356 .release_bus = mvebu_spi_release_bus,
357 .xfer = mvebu_spi_xfer,
358 .set_speed = mvebu_spi_set_speed,
359 .set_mode = mvebu_spi_set_mode,
361 * cs_info is not needed, since we require all chip selects to be
362 * in the device tree explicitly
366 static const struct mvebu_spi_dev armada_spi_dev_data = {
367 .is_errata_50mhz_ac = false,
370 static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
371 .is_errata_50mhz_ac = false,
374 static const struct mvebu_spi_dev armada_375_spi_dev_data = {
375 .is_errata_50mhz_ac = false,
378 static const struct mvebu_spi_dev armada_380_spi_dev_data = {
379 .is_errata_50mhz_ac = true,
382 static const struct udevice_id mvebu_spi_ids[] = {
384 .compatible = "marvell,orion-spi",
385 .data = (ulong)&armada_spi_dev_data,
388 .compatible = "marvell,armada-375-spi",
389 .data = (ulong)&armada_375_spi_dev_data
392 .compatible = "marvell,armada-380-spi",
393 .data = (ulong)&armada_380_spi_dev_data
396 .compatible = "marvell,armada-xp-spi",
397 .data = (ulong)&armada_xp_spi_dev_data
402 U_BOOT_DRIVER(mvebu_spi) = {
405 .of_match = mvebu_spi_ids,
406 .ops = &mvebu_spi_ops,
407 .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
408 .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
409 .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
410 .probe = mvebu_spi_probe,