1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2020-2021 Broadcom
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/iopoll.h>
14 #include <linux/log2.h>
16 /* Delay required to change the mode of operation */
17 #define BUSY_DELAY_US 1
18 #define BUSY_TIMEOUT_US 200000
19 #define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3))
22 #define QSPI_AXI_CLK 175000000
28 #define CDRAM_CONT BIT(7)
29 #define CDRAM_BITS_EN BIT(6)
30 #define CDRAM_QUAD_MODE BIT(8)
31 #define CDRAM_RBIT_INPUT BIT(10)
32 #define MSPI_SPE BIT(6)
33 #define MSPI_CONT_AFTER_CMD BIT(7)
34 #define MSPI_MSTR BIT(7)
37 #define MSPI_SPCR0_MSB_BITS_8 0x00000020
38 #define BSPI_RAF_CONTROL_START_MASK 0x00000001
39 #define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
40 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
41 #define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3
42 #define BSPI_STRAP_OVERRIDE_4BYTE_SHIFT 2
43 #define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1
44 #define BSPI_STRAP_OVERRIDE_SHIFT 0
45 #define BSPI_BPC_DATA_SHIFT 0
46 #define BSPI_BPC_MODE_SHIFT 8
47 #define BSPI_BPC_ADDR_SHIFT 16
48 #define BSPI_BPC_CMD_SHIFT 24
49 #define BSPI_BPP_ADDR_SHIFT 16
52 #define MSPI_SPCR0_LSB_REG 0x000
53 #define MSPI_SPCR0_MSB_REG 0x004
54 #define MSPI_SPCR1_LSB_REG 0x008
55 #define MSPI_SPCR1_MSB_REG 0x00c
56 #define MSPI_NEWQP_REG 0x010
57 #define MSPI_ENDQP_REG 0x014
58 #define MSPI_SPCR2_REG 0x018
59 #define MSPI_STATUS_REG 0x020
60 #define MSPI_CPTQP_REG 0x024
61 #define MSPI_TX_REG 0x040
62 #define MSPI_RX_REG 0x0c0
63 #define MSPI_CDRAM_REG 0x140
64 #define MSPI_WRITE_LOCK_REG 0x180
65 #define MSPI_DISABLE_FLUSH_GEN_REG 0x184
68 #define BSPI_REVISION_ID_REG 0x000
69 #define BSPI_SCRATCH_REG 0x004
70 #define BSPI_MAST_N_BOOT_CTRL_REG 0x008
71 #define BSPI_BUSY_STATUS_REG 0x00c
72 #define BSPI_INTR_STATUS_REG 0x010
73 #define BSPI_B0_STATUS_REG 0x014
74 #define BSPI_B0_CTRL_REG 0x018
75 #define BSPI_B1_STATUS_REG 0x01c
76 #define BSPI_B1_CTRL_REG 0x020
77 #define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024
78 #define BSPI_FLEX_MODE_ENABLE_REG 0x028
79 #define BSPI_BITS_PER_CYCLE_REG 0x02C
80 #define BSPI_BITS_PER_PHASE_REG 0x030
81 #define BSPI_CMD_AND_MODE_BYTE_REG 0x034
82 #define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038
83 #define BSPI_XOR_VALUE_REG 0x03C
84 #define BSPI_XOR_ENABLE_REG 0x040
85 #define BSPI_PIO_MODE_ENABLE_REG 0x044
86 #define BSPI_PIO_IODIR_REG 0x048
87 #define BSPI_PIO_DATA_REG 0x04C
90 #define BSPI_RAF_START_ADDRESS_REG 0x00
91 #define BSPI_RAF_NUM_WORDS_REG 0x04
92 #define BSPI_RAF_CTRL_REG 0x08
93 #define BSPI_RAF_FULLNESS_REG 0x0C
94 #define BSPI_RAF_WATERMARK_REG 0x10
95 #define BSPI_RAF_STATUS_REG 0x14
96 #define BSPI_RAF_READ_DATA_REG 0x18
97 #define BSPI_RAF_WORD_CNT_REG 0x1C
98 #define BSPI_RAF_CURR_ADDR_REG 0x20
100 #define XFER_DUAL BIT(30)
101 #define XFER_QUAD BIT(31)
103 #define FLUSH_BIT BIT(0)
104 #define MAST_N_BOOT_BIT BIT(0)
105 #define WRITE_LOCK_BIT BIT(0)
107 #define CEIL(m, n) (((m) + (n) - 1) / (n))
108 #define UPPER_BYTE_MASK 0xFF000000
109 #define SIZE_16MB 0x001000000
112 * struct bcmspi_priv - qspi private structure
114 * @bspi_addr: bspi read address
115 * @bspi_4byte_addr: bspi 4 byte address mode
116 * @mspi: mspi registers block address
117 * @bspi: bspi registers block address
118 * @bspi_raf: bspi raf registers block address
122 bool bspi_4byte_addr;
130 static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
132 writel(0, priv->bspi + BSPI_B0_CTRL_REG);
133 writel(0, priv->bspi + BSPI_B1_CTRL_REG);
134 writel(FLUSH_BIT, priv->bspi + BSPI_B0_CTRL_REG);
135 writel(FLUSH_BIT, priv->bspi + BSPI_B1_CTRL_REG);
138 static int bspi_enable(struct bcmspi_priv *priv)
140 /* Disable write lock */
141 writel(0, priv->mspi + MSPI_WRITE_LOCK_REG);
142 /* Flush prefetch buffers */
143 bspi_flush_prefetch_buffers(priv);
145 writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
150 static int bspi_disable(struct bcmspi_priv *priv)
155 if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
156 ret = readl_poll_timeout(priv->bspi + BSPI_BUSY_STATUS_REG, val, !(val & 1),
159 printf("%s: Failed to disable bspi, device busy\n", __func__);
164 writel(MAST_N_BOOT_BIT, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
165 udelay(BUSY_DELAY_US);
167 val = readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
169 printf("%s: Failed to enable mspi\n", __func__);
174 /* Enable write lock */
175 writel(WRITE_LOCK_BIT, priv->mspi + MSPI_WRITE_LOCK_REG);
180 static int bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes)
188 * Flush data from the previous session (unlikely)
189 * Read outstanding bits in the poll condition to empty FIFO
191 ret = readl_poll_timeout(priv->bspi_raf + BSPI_RAF_STATUS_REG,
193 (!readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG) &&
194 status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK) &&
195 !(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK),
198 printf("%s: Failed to flush fifo\n", __func__);
202 /* Transfer is in words */
203 words = CEIL(bytes, 4);
206 if (priv->bspi_4byte_addr) {
207 u32 val = priv->bspi_addr & UPPER_BYTE_MASK;
209 if (val != readl(priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG)) {
210 writel(val, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
211 bspi_flush_prefetch_buffers(priv);
215 writel(priv->bspi_addr & ~UPPER_BYTE_MASK, priv->bspi_raf + BSPI_RAF_START_ADDRESS_REG);
216 writel(words, priv->bspi_raf + BSPI_RAF_NUM_WORDS_REG);
217 writel(0, priv->bspi_raf + BSPI_RAF_WATERMARK_REG);
220 writel(BSPI_RAF_CONTROL_START_MASK, priv->bspi_raf + BSPI_RAF_CTRL_REG);
221 aligned = DWORD_ALIGNED(rx);
223 status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
224 if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
225 /* RAF is LE only, convert data to host endianness */
226 u32 data = le32_to_cpu(readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG));
228 /* Check if we can use the whole word */
229 if (aligned && bytes >= 4) {
234 uint chunk = min(bytes, 4U);
236 /* Read out bytes one by one */
247 if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) {
248 /* FIFO is empty and the session is done */
256 static int bspi_read(struct bcmspi_priv *priv, u8 *rx, uint bytes)
262 /* Special handing since RAF cannot go across 16MB boundary */
264 /* Divide into multiple transfers if it goes across the 16MB boundary */
265 if (priv->bspi_4byte_addr && (priv->bspi_addr >> 24) !=
266 ((priv->bspi_addr + bytes) >> 24))
267 trans = SIZE_16MB - (priv->bspi_addr & ~UPPER_BYTE_MASK);
269 ret = bspi_read_via_raf(priv, rx, trans);
273 priv->bspi_addr += trans;
278 bspi_flush_prefetch_buffers(priv);
282 static void bspi_set_flex_mode(struct bcmspi_priv *priv, const struct spi_mem_op *op)
284 int bpp = (op->dummy.nbytes * 8) / op->dummy.buswidth;
285 int cmd = op->cmd.opcode;
286 int bpc = ilog2(op->data.buswidth) << BSPI_BPC_DATA_SHIFT |
287 ilog2(op->addr.buswidth) << BSPI_BPC_ADDR_SHIFT |
288 ilog2(op->cmd.buswidth) << BSPI_BPC_CMD_SHIFT;
289 int so = BIT(BSPI_STRAP_OVERRIDE_SHIFT) |
290 (op->data.buswidth > 1) << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT |
291 (op->addr.nbytes > 3) << BSPI_STRAP_OVERRIDE_4BYTE_SHIFT |
292 (op->data.buswidth > 3) << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT;
294 /* Disable flex mode first */
295 writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
297 /* Configure single, dual or quad mode */
298 writel(bpc, priv->bspi + BSPI_BITS_PER_CYCLE_REG);
301 writel(cmd, priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
303 /* Count of dummy cycles */
304 writel(bpp, priv->bspi + BSPI_BITS_PER_PHASE_REG);
306 /* Enable 4-byte address */
307 if (priv->bspi_4byte_addr) {
308 setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
310 clrbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
311 writel(0, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
314 /* Enable flex mode to take effect */
315 writel(1, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
317 /* Flush prefetch buffers since 32MB window BSPI could be used */
318 bspi_flush_prefetch_buffers(priv);
320 /* Override the strap settings */
321 writel(so, priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG);
324 static int bspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
326 struct udevice *bus = dev_get_parent(slave->dev);
327 struct bcmspi_priv *priv = dev_get_priv(bus);
331 if (op->data.dir == SPI_MEM_DATA_IN &&
332 op->data.nbytes && op->addr.nbytes) {
333 priv->bspi_4byte_addr = (op->addr.nbytes > 3);
334 priv->bspi_addr = op->addr.val;
335 bspi_set_flex_mode(priv, op);
336 ret = bspi_read(priv, op->data.buf.in, op->data.nbytes);
342 static const struct spi_controller_mem_ops bspi_mem_ops = {
343 .exec_op = bspi_exec_op,
348 static int mspi_exec(struct bcmspi_priv *priv, uint bytes, const u8 *tx, u8 *rx, ulong flags)
350 u32 cdr = CDRAM_PCS0 | CDRAM_CONT;
351 bool use_16bits = !(bytes & 1);
353 if (flags & XFER_QUAD) {
354 cdr |= CDRAM_QUAD_MODE;
357 cdr |= CDRAM_RBIT_INPUT;
368 chunk = min(bytes, NUM_CDRAM * 2);
369 queues = (chunk + 1) / 2;
373 for (i = 0; i < queues; i++)
374 writel(cdr | CDRAM_BITS_EN, priv->mspi + MSPI_CDRAM_REG + 4 * i);
377 for (i = 0; i < chunk; i++)
378 writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 4 * i);
380 /* Determine how many bytes to process this time */
381 chunk = min(bytes, NUM_CDRAM);
385 /* Fill CDRAMs and TXRAMS */
386 for (i = 0; i < chunk; i++) {
387 writel(cdr, priv->mspi + MSPI_CDRAM_REG + 4 * i);
388 writel(tx ? tx[i] : 0xff, priv->mspi + MSPI_TX_REG + 8 * i);
392 /* Setup queue pointers */
393 writel(0, priv->mspi + MSPI_NEWQP_REG);
394 writel(queues - 1, priv->mspi + MSPI_ENDQP_REG);
396 /* Deassert CS if requested and it's the last transfer */
397 if (bytes == 0 && (flags & SPI_XFER_END))
398 clrbits_le32(priv->mspi + MSPI_CDRAM_REG + ((queues - 1) << 2), CDRAM_CONT);
401 writel(0, priv->mspi + MSPI_STATUS_REG);
402 if (bytes == 0 && (flags & SPI_XFER_END))
403 writel(MSPI_SPE, priv->mspi + MSPI_SPCR2_REG);
405 writel(MSPI_SPE | MSPI_CONT_AFTER_CMD,
406 priv->mspi + MSPI_SPCR2_REG);
408 ret = readl_poll_timeout(priv->mspi + MSPI_STATUS_REG, val, (val & 1),
411 printf("%s: Failed to disable bspi, device busy\n", __func__);
418 for (i = 0; i < chunk; i++)
419 rx[i] = readl(priv->mspi + MSPI_RX_REG + 4 * i) & 0xff;
421 for (i = 0; i < chunk; i++)
422 rx[i] = readl(priv->mspi + MSPI_RX_REG + 8 * i + 4) & 0xff;
426 /* Advance pointers */
436 static int mspi_xfer(struct udevice *dev, uint bitlen, const void *dout, void *din, ulong flags)
438 struct udevice *bus = dev_get_parent(dev);
439 struct bcmspi_priv *priv = dev_get_priv(bus);
443 /* we can only transfer multiples of 8 bits */
445 return -EPROTONOSUPPORT;
449 if (flags & SPI_XFER_BEGIN) {
451 ret = bspi_disable(priv);
458 ret = mspi_exec(priv, bytes, dout, din, flags);
460 if (flags & SPI_XFER_END) {
461 /* Switch back to BSPI */
462 ret = bspi_enable(priv);
470 /* iProc interface */
472 static int iproc_qspi_set_speed(struct udevice *bus, uint speed)
474 struct bcmspi_priv *priv = dev_get_priv(bus);
477 /* MSPI: SCK configuration */
478 spbr = (QSPI_AXI_CLK - 1) / (2 * speed) + 1;
479 writel(max(min(spbr, SPBR_MAX), SPBR_MIN), priv->mspi + MSPI_SPCR0_LSB_REG);
484 static int iproc_qspi_set_mode(struct udevice *bus, uint mode)
486 struct bcmspi_priv *priv = dev_get_priv(bus);
488 /* MSPI: set master bit and mode */
489 writel(MSPI_MSTR /* Master */ | (mode & 3), priv->mspi + MSPI_SPCR0_MSB_REG);
494 static int iproc_qspi_claim_bus(struct udevice *dev)
500 static int iproc_qspi_release_bus(struct udevice *dev)
502 struct udevice *bus = dev_get_parent(dev);
503 struct bcmspi_priv *priv = dev_get_priv(bus);
505 /* Make sure no operation is in progress */
506 writel(0, priv->mspi + MSPI_SPCR2_REG);
507 udelay(BUSY_DELAY_US);
512 static int iproc_qspi_of_to_plat(struct udevice *bus)
514 struct bcmspi_priv *priv = dev_get_priv(bus);
516 priv->bspi = dev_read_addr_name(bus, "bspi");
517 if (IS_ERR((void *)priv->bspi)) {
518 printf("%s: Failed to get bspi base address\n", __func__);
519 return PTR_ERR((void *)priv->bspi);
522 priv->bspi_raf = dev_read_addr_name(bus, "bspi_raf");
523 if (IS_ERR((void *)priv->bspi_raf)) {
524 printf("%s: Failed to get bspi_raf base address\n", __func__);
525 return PTR_ERR((void *)priv->bspi_raf);
528 priv->mspi = dev_read_addr_name(bus, "mspi");
529 if (IS_ERR((void *)priv->mspi)) {
530 printf("%s: Failed to get mspi base address\n", __func__);
531 return PTR_ERR((void *)priv->mspi);
537 static int iproc_qspi_probe(struct udevice *bus)
539 struct bcmspi_priv *priv = dev_get_priv(bus);
542 writel(0, priv->mspi + MSPI_SPCR1_LSB_REG);
543 writel(0, priv->mspi + MSPI_SPCR1_MSB_REG);
544 writel(0, priv->mspi + MSPI_NEWQP_REG);
545 writel(0, priv->mspi + MSPI_ENDQP_REG);
546 writel(0, priv->mspi + MSPI_SPCR2_REG);
554 static const struct dm_spi_ops iproc_qspi_ops = {
555 .claim_bus = iproc_qspi_claim_bus,
556 .release_bus = iproc_qspi_release_bus,
558 .set_speed = iproc_qspi_set_speed,
559 .set_mode = iproc_qspi_set_mode,
560 .mem_ops = &bspi_mem_ops,
563 static const struct udevice_id iproc_qspi_ids[] = {
564 { .compatible = "brcm,iproc-qspi" },
568 U_BOOT_DRIVER(iproc_qspi) = {
569 .name = "iproc_qspi",
571 .of_match = iproc_qspi_ids,
572 .ops = &iproc_qspi_ops,
573 .of_to_plat = iproc_qspi_of_to_plat,
574 .priv_auto = sizeof(struct bcmspi_priv),
575 .probe = iproc_qspi_probe,