1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
11 #include <linux/bitops.h>
12 struct ich7_spi_regs {
24 struct ich9_spi_regs {
25 uint32_t bfpr; /* 0x00 */
30 uint32_t fdata[16]; /* 0x10 */
31 uint32_t frap; /* 0x50 */
33 uint32_t _reserved1[3];
34 uint32_t pr[5]; /* 0x74 */
35 uint32_t _reserved2[2];
36 uint8_t ssfs; /* 0x90 */
38 uint16_t preop; /* 0x94 */
40 uint8_t opmenu[8]; /* 0x98 */
42 uint8_t _reserved3[12];
43 uint32_t fdoc; /* 0xb0 */
45 uint8_t _reserved4[8];
46 uint32_t afc; /* 0xc0 */
49 uint8_t _reserved5[4];
50 uint32_t fpb; /* 0xd0 */
51 uint8_t _reserved6[28];
52 uint32_t srdl; /* 0xf0 */
65 SPIS_RESERVED_MASK = 0x7ff0,
66 SSFS_RESERVED_MASK = 0x7fe2
76 SSFC_SCF_MASK = 0x070000,
77 SSFC_RESERVED = 0xf80000,
79 /* Mask for speed byte, biuts 23:16 of SSFC */
80 SSFC_SCF_33MHZ = 0x01,
87 HSFS_BERASE_MASK = 0x0018,
88 HSFS_BERASE_SHIFT = 3,
97 HSFC_FCYCLE_MASK = 0x0006,
98 HSFC_FCYCLE_SHIFT = 1,
99 HSFC_FDBC_MASK = 0x3f00,
115 #define SPI_OPCODE_WRSR 0x01
116 #define SPI_OPCODE_PAGE_PROGRAM 0x02
117 #define SPI_OPCODE_READ 0x03
118 #define SPI_OPCODE_WRDIS 0x04
119 #define SPI_OPCODE_RDSR 0x05
120 #define SPI_OPCODE_WREN 0x06
121 #define SPI_OPCODE_FAST_READ 0x0b
122 #define SPI_OPCODE_ERASE_SECT 0x20
123 #define SPI_OPCODE_READ_ID 0x9f
124 #define SPI_OPCODE_ERASE_BLOCK 0xd8
126 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
127 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
128 #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
129 #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
131 #define SPI_OPMENU_0 SPI_OPCODE_WRSR
132 #define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
134 #define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
135 #define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
137 #define SPI_OPMENU_2 SPI_OPCODE_READ
138 #define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
140 #define SPI_OPMENU_3 SPI_OPCODE_RDSR
141 #define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
143 #define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
144 #define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
146 #define SPI_OPMENU_5 SPI_OPCODE_READ_ID
147 #define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
149 #define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
150 #define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
152 #define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
153 #define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
155 #define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
156 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
157 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
158 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
159 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
160 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
161 (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
162 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
163 (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
165 #define ICH_BOUNDARY 0x1000
167 #define HSFSTS_FDBC_SHIFT 24
168 #define HSFSTS_FDBC_MASK (0x3f << HSFSTS_FDBC_SHIFT)
169 #define HSFSTS_WET BIT(21)
170 #define HSFSTS_FCYCLE_SHIFT 17
171 #define HSFSTS_FCYCLE_MASK (0xf << HSFSTS_FCYCLE_SHIFT)
173 /* Supported flash cycle types */
174 enum hsfsts_cycle_t {
175 HSFSTS_CYCLE_READ = 0,
176 HSFSTS_CYCLE_WRITE = 2,
177 HSFSTS_CYCLE_4K_ERASE,
178 HSFSTS_CYCLE_64K_ERASE,
181 HSFSTS_CYCLE_WR_STATUS,
182 HSFSTS_CYCLE_RD_STATUS,
185 #define HSFSTS_FGO BIT(16)
186 #define HSFSTS_FLOCKDN BIT(15)
187 #define HSFSTS_FDV BIT(14)
188 #define HSFSTS_FDOPSS BIT(13)
189 #define HSFSTS_WRSDIS BIT(11)
190 #define HSFSTS_SAF_CE BIT(8)
191 #define HSFSTS_SAF_ACTIVE BIT(7)
192 #define HSFSTS_SAF_LE BIT(6)
193 #define HSFSTS_SCIP BIT(5)
194 #define HSFSTS_SAF_DLE BIT(4)
195 #define HSFSTS_SAF_ERROR BIT(3)
196 #define HSFSTS_AEL BIT(2)
197 #define HSFSTS_FCERR BIT(1)
198 #define HSFSTS_FDONE BIT(0)
199 #define HSFSTS_W1C_BITS 0xff
201 /* Maximum bytes of data that can fit in FDATAn (0x10) registers */
202 #define SPIBAR_FDATA_FIFO_SIZE 0x40
204 #define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000
212 struct ich_spi_priv {
215 void *base; /* Base of register set */
225 uint32_t *pr; /* only for ich9 */
226 int speed; /* pointer to speed control */
227 ulong max_speed; /* Maximum bus speed in MHz */
228 ulong cur_speed; /* Current bus speed */
229 struct spi_trans trans; /* current transaction in progress */
230 struct udevice *pch; /* PCH, used to control SPI access */
233 struct ich_spi_plat {
234 #if CONFIG_IS_ENABLED(OF_PLATDATA)
235 struct dtd_intel_fast_spi dtplat;
237 enum ich_version ich_version; /* Controller version, 7 or 9 */
238 bool lockdown; /* lock down controller settings? */
239 ulong mmio_base; /* Base of MMIO registers */
240 pci_dev_t bdf; /* PCI address used by of-platdata */
241 bool hwseq; /* Use hardware sequencing (not s/w) */