drivers/spi/ich.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2011-12 The Chromium OS Authors.
   4  *
   5  * This file is derived from the flashrom project.
   6  */
   7
   8 #include <common.h>
   9 #include <div64.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <pch.h>
  14 #include <pci.h>
  15 #include <pci_ids.h>
  16 #include <spi.h>
  17 #include <spi-mem.h>
  18 #include <asm/io.h>
  19
  20 #include "ich.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef DEBUG_TRACE
  25 #define debug_trace(fmt, args...) debug(fmt, ##args)
  26 #else
  27 #define debug_trace(x, args...)
  28 #endif
  29
  30 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
  31 {
  32         u8 value = readb(priv->base + reg);
  33
  34         debug_trace("read %2.2x from %4.4x\n", value, reg);
  35
  36         return value;
  37 }
  38
  39 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
  40 {
  41         u16 value = readw(priv->base + reg);
  42
  43         debug_trace("read %4.4x from %4.4x\n", value, reg);
  44
  45         return value;
  46 }
  47
  48 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
  49 {
  50         u32 value = readl(priv->base + reg);
  51
  52         debug_trace("read %8.8x from %4.4x\n", value, reg);
  53
  54         return value;
  55 }
  56
  57 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
  58 {
  59         writeb(value, priv->base + reg);
  60         debug_trace("wrote %2.2x to %4.4x\n", value, reg);
  61 }
  62
  63 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
  64 {
  65         writew(value, priv->base + reg);
  66         debug_trace("wrote %4.4x to %4.4x\n", value, reg);
  67 }
  68
  69 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
  70 {
  71         writel(value, priv->base + reg);
  72         debug_trace("wrote %8.8x to %4.4x\n", value, reg);
  73 }
  74
  75 static void write_reg(struct ich_spi_priv *priv, const void *value,
  76                       int dest_reg, uint32_t size)
  77 {
  78         memcpy_toio(priv->base + dest_reg, value, size);
  79 }
  80
  81 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
  82                      uint32_t size)
  83 {
  84         memcpy_fromio(value, priv->base + src_reg, size);
  85 }
  86
  87 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
  88 {
  89         const uint32_t bbar_mask = 0x00ffff00;
  90         uint32_t ichspi_bbar;
  91
  92         minaddr &= bbar_mask;
  93         ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
  94         ichspi_bbar |= minaddr;
  95         ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
  96 }
  97
  98 /* @return 1 if the SPI flash supports the 33MHz speed */
  99 static int ich9_can_do_33mhz(struct udevice *dev)
 100 {
 101         struct ich_spi_priv *priv = dev_get_priv(dev);
 102         u32 fdod, speed;
 103
 104         /* Observe SPI Descriptor Component Section 0 */
 105         dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
 106
 107         /* Extract the Write/Erase SPI Frequency from descriptor */
 108         dm_pci_read_config32(priv->pch, 0xb4, &fdod);
 109
 110         /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
 111         speed = (fdod >> 21) & 7;
 112
 113         return speed == 1;
 114 }
 115
 116 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
 117 {
 118         if (plat->ich_version == ICHV_7) {
 119                 struct ich7_spi_regs *ich7_spi = sbase;
 120
 121                 setbits_le16(&ich7_spi->spis, SPIS_LOCK);
 122         } else if (plat->ich_version == ICHV_9) {
 123                 struct ich9_spi_regs *ich9_spi = sbase;
 124
 125                 setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
 126         }
 127 }
 128
 129 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
 130 {
 131         int lock = 0;
 132
 133         if (plat->ich_version == ICHV_7) {
 134                 struct ich7_spi_regs *ich7_spi = sbase;
 135
 136                 lock = readw(&ich7_spi->spis) & SPIS_LOCK;
 137         } else if (plat->ich_version == ICHV_9) {
 138                 struct ich9_spi_regs *ich9_spi = sbase;
 139
 140                 lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
 141         }
 142
 143         return lock != 0;
 144 }
 145
 146 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
 147                             bool lock)
 148 {
 149         uint16_t optypes;
 150         uint8_t opmenu[ctlr->menubytes];
 151
 152         if (!lock) {
 153                 /* The lock is off, so just use index 0. */
 154                 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
 155                 optypes = ich_readw(ctlr, ctlr->optype);
 156                 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
 157                 ich_writew(ctlr, optypes, ctlr->optype);
 158                 return 0;
 159         } else {
 160                 /* The lock is on. See if what we need is on the menu. */
 161                 uint8_t optype;
 162                 uint16_t opcode_index;
 163
 164                 /* Write Enable is handled as atomic prefix */
 165                 if (trans->opcode == SPI_OPCODE_WREN)
 166                         return 0;
 167
 168                 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
 169                 for (opcode_index = 0; opcode_index < ctlr->menubytes;
 170                                 opcode_index++) {
 171                         if (opmenu[opcode_index] == trans->opcode)
 172                                 break;
 173                 }
 174
 175                 if (opcode_index == ctlr->menubytes) {
 176                         printf("ICH SPI: Opcode %x not found\n",
 177                                trans->opcode);
 178                         return -EINVAL;
 179                 }
 180
 181                 optypes = ich_readw(ctlr, ctlr->optype);
 182                 optype = (optypes >> (opcode_index * 2)) & 0x3;
 183
 184                 if (optype != trans->type) {
 185                         printf("ICH SPI: Transaction doesn't fit type %d\n",
 186                                optype);
 187                         return -ENOSPC;
 188                 }
 189                 return opcode_index;
 190         }
 191 }
 192
 193 /*
 194  * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
 195  * below is true) or 0. In case the wait was for the bit(s) to set - write
 196  * those bits back, which would cause resetting them.
 197  *
 198  * Return the last read status value on success or -1 on failure.
 199  */
 200 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
 201                            int wait_til_set)
 202 {
 203         int timeout = 600000; /* This will result in 6s */
 204         u16 status = 0;
 205
 206         while (timeout--) {
 207                 status = ich_readw(ctlr, ctlr->status);
 208                 if (wait_til_set ^ ((status & bitmask) == 0)) {
 209                         if (wait_til_set) {
 210                                 ich_writew(ctlr, status & bitmask,
 211                                            ctlr->status);
 212                         }
 213                         return status;
 214                 }
 215                 udelay(10);
 216         }
 217
 218         printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
 219                status, bitmask);
 220         return -ETIMEDOUT;
 221 }
 222
 223 static void ich_spi_config_opcode(struct udevice *dev)
 224 {
 225         struct ich_spi_priv *ctlr = dev_get_priv(dev);
 226
 227         /*
 228          * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
 229          * to prevent accidental or intentional writes. Before they get
 230          * locked down, these registers should be initialized properly.
 231          */
 232         ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
 233         ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
 234         ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
 235         ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
 236 }
 237
 238 static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 239 {
 240         struct udevice *bus = dev_get_parent(slave->dev);
 241         struct ich_spi_platdata *plat = dev_get_platdata(bus);
 242         struct ich_spi_priv *ctlr = dev_get_priv(bus);
 243         uint16_t control;
 244         int16_t opcode_index;
 245         int with_address;
 246         int status;
 247         struct spi_trans *trans = &ctlr->trans;
 248         bool lock = spi_lock_status(plat, ctlr->base);
 249         int ret = 0;
 250
 251         trans->in = NULL;
 252         trans->out = NULL;
 253         trans->type = 0xFF;
 254
 255         if (op->data.nbytes) {
 256                 if (op->data.dir == SPI_MEM_DATA_IN) {
 257                         trans->in = op->data.buf.in;
 258                         trans->bytesin = op->data.nbytes;
 259                 } else {
 260                         trans->out = op->data.buf.out;
 261                         trans->bytesout = op->data.nbytes;
 262                 }
 263         }
 264
 265         if (trans->opcode != op->cmd.opcode)
 266                 trans->opcode = op->cmd.opcode;
 267
 268         if (lock && trans->opcode == SPI_OPCODE_WRDIS)
 269                 return 0;
 270
 271         if (trans->opcode == SPI_OPCODE_WREN) {
 272                 /*
 273                  * Treat Write Enable as Atomic Pre-Op if possible
 274                  * in order to prevent the Management Engine from
 275                  * issuing a transaction between WREN and DATA.
 276                  */
 277                 if (!lock)
 278                         ich_writew(ctlr, trans->opcode, ctlr->preop);
 279                 return 0;
 280         }
 281
 282         ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
 283         if (ret < 0)
 284                 return ret;
 285
 286         if (plat->ich_version == ICHV_7)
 287                 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 288         else
 289                 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 290
 291         /* Try to guess spi transaction type */
 292         if (op->data.dir == SPI_MEM_DATA_OUT) {
 293                 if (op->addr.nbytes)
 294                         trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
 295                 else
 296                         trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
 297         } else {
 298                 if (op->addr.nbytes)
 299                         trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
 300                 else
 301                         trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
 302         }
 303         /* Special erase case handling */
 304         if (op->addr.nbytes && !op->data.buswidth)
 305                 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
 306
 307         opcode_index = spi_setup_opcode(ctlr, trans, lock);
 308         if (opcode_index < 0)
 309                 return -EINVAL;
 310
 311         if (op->addr.nbytes) {
 312                 trans->offset = op->addr.val;
 313                 with_address = 1;
 314         }
 315
 316         if (ctlr->speed && ctlr->max_speed >= 33000000) {
 317                 int byte;
 318
 319                 byte = ich_readb(ctlr, ctlr->speed);
 320                 if (ctlr->cur_speed >= 33000000)
 321                         byte |= SSFC_SCF_33MHZ;
 322                 else
 323                         byte &= ~SSFC_SCF_33MHZ;
 324                 ich_writeb(ctlr, byte, ctlr->speed);
 325         }
 326
 327         /* Preset control fields */
 328         control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
 329
 330         /* Issue atomic preop cycle if needed */
 331         if (ich_readw(ctlr, ctlr->preop))
 332                 control |= SPIC_ACS;
 333
 334         if (!trans->bytesout && !trans->bytesin) {
 335                 /* SPI addresses are 24 bit only */
 336                 if (with_address) {
 337                         ich_writel(ctlr, trans->offset & 0x00FFFFFF,
 338                                    ctlr->addr);
 339                 }
 340                 /*
 341                  * This is a 'no data' command (like Write Enable), its
 342                  * bitesout size was 1, decremented to zero while executing
 343                  * spi_setup_opcode() above. Tell the chip to send the
 344                  * command.
 345                  */
 346                 ich_writew(ctlr, control, ctlr->control);
 347
 348                 /* wait for the result */
 349                 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
 350                 if (status < 0)
 351                         return status;
 352
 353                 if (status & SPIS_FCERR) {
 354                         debug("ICH SPI: Command transaction error\n");
 355                         return -EIO;
 356                 }
 357
 358                 return 0;
 359         }
 360
 361         while (trans->bytesout || trans->bytesin) {
 362                 uint32_t data_length;
 363
 364                 /* SPI addresses are 24 bit only */
 365                 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
 366
 367                 if (trans->bytesout)
 368                         data_length = min(trans->bytesout, ctlr->databytes);
 369                 else
 370                         data_length = min(trans->bytesin, ctlr->databytes);
 371
 372                 /* Program data into FDATA0 to N */
 373                 if (trans->bytesout) {
 374                         write_reg(ctlr, trans->out, ctlr->data, data_length);
 375                         trans->bytesout -= data_length;
 376                 }
 377
 378                 /* Add proper control fields' values */
 379                 control &= ~((ctlr->databytes - 1) << 8);
 380                 control |= SPIC_DS;
 381                 control |= (data_length - 1) << 8;
 382
 383                 /* write it */
 384                 ich_writew(ctlr, control, ctlr->control);
 385
 386                 /* Wait for Cycle Done Status or Flash Cycle Error */
 387                 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
 388                 if (status < 0)
 389                         return status;
 390
 391                 if (status & SPIS_FCERR) {
 392                         debug("ICH SPI: Data transaction error %x\n", status);
 393                         return -EIO;
 394                 }
 395
 396                 if (trans->bytesin) {
 397                         read_reg(ctlr, ctlr->data, trans->in, data_length);
 398                         trans->bytesin -= data_length;
 399                 }
 400         }
 401
 402         /* Clear atomic preop now that xfer is done */
 403         if (!lock)
 404                 ich_writew(ctlr, 0, ctlr->preop);
 405
 406         return 0;
 407 }
 408
 409 static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
 410 {
 411         unsigned int page_offset;
 412         int addr = op->addr.val;
 413         unsigned int byte_count = op->data.nbytes;
 414
 415         if (hweight32(ICH_BOUNDARY) == 1) {
 416                 page_offset = addr & (ICH_BOUNDARY - 1);
 417         } else {
 418                 u64 aux = addr;
 419
 420                 page_offset = do_div(aux, ICH_BOUNDARY);
 421         }
 422
 423         if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) {
 424                 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
 425                                       slave->max_read_size);
 426         } else if (slave->max_write_size) {
 427                 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
 428                                       slave->max_write_size);
 429         }
 430
 431         op->data.nbytes = min(op->data.nbytes, byte_count);
 432
 433         return 0;
 434 }
 435
 436 static int ich_protect_lockdown(struct udevice *dev)
 437 {
 438         struct ich_spi_platdata *plat = dev_get_platdata(dev);
 439         struct ich_spi_priv *priv = dev_get_priv(dev);
 440         int ret = -ENOSYS;
 441
 442         /* Disable the BIOS write protect so write commands are allowed */
 443         if (priv->pch)
 444                 ret = pch_set_spi_protect(priv->pch, false);
 445         if (ret == -ENOSYS) {
 446                 u8 bios_cntl;
 447
 448                 bios_cntl = ich_readb(priv, priv->bcr);
 449                 bios_cntl &= ~BIT(5);   /* clear Enable InSMM_STS (EISS) */
 450                 bios_cntl |= 1;         /* Write Protect Disable (WPD) */
 451                 ich_writeb(priv, bios_cntl, priv->bcr);
 452         } else if (ret) {
 453                 debug("%s: Failed to disable write-protect: err=%d\n",
 454                       __func__, ret);
 455                 return ret;
 456         }
 457
 458         /* Lock down SPI controller settings if required */
 459         if (plat->lockdown) {
 460                 ich_spi_config_opcode(dev);
 461                 spi_lock_down(plat, priv->base);
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int ich_init_controller(struct udevice *dev,
 468                                struct ich_spi_platdata *plat,
 469                                struct ich_spi_priv *ctlr)
 470 {
 471         ulong sbase_addr;
 472         void *sbase;
 473
 474         /* SBASE is similar */
 475         pch_get_spi_base(dev->parent, &sbase_addr);
 476         sbase = (void *)sbase_addr;
 477         debug("%s: sbase=%p\n", __func__, sbase);
 478
 479         if (plat->ich_version == ICHV_7) {
 480                 struct ich7_spi_regs *ich7_spi = sbase;
 481
 482                 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
 483                 ctlr->menubytes = sizeof(ich7_spi->opmenu);
 484                 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
 485                 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
 486                 ctlr->data = offsetof(struct ich7_spi_regs, spid);
 487                 ctlr->databytes = sizeof(ich7_spi->spid);
 488                 ctlr->status = offsetof(struct ich7_spi_regs, spis);
 489                 ctlr->control = offsetof(struct ich7_spi_regs, spic);
 490                 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
 491                 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
 492                 ctlr->base = ich7_spi;
 493         } else if (plat->ich_version == ICHV_9) {
 494                 struct ich9_spi_regs *ich9_spi = sbase;
 495
 496                 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
 497                 ctlr->menubytes = sizeof(ich9_spi->opmenu);
 498                 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
 499                 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
 500                 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
 501                 ctlr->databytes = sizeof(ich9_spi->fdata);
 502                 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
 503                 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
 504                 ctlr->speed = ctlr->control + 2;
 505                 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
 506                 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
 507                 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
 508                 ctlr->pr = &ich9_spi->pr[0];
 509                 ctlr->base = ich9_spi;
 510         } else {
 511                 debug("ICH SPI: Unrecognised ICH version %d\n",
 512                       plat->ich_version);
 513                 return -EINVAL;
 514         }
 515
 516         /* Work out the maximum speed we can support */
 517         ctlr->max_speed = 20000000;
 518         if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
 519                 ctlr->max_speed = 33000000;
 520         debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
 521               plat->ich_version, ctlr->base, ctlr->max_speed);
 522
 523         ich_set_bbar(ctlr, 0);
 524
 525         return 0;
 526 }
 527
 528 static int ich_spi_probe(struct udevice *dev)
 529 {
 530         struct ich_spi_platdata *plat = dev_get_platdata(dev);
 531         struct ich_spi_priv *priv = dev_get_priv(dev);
 532         int ret;
 533
 534         ret = ich_init_controller(dev, plat, priv);
 535         if (ret)
 536                 return ret;
 537
 538         ret = ich_protect_lockdown(dev);
 539         if (ret)
 540                 return ret;
 541
 542         priv->cur_speed = priv->max_speed;
 543
 544         return 0;
 545 }
 546
 547 static int ich_spi_remove(struct udevice *bus)
 548 {
 549         /*
 550          * Configure SPI controller so that the Linux MTD driver can fully
 551          * access the SPI NOR chip
 552          */
 553         ich_spi_config_opcode(bus);
 554
 555         return 0;
 556 }
 557
 558 static int ich_spi_set_speed(struct udevice *bus, uint speed)
 559 {
 560         struct ich_spi_priv *priv = dev_get_priv(bus);
 561
 562         priv->cur_speed = speed;
 563
 564         return 0;
 565 }
 566
 567 static int ich_spi_set_mode(struct udevice *bus, uint mode)
 568 {
 569         debug("%s: mode=%d\n", __func__, mode);
 570
 571         return 0;
 572 }
 573
 574 static int ich_spi_child_pre_probe(struct udevice *dev)
 575 {
 576         struct udevice *bus = dev_get_parent(dev);
 577         struct ich_spi_platdata *plat = dev_get_platdata(bus);
 578         struct ich_spi_priv *priv = dev_get_priv(bus);
 579         struct spi_slave *slave = dev_get_parent_priv(dev);
 580
 581         /*
 582          * Yes this controller can only write a small number of bytes at
 583          * once! The limit is typically 64 bytes.
 584          */
 585         slave->max_write_size = priv->databytes;
 586         /*
 587          * ICH 7 SPI controller only supports array read command
 588          * and byte program command for SST flash
 589          */
 590         if (plat->ich_version == ICHV_7)
 591                 slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
 592
 593         return 0;
 594 }
 595
 596 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
 597 {
 598         struct ich_spi_platdata *plat = dev_get_platdata(dev);
 599         struct ich_spi_priv *priv = dev_get_priv(dev);
 600
 601         /* Find a PCH if there is one */
 602         uclass_first_device(UCLASS_PCH, &priv->pch);
 603         if (!priv->pch)
 604                 priv->pch = dev_get_parent(dev);
 605
 606         plat->ich_version = dev_get_driver_data(dev);
 607         plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
 608
 609         return 0;
 610 }
 611
 612 static const struct spi_controller_mem_ops ich_controller_mem_ops = {
 613         .adjust_op_size = ich_spi_adjust_size,
 614         .supports_op    = NULL,
 615         .exec_op        = ich_spi_exec_op,
 616 };
 617
 618 static const struct dm_spi_ops ich_spi_ops = {
 619         /* xfer is not supported */
 620         .set_speed      = ich_spi_set_speed,
 621         .set_mode       = ich_spi_set_mode,
 622         .mem_ops        = &ich_controller_mem_ops,
 623         /*
 624          * cs_info is not needed, since we require all chip selects to be
 625          * in the device tree explicitly
 626          */
 627 };
 628
 629 static const struct udevice_id ich_spi_ids[] = {
 630         { .compatible = "intel,ich7-spi", ICHV_7 },
 631         { .compatible = "intel,ich9-spi", ICHV_9 },
 632         { }
 633 };
 634
 635 U_BOOT_DRIVER(ich_spi) = {
 636         .name   = "ich_spi",
 637         .id     = UCLASS_SPI,
 638         .of_match = ich_spi_ids,
 639         .ops    = &ich_spi_ops,
 640         .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
 641         .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
 642         .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
 643         .child_pre_probe = ich_spi_child_pre_probe,
 644         .probe  = ich_spi_probe,
 645         .remove = ich_spi_remove,
 646         .flags  = DM_FLAG_OS_PREPARE,
 647 };