1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011-12 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
8 #define LOG_CATEGORY UCLASS_SPI
25 #define debug_trace(fmt, args...) debug(fmt, ##args)
27 #define debug_trace(x, args...)
30 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
32 u8 value = readb(priv->base + reg);
34 debug_trace("read %2.2x from %4.4x\n", value, reg);
39 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
41 u16 value = readw(priv->base + reg);
43 debug_trace("read %4.4x from %4.4x\n", value, reg);
48 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
50 u32 value = readl(priv->base + reg);
52 debug_trace("read %8.8x from %4.4x\n", value, reg);
57 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
59 writeb(value, priv->base + reg);
60 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
63 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
65 writew(value, priv->base + reg);
66 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
69 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
71 writel(value, priv->base + reg);
72 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
75 static void write_reg(struct ich_spi_priv *priv, const void *value,
76 int dest_reg, uint32_t size)
78 memcpy_toio(priv->base + dest_reg, value, size);
81 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
84 memcpy_fromio(value, priv->base + src_reg, size);
87 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
89 const uint32_t bbar_mask = 0x00ffff00;
93 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
94 ichspi_bbar |= minaddr;
95 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
98 /* @return 1 if the SPI flash supports the 33MHz speed */
99 static bool ich9_can_do_33mhz(struct udevice *dev)
101 struct ich_spi_priv *priv = dev_get_priv(dev);
104 /* Observe SPI Descriptor Component Section 0 */
105 dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
107 /* Extract the Write/Erase SPI Frequency from descriptor */
108 dm_pci_read_config32(priv->pch, 0xb4, &fdod);
110 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
111 speed = (fdod >> 21) & 7;
116 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
118 if (plat->ich_version == ICHV_7) {
119 struct ich7_spi_regs *ich7_spi = sbase;
121 setbits_le16(&ich7_spi->spis, SPIS_LOCK);
122 } else if (plat->ich_version == ICHV_9) {
123 struct ich9_spi_regs *ich9_spi = sbase;
125 setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
129 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
133 if (plat->ich_version == ICHV_7) {
134 struct ich7_spi_regs *ich7_spi = sbase;
136 lock = readw(&ich7_spi->spis) & SPIS_LOCK;
137 } else if (plat->ich_version == ICHV_9) {
138 struct ich9_spi_regs *ich9_spi = sbase;
140 lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
146 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
150 uint8_t opmenu[ctlr->menubytes];
153 /* The lock is off, so just use index 0. */
154 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
155 optypes = ich_readw(ctlr, ctlr->optype);
156 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
157 ich_writew(ctlr, optypes, ctlr->optype);
160 /* The lock is on. See if what we need is on the menu. */
162 uint16_t opcode_index;
164 /* Write Enable is handled as atomic prefix */
165 if (trans->opcode == SPI_OPCODE_WREN)
168 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
169 for (opcode_index = 0; opcode_index < ctlr->menubytes;
171 if (opmenu[opcode_index] == trans->opcode)
175 if (opcode_index == ctlr->menubytes) {
176 debug("ICH SPI: Opcode %x not found\n", trans->opcode);
180 optypes = ich_readw(ctlr, ctlr->optype);
181 optype = (optypes >> (opcode_index * 2)) & 0x3;
183 if (optype != trans->type) {
184 debug("ICH SPI: Transaction doesn't fit type %d\n",
193 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
194 * below is true) or 0. In case the wait was for the bit(s) to set - write
195 * those bits back, which would cause resetting them.
197 * Return the last read status value on success or -1 on failure.
199 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
202 int timeout = 600000; /* This will result in 6s */
206 status = ich_readw(ctlr, ctlr->status);
207 if (wait_til_set ^ ((status & bitmask) == 0)) {
209 ich_writew(ctlr, status & bitmask,
216 debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n",
217 status, bitmask, wait_til_set, status & bitmask);
222 static void ich_spi_config_opcode(struct udevice *dev)
224 struct ich_spi_priv *ctlr = dev_get_priv(dev);
227 * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
228 * to prevent accidental or intentional writes. Before they get
229 * locked down, these registers should be initialized properly.
231 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
232 ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
233 ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
234 ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
237 static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
239 struct udevice *bus = dev_get_parent(slave->dev);
240 struct ich_spi_platdata *plat = dev_get_platdata(bus);
241 struct ich_spi_priv *ctlr = dev_get_priv(bus);
243 int16_t opcode_index;
246 struct spi_trans *trans = &ctlr->trans;
247 bool lock = spi_lock_status(plat, ctlr->base);
254 if (op->data.nbytes) {
255 if (op->data.dir == SPI_MEM_DATA_IN) {
256 trans->in = op->data.buf.in;
257 trans->bytesin = op->data.nbytes;
259 trans->out = op->data.buf.out;
260 trans->bytesout = op->data.nbytes;
264 if (trans->opcode != op->cmd.opcode)
265 trans->opcode = op->cmd.opcode;
267 if (lock && trans->opcode == SPI_OPCODE_WRDIS)
270 if (trans->opcode == SPI_OPCODE_WREN) {
272 * Treat Write Enable as Atomic Pre-Op if possible
273 * in order to prevent the Management Engine from
274 * issuing a transaction between WREN and DATA.
277 ich_writew(ctlr, trans->opcode, ctlr->preop);
281 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
285 if (plat->ich_version == ICHV_7)
286 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
288 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
290 /* Try to guess spi transaction type */
291 if (op->data.dir == SPI_MEM_DATA_OUT) {
293 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
295 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
298 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
300 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
302 /* Special erase case handling */
303 if (op->addr.nbytes && !op->data.buswidth)
304 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
306 opcode_index = spi_setup_opcode(ctlr, trans, lock);
307 if (opcode_index < 0)
310 if (op->addr.nbytes) {
311 trans->offset = op->addr.val;
315 if (ctlr->speed && ctlr->max_speed >= 33000000) {
318 byte = ich_readb(ctlr, ctlr->speed);
319 if (ctlr->cur_speed >= 33000000)
320 byte |= SSFC_SCF_33MHZ;
322 byte &= ~SSFC_SCF_33MHZ;
323 ich_writeb(ctlr, byte, ctlr->speed);
326 /* Preset control fields */
327 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
329 /* Issue atomic preop cycle if needed */
330 if (ich_readw(ctlr, ctlr->preop))
333 if (!trans->bytesout && !trans->bytesin) {
334 /* SPI addresses are 24 bit only */
336 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
340 * This is a 'no data' command (like Write Enable), its
341 * bitesout size was 1, decremented to zero while executing
342 * spi_setup_opcode() above. Tell the chip to send the
345 ich_writew(ctlr, control, ctlr->control);
347 /* wait for the result */
348 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
352 if (status & SPIS_FCERR) {
353 debug("ICH SPI: Command transaction error\n");
360 while (trans->bytesout || trans->bytesin) {
361 uint32_t data_length;
363 /* SPI addresses are 24 bit only */
364 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
367 data_length = min(trans->bytesout, ctlr->databytes);
369 data_length = min(trans->bytesin, ctlr->databytes);
371 /* Program data into FDATA0 to N */
372 if (trans->bytesout) {
373 write_reg(ctlr, trans->out, ctlr->data, data_length);
374 trans->bytesout -= data_length;
377 /* Add proper control fields' values */
378 control &= ~((ctlr->databytes - 1) << 8);
380 control |= (data_length - 1) << 8;
383 ich_writew(ctlr, control, ctlr->control);
385 /* Wait for Cycle Done Status or Flash Cycle Error */
386 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
390 if (status & SPIS_FCERR) {
391 debug("ICH SPI: Data transaction error %x\n", status);
395 if (trans->bytesin) {
396 read_reg(ctlr, ctlr->data, trans->in, data_length);
397 trans->bytesin -= data_length;
401 /* Clear atomic preop now that xfer is done */
403 ich_writew(ctlr, 0, ctlr->preop);
408 static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
410 unsigned int page_offset;
411 int addr = op->addr.val;
412 unsigned int byte_count = op->data.nbytes;
414 if (hweight32(ICH_BOUNDARY) == 1) {
415 page_offset = addr & (ICH_BOUNDARY - 1);
419 page_offset = do_div(aux, ICH_BOUNDARY);
422 if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) {
423 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
424 slave->max_read_size);
425 } else if (slave->max_write_size) {
426 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
427 slave->max_write_size);
430 op->data.nbytes = min(op->data.nbytes, byte_count);
435 static int ich_protect_lockdown(struct udevice *dev)
437 struct ich_spi_platdata *plat = dev_get_platdata(dev);
438 struct ich_spi_priv *priv = dev_get_priv(dev);
441 /* Disable the BIOS write protect so write commands are allowed */
443 ret = pch_set_spi_protect(priv->pch, false);
444 if (ret == -ENOSYS) {
447 bios_cntl = ich_readb(priv, priv->bcr);
448 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
449 bios_cntl |= 1; /* Write Protect Disable (WPD) */
450 ich_writeb(priv, bios_cntl, priv->bcr);
452 debug("%s: Failed to disable write-protect: err=%d\n",
457 /* Lock down SPI controller settings if required */
458 if (plat->lockdown) {
459 ich_spi_config_opcode(dev);
460 spi_lock_down(plat, priv->base);
466 static int ich_init_controller(struct udevice *dev,
467 struct ich_spi_platdata *plat,
468 struct ich_spi_priv *ctlr)
473 /* SBASE is similar */
474 pch_get_spi_base(dev->parent, &sbase_addr);
475 sbase = (void *)sbase_addr;
476 debug("%s: sbase=%p\n", __func__, sbase);
478 if (plat->ich_version == ICHV_7) {
479 struct ich7_spi_regs *ich7_spi = sbase;
481 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
482 ctlr->menubytes = sizeof(ich7_spi->opmenu);
483 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
484 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
485 ctlr->data = offsetof(struct ich7_spi_regs, spid);
486 ctlr->databytes = sizeof(ich7_spi->spid);
487 ctlr->status = offsetof(struct ich7_spi_regs, spis);
488 ctlr->control = offsetof(struct ich7_spi_regs, spic);
489 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
490 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
491 ctlr->base = ich7_spi;
492 } else if (plat->ich_version == ICHV_9) {
493 struct ich9_spi_regs *ich9_spi = sbase;
495 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
496 ctlr->menubytes = sizeof(ich9_spi->opmenu);
497 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
498 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
499 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
500 ctlr->databytes = sizeof(ich9_spi->fdata);
501 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
502 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
503 ctlr->speed = ctlr->control + 2;
504 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
505 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
506 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
507 ctlr->pr = &ich9_spi->pr[0];
508 ctlr->base = ich9_spi;
510 debug("ICH SPI: Unrecognised ICH version %d\n",
515 /* Work out the maximum speed we can support */
516 ctlr->max_speed = 20000000;
517 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
518 ctlr->max_speed = 33000000;
519 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
520 plat->ich_version, ctlr->base, ctlr->max_speed);
522 ich_set_bbar(ctlr, 0);
527 static int ich_spi_probe(struct udevice *dev)
529 struct ich_spi_platdata *plat = dev_get_platdata(dev);
530 struct ich_spi_priv *priv = dev_get_priv(dev);
533 ret = ich_init_controller(dev, plat, priv);
537 ret = ich_protect_lockdown(dev);
541 priv->cur_speed = priv->max_speed;
546 static int ich_spi_remove(struct udevice *bus)
549 * Configure SPI controller so that the Linux MTD driver can fully
550 * access the SPI NOR chip
552 ich_spi_config_opcode(bus);
557 static int ich_spi_set_speed(struct udevice *bus, uint speed)
559 struct ich_spi_priv *priv = dev_get_priv(bus);
561 priv->cur_speed = speed;
566 static int ich_spi_set_mode(struct udevice *bus, uint mode)
568 debug("%s: mode=%d\n", __func__, mode);
573 static int ich_spi_child_pre_probe(struct udevice *dev)
575 struct udevice *bus = dev_get_parent(dev);
576 struct ich_spi_platdata *plat = dev_get_platdata(bus);
577 struct ich_spi_priv *priv = dev_get_priv(bus);
578 struct spi_slave *slave = dev_get_parent_priv(dev);
581 * Yes this controller can only write a small number of bytes at
582 * once! The limit is typically 64 bytes.
584 slave->max_write_size = priv->databytes;
586 * ICH 7 SPI controller only supports array read command
587 * and byte program command for SST flash
589 if (plat->ich_version == ICHV_7)
590 slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
595 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
597 struct ich_spi_platdata *plat = dev_get_platdata(dev);
598 struct ich_spi_priv *priv = dev_get_priv(dev);
600 /* Find a PCH if there is one */
601 uclass_first_device(UCLASS_PCH, &priv->pch);
603 priv->pch = dev_get_parent(dev);
605 plat->ich_version = dev_get_driver_data(dev);
606 plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
611 static const struct spi_controller_mem_ops ich_controller_mem_ops = {
612 .adjust_op_size = ich_spi_adjust_size,
614 .exec_op = ich_spi_exec_op,
617 static const struct dm_spi_ops ich_spi_ops = {
618 /* xfer is not supported */
619 .set_speed = ich_spi_set_speed,
620 .set_mode = ich_spi_set_mode,
621 .mem_ops = &ich_controller_mem_ops,
623 * cs_info is not needed, since we require all chip selects to be
624 * in the device tree explicitly
628 static const struct udevice_id ich_spi_ids[] = {
629 { .compatible = "intel,ich7-spi", ICHV_7 },
630 { .compatible = "intel,ich9-spi", ICHV_9 },
634 U_BOOT_DRIVER(ich_spi) = {
637 .of_match = ich_spi_ids,
639 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
640 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
641 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
642 .child_pre_probe = ich_spi_child_pre_probe,
643 .probe = ich_spi_probe,
644 .remove = ich_spi_remove,
645 .flags = DM_FLAG_OS_PREPARE,