1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011-12 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
22 DECLARE_GLOBAL_DATA_PTR;
25 #define debug_trace(fmt, args...) debug(fmt, ##args)
27 #define debug_trace(x, args...)
30 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
32 u8 value = readb(priv->base + reg);
34 debug_trace("read %2.2x from %4.4x\n", value, reg);
39 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
41 u16 value = readw(priv->base + reg);
43 debug_trace("read %4.4x from %4.4x\n", value, reg);
48 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
50 u32 value = readl(priv->base + reg);
52 debug_trace("read %8.8x from %4.4x\n", value, reg);
57 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
59 writeb(value, priv->base + reg);
60 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
63 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
65 writew(value, priv->base + reg);
66 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
69 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
71 writel(value, priv->base + reg);
72 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
75 static void write_reg(struct ich_spi_priv *priv, const void *value,
76 int dest_reg, uint32_t size)
78 memcpy_toio(priv->base + dest_reg, value, size);
81 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
84 memcpy_fromio(value, priv->base + src_reg, size);
87 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
89 const uint32_t bbar_mask = 0x00ffff00;
93 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
94 ichspi_bbar |= minaddr;
95 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
98 /* @return 1 if the SPI flash supports the 33MHz speed */
99 static int ich9_can_do_33mhz(struct udevice *dev)
101 struct ich_spi_priv *priv = dev_get_priv(dev);
104 /* Observe SPI Descriptor Component Section 0 */
105 dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
107 /* Extract the Write/Erase SPI Frequency from descriptor */
108 dm_pci_read_config32(priv->pch, 0xb4, &fdod);
110 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
111 speed = (fdod >> 21) & 7;
116 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
118 if (plat->ich_version == ICHV_7) {
119 struct ich7_spi_regs *ich7_spi = sbase;
121 setbits_le16(&ich7_spi->spis, SPIS_LOCK);
122 } else if (plat->ich_version == ICHV_9) {
123 struct ich9_spi_regs *ich9_spi = sbase;
125 setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
129 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
133 if (plat->ich_version == ICHV_7) {
134 struct ich7_spi_regs *ich7_spi = sbase;
136 lock = readw(&ich7_spi->spis) & SPIS_LOCK;
137 } else if (plat->ich_version == ICHV_9) {
138 struct ich9_spi_regs *ich9_spi = sbase;
140 lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
146 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
150 uint8_t opmenu[ctlr->menubytes];
153 /* The lock is off, so just use index 0. */
154 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
155 optypes = ich_readw(ctlr, ctlr->optype);
156 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
157 ich_writew(ctlr, optypes, ctlr->optype);
160 /* The lock is on. See if what we need is on the menu. */
162 uint16_t opcode_index;
164 /* Write Enable is handled as atomic prefix */
165 if (trans->opcode == SPI_OPCODE_WREN)
168 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
169 for (opcode_index = 0; opcode_index < ctlr->menubytes;
171 if (opmenu[opcode_index] == trans->opcode)
175 if (opcode_index == ctlr->menubytes) {
176 printf("ICH SPI: Opcode %x not found\n",
181 optypes = ich_readw(ctlr, ctlr->optype);
182 optype = (optypes >> (opcode_index * 2)) & 0x3;
184 if (optype != trans->type) {
185 printf("ICH SPI: Transaction doesn't fit type %d\n",
194 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
195 * below is true) or 0. In case the wait was for the bit(s) to set - write
196 * those bits back, which would cause resetting them.
198 * Return the last read status value on success or -1 on failure.
200 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
203 int timeout = 600000; /* This will result in 6s */
207 status = ich_readw(ctlr, ctlr->status);
208 if (wait_til_set ^ ((status & bitmask) == 0)) {
210 ich_writew(ctlr, status & bitmask,
218 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
223 static void ich_spi_config_opcode(struct udevice *dev)
225 struct ich_spi_priv *ctlr = dev_get_priv(dev);
228 * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
229 * to prevent accidental or intentional writes. Before they get
230 * locked down, these registers should be initialized properly.
232 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
233 ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
234 ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
235 ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
238 static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
240 struct udevice *bus = dev_get_parent(slave->dev);
241 struct ich_spi_platdata *plat = dev_get_platdata(bus);
242 struct ich_spi_priv *ctlr = dev_get_priv(bus);
244 int16_t opcode_index;
247 struct spi_trans *trans = &ctlr->trans;
248 bool lock = spi_lock_status(plat, ctlr->base);
255 if (op->data.nbytes) {
256 if (op->data.dir == SPI_MEM_DATA_IN) {
257 trans->in = op->data.buf.in;
258 trans->bytesin = op->data.nbytes;
260 trans->out = op->data.buf.out;
261 trans->bytesout = op->data.nbytes;
265 if (trans->opcode != op->cmd.opcode)
266 trans->opcode = op->cmd.opcode;
268 if (lock && trans->opcode == SPI_OPCODE_WRDIS)
271 if (trans->opcode == SPI_OPCODE_WREN) {
273 * Treat Write Enable as Atomic Pre-Op if possible
274 * in order to prevent the Management Engine from
275 * issuing a transaction between WREN and DATA.
278 ich_writew(ctlr, trans->opcode, ctlr->preop);
282 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
286 if (plat->ich_version == ICHV_7)
287 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
289 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
291 /* Try to guess spi transaction type */
292 if (op->data.dir == SPI_MEM_DATA_OUT) {
294 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
296 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
299 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
301 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
303 /* Special erase case handling */
304 if (op->addr.nbytes && !op->data.buswidth)
305 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
307 opcode_index = spi_setup_opcode(ctlr, trans, lock);
308 if (opcode_index < 0)
311 if (op->addr.nbytes) {
312 trans->offset = op->addr.val;
316 if (ctlr->speed && ctlr->max_speed >= 33000000) {
319 byte = ich_readb(ctlr, ctlr->speed);
320 if (ctlr->cur_speed >= 33000000)
321 byte |= SSFC_SCF_33MHZ;
323 byte &= ~SSFC_SCF_33MHZ;
324 ich_writeb(ctlr, byte, ctlr->speed);
327 /* Preset control fields */
328 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
330 /* Issue atomic preop cycle if needed */
331 if (ich_readw(ctlr, ctlr->preop))
334 if (!trans->bytesout && !trans->bytesin) {
335 /* SPI addresses are 24 bit only */
337 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
341 * This is a 'no data' command (like Write Enable), its
342 * bitesout size was 1, decremented to zero while executing
343 * spi_setup_opcode() above. Tell the chip to send the
346 ich_writew(ctlr, control, ctlr->control);
348 /* wait for the result */
349 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
353 if (status & SPIS_FCERR) {
354 debug("ICH SPI: Command transaction error\n");
361 while (trans->bytesout || trans->bytesin) {
362 uint32_t data_length;
364 /* SPI addresses are 24 bit only */
365 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
368 data_length = min(trans->bytesout, ctlr->databytes);
370 data_length = min(trans->bytesin, ctlr->databytes);
372 /* Program data into FDATA0 to N */
373 if (trans->bytesout) {
374 write_reg(ctlr, trans->out, ctlr->data, data_length);
375 trans->bytesout -= data_length;
378 /* Add proper control fields' values */
379 control &= ~((ctlr->databytes - 1) << 8);
381 control |= (data_length - 1) << 8;
384 ich_writew(ctlr, control, ctlr->control);
386 /* Wait for Cycle Done Status or Flash Cycle Error */
387 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
391 if (status & SPIS_FCERR) {
392 debug("ICH SPI: Data transaction error %x\n", status);
396 if (trans->bytesin) {
397 read_reg(ctlr, ctlr->data, trans->in, data_length);
398 trans->bytesin -= data_length;
402 /* Clear atomic preop now that xfer is done */
404 ich_writew(ctlr, 0, ctlr->preop);
409 static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
411 unsigned int page_offset;
412 int addr = op->addr.val;
413 unsigned int byte_count = op->data.nbytes;
415 if (hweight32(ICH_BOUNDARY) == 1) {
416 page_offset = addr & (ICH_BOUNDARY - 1);
420 page_offset = do_div(aux, ICH_BOUNDARY);
423 if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) {
424 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
425 slave->max_read_size);
426 } else if (slave->max_write_size) {
427 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
428 slave->max_write_size);
431 op->data.nbytes = min(op->data.nbytes, byte_count);
436 static int ich_protect_lockdown(struct udevice *dev)
438 struct ich_spi_platdata *plat = dev_get_platdata(dev);
439 struct ich_spi_priv *priv = dev_get_priv(dev);
442 /* Disable the BIOS write protect so write commands are allowed */
444 ret = pch_set_spi_protect(priv->pch, false);
445 if (ret == -ENOSYS) {
448 bios_cntl = ich_readb(priv, priv->bcr);
449 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
450 bios_cntl |= 1; /* Write Protect Disable (WPD) */
451 ich_writeb(priv, bios_cntl, priv->bcr);
453 debug("%s: Failed to disable write-protect: err=%d\n",
458 /* Lock down SPI controller settings if required */
459 if (plat->lockdown) {
460 ich_spi_config_opcode(dev);
461 spi_lock_down(plat, priv->base);
467 static int ich_init_controller(struct udevice *dev,
468 struct ich_spi_platdata *plat,
469 struct ich_spi_priv *ctlr)
474 /* SBASE is similar */
475 pch_get_spi_base(dev->parent, &sbase_addr);
476 sbase = (void *)sbase_addr;
477 debug("%s: sbase=%p\n", __func__, sbase);
479 if (plat->ich_version == ICHV_7) {
480 struct ich7_spi_regs *ich7_spi = sbase;
482 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
483 ctlr->menubytes = sizeof(ich7_spi->opmenu);
484 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
485 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
486 ctlr->data = offsetof(struct ich7_spi_regs, spid);
487 ctlr->databytes = sizeof(ich7_spi->spid);
488 ctlr->status = offsetof(struct ich7_spi_regs, spis);
489 ctlr->control = offsetof(struct ich7_spi_regs, spic);
490 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
491 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
492 ctlr->base = ich7_spi;
493 } else if (plat->ich_version == ICHV_9) {
494 struct ich9_spi_regs *ich9_spi = sbase;
496 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
497 ctlr->menubytes = sizeof(ich9_spi->opmenu);
498 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
499 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
500 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
501 ctlr->databytes = sizeof(ich9_spi->fdata);
502 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
503 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
504 ctlr->speed = ctlr->control + 2;
505 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
506 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
507 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
508 ctlr->pr = &ich9_spi->pr[0];
509 ctlr->base = ich9_spi;
511 debug("ICH SPI: Unrecognised ICH version %d\n",
516 /* Work out the maximum speed we can support */
517 ctlr->max_speed = 20000000;
518 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
519 ctlr->max_speed = 33000000;
520 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
521 plat->ich_version, ctlr->base, ctlr->max_speed);
523 ich_set_bbar(ctlr, 0);
528 static int ich_spi_probe(struct udevice *dev)
530 struct ich_spi_platdata *plat = dev_get_platdata(dev);
531 struct ich_spi_priv *priv = dev_get_priv(dev);
534 ret = ich_init_controller(dev, plat, priv);
538 ret = ich_protect_lockdown(dev);
542 priv->cur_speed = priv->max_speed;
547 static int ich_spi_remove(struct udevice *bus)
550 * Configure SPI controller so that the Linux MTD driver can fully
551 * access the SPI NOR chip
553 ich_spi_config_opcode(bus);
558 static int ich_spi_set_speed(struct udevice *bus, uint speed)
560 struct ich_spi_priv *priv = dev_get_priv(bus);
562 priv->cur_speed = speed;
567 static int ich_spi_set_mode(struct udevice *bus, uint mode)
569 debug("%s: mode=%d\n", __func__, mode);
574 static int ich_spi_child_pre_probe(struct udevice *dev)
576 struct udevice *bus = dev_get_parent(dev);
577 struct ich_spi_platdata *plat = dev_get_platdata(bus);
578 struct ich_spi_priv *priv = dev_get_priv(bus);
579 struct spi_slave *slave = dev_get_parent_priv(dev);
582 * Yes this controller can only write a small number of bytes at
583 * once! The limit is typically 64 bytes.
585 slave->max_write_size = priv->databytes;
587 * ICH 7 SPI controller only supports array read command
588 * and byte program command for SST flash
590 if (plat->ich_version == ICHV_7)
591 slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
596 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
598 struct ich_spi_platdata *plat = dev_get_platdata(dev);
599 struct ich_spi_priv *priv = dev_get_priv(dev);
601 /* Find a PCH if there is one */
602 uclass_first_device(UCLASS_PCH, &priv->pch);
604 priv->pch = dev_get_parent(dev);
606 plat->ich_version = dev_get_driver_data(dev);
607 plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
612 static const struct spi_controller_mem_ops ich_controller_mem_ops = {
613 .adjust_op_size = ich_spi_adjust_size,
615 .exec_op = ich_spi_exec_op,
618 static const struct dm_spi_ops ich_spi_ops = {
619 /* xfer is not supported */
620 .set_speed = ich_spi_set_speed,
621 .set_mode = ich_spi_set_mode,
622 .mem_ops = &ich_controller_mem_ops,
624 * cs_info is not needed, since we require all chip selects to be
625 * in the device tree explicitly
629 static const struct udevice_id ich_spi_ids[] = {
630 { .compatible = "intel,ich7-spi", ICHV_7 },
631 { .compatible = "intel,ich9-spi", ICHV_9 },
635 U_BOOT_DRIVER(ich_spi) = {
638 .of_match = ich_spi_ids,
640 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
641 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
642 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
643 .child_pre_probe = ich_spi_child_pre_probe,
644 .probe = ich_spi_probe,
645 .remove = ich_spi_remove,
646 .flags = DM_FLAG_OS_PREPARE,