drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <linux/iopoll.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include <wait_bit.h>
  18 #include "fsl_qspi.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define RX_BUFFER_SIZE          0x80
  23 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
  24         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
  25 #define TX_BUFFER_SIZE          0x200
  26 #else
  27 #define TX_BUFFER_SIZE          0x40
  28 #endif
  29
  30 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  31
  32 #define FLASH_STATUS_WEL        0x02
  33
  34 /* SEQID */
  35 #define SEQID_WREN              1
  36 #define SEQID_FAST_READ         2
  37 #define SEQID_RDSR              3
  38 #define SEQID_SE                4
  39 #define SEQID_CHIP_ERASE        5
  40 #define SEQID_PP                6
  41 #define SEQID_RDID              7
  42 #define SEQID_BE_4K             8
  43 #ifdef CONFIG_SPI_FLASH_BAR
  44 #define SEQID_BRRD              9
  45 #define SEQID_BRWR              10
  46 #define SEQID_RDEAR             11
  47 #define SEQID_WREAR             12
  48 #endif
  49 #define SEQID_WRAR              13
  50 #define SEQID_RDAR              14
  51
  52 /* QSPI CMD */
  53 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  54 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  55 #define QSPI_CMD_WREN           0x06    /* Write enable */
  56 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  57 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  58 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  59 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  60 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  61
  62 /* Used for Micron, winbond and Macronix flashes */
  63 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  64 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  65
  66 /* Used for Spansion flashes only. */
  67 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  68 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  69
  70 /* Used for Spansion S25FS-S family flash only. */
  71 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  72 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  73
  74 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  75 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  76 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  77 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  78
  79 /* fsl_qspi_platdata flags */
  80 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  81
  82 /* default SCK frequency, unit: HZ */
  83 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  84
  85 /* QSPI max chipselect signals number */
  86 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  87
  88 /**
  89  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  90  *
  91  * @flags: Flags for QSPI QSPI_FLAG_...
  92  * @speed_hz: Default SCK frequency
  93  * @reg_base: Base address of QSPI registers
  94  * @amba_base: Base address of QSPI memory mapping
  95  * @amba_total_size: size of QSPI memory mapping
  96  * @flash_num: Number of active slave devices
  97  * @num_chipselect: Number of QSPI chipselect signals
  98  */
  99 struct fsl_qspi_platdata {
 100         u32 flags;
 101         u32 speed_hz;
 102         fdt_addr_t reg_base;
 103         fdt_addr_t amba_base;
 104         fdt_size_t amba_total_size;
 105         u32 flash_num;
 106         u32 num_chipselect;
 107 };
 108
 109 /**
 110  * struct fsl_qspi_priv - private data for Freescale QSPI
 111  *
 112  * @flags: Flags for QSPI QSPI_FLAG_...
 113  * @bus_clk: QSPI input clk frequency
 114  * @speed_hz: Default SCK frequency
 115  * @cur_seqid: current LUT table sequence id
 116  * @sf_addr: flash access offset
 117  * @amba_base: Base address of QSPI memory mapping of every CS
 118  * @amba_total_size: size of QSPI memory mapping
 119  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 120  * @flash_num: Number of active slave devices
 121  * @num_chipselect: Number of QSPI chipselect signals
 122  * @regs: Point to QSPI register structure for I/O access
 123  */
 124 struct fsl_qspi_priv {
 125         u32 flags;
 126         u32 bus_clk;
 127         u32 speed_hz;
 128         u32 cur_seqid;
 129         u32 sf_addr;
 130         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 131         u32 amba_total_size;
 132         u32 cur_amba_base;
 133         u32 flash_num;
 134         u32 num_chipselect;
 135         struct fsl_qspi_regs *regs;
 136 };
 137
 138
 139 static u32 qspi_read32(u32 flags, u32 *addr)
 140 {
 141         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 142                 in_be32(addr) : in_le32(addr);
 143 }
 144
 145 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 146 {
 147         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 148                 out_be32(addr, val) : out_le32(addr, val);
 149 }
 150
 151 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
 152 {
 153         u32 val;
 154         u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
 155                    QSPI_SR_IP_ACC_MASK;
 156
 157         if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
 158                 mask = (u32)cpu_to_be32(mask);
 159
 160         return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
 161 }
 162
 163 /* QSPI support swapping the flash read/write data
 164  * in hardware for LS102xA, but not for VF610 */
 165 static inline u32 qspi_endian_xchg(u32 data)
 166 {
 167 #ifdef CONFIG_VF610
 168         return swab32(data);
 169 #else
 170         return data;
 171 #endif
 172 }
 173
 174 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 175 {
 176         struct fsl_qspi_regs *regs = priv->regs;
 177         u32 lut_base;
 178
 179         /* Unlock the LUT */
 180         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 181         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 182
 183         /* Write Enable */
 184         lut_base = SEQID_WREN * 4;
 185         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 186                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 187         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 188         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 189         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 190
 191         /* Fast Read */
 192         lut_base = SEQID_FAST_READ * 4;
 193 #ifdef CONFIG_SPI_FLASH_BAR
 194         qspi_write32(priv->flags, &regs->lut[lut_base],
 195                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 196                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 197                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 198 #else
 199         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 200                 qspi_write32(priv->flags, &regs->lut[lut_base],
 201                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 202                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 203                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 204         else
 205                 qspi_write32(priv->flags, &regs->lut[lut_base],
 206                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 207                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 208                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 209                              INSTR1(LUT_ADDR));
 210 #endif
 211         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 212                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 213                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 214                      INSTR1(LUT_READ));
 215         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 216         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 217
 218         /* Read Status */
 219         lut_base = SEQID_RDSR * 4;
 220         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 221                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 222                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 223         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 224         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 225         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 226
 227         /* Erase a sector */
 228         lut_base = SEQID_SE * 4;
 229 #ifdef CONFIG_SPI_FLASH_BAR
 230         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 231                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 232                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 233 #else
 234         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 235                 qspi_write32(priv->flags, &regs->lut[lut_base],
 236                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 237                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 238                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 239         else
 240                 qspi_write32(priv->flags, &regs->lut[lut_base],
 241                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 242                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 243                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 244 #endif
 245         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 246         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 247         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 248
 249         /* Erase the whole chip */
 250         lut_base = SEQID_CHIP_ERASE * 4;
 251         qspi_write32(priv->flags, &regs->lut[lut_base],
 252                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 253                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 254         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 255         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 256         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 257
 258         /* Page Program */
 259         lut_base = SEQID_PP * 4;
 260 #ifdef CONFIG_SPI_FLASH_BAR
 261         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 262                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 263                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 264 #else
 265         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 266                 qspi_write32(priv->flags, &regs->lut[lut_base],
 267                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 268                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 269                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 270         else
 271                 qspi_write32(priv->flags, &regs->lut[lut_base],
 272                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 273                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 274                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 275 #endif
 276 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
 277         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
 278         /*
 279          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 280          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 281          */
 282         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 283                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 284 #else
 285         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 286                      OPRND0(TX_BUFFER_SIZE) |
 287                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 288 #endif
 289         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 290         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 291
 292         /* READ ID */
 293         lut_base = SEQID_RDID * 4;
 294         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 295                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 296                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 297         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 298         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 299         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 300
 301         /* SUB SECTOR 4K ERASE */
 302         lut_base = SEQID_BE_4K * 4;
 303         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 304                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 305                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 306
 307 #ifdef CONFIG_SPI_FLASH_BAR
 308         /*
 309          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 310          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 311          * initialization.
 312          */
 313         lut_base = SEQID_BRRD * 4;
 314         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 315                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 316                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 317
 318         lut_base = SEQID_BRWR * 4;
 319         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 320                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 321                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 322
 323         lut_base = SEQID_RDEAR * 4;
 324         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 325                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 326                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 327
 328         lut_base = SEQID_WREAR * 4;
 329         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 330                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 331                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 332 #endif
 333
 334         /*
 335          * Read any device register.
 336          * Used for Spansion S25FS-S family flash only.
 337          */
 338         lut_base = SEQID_RDAR * 4;
 339         qspi_write32(priv->flags, &regs->lut[lut_base],
 340                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 341                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 342                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 343         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 344                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 345                      OPRND1(1) | PAD1(LUT_PAD1) |
 346                      INSTR1(LUT_READ));
 347
 348         /*
 349          * Write any device register.
 350          * Used for Spansion S25FS-S family flash only.
 351          */
 352         lut_base = SEQID_WRAR * 4;
 353         qspi_write32(priv->flags, &regs->lut[lut_base],
 354                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 355                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 356                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 357         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 358                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 359
 360         /* Lock the LUT */
 361         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 362         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 363 }
 364
 365 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 366 /*
 367  * If we have changed the content of the flash by writing or erasing,
 368  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 369  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 370  * domain at the same time.
 371  */
 372 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 373 {
 374         struct fsl_qspi_regs *regs = priv->regs;
 375         u32 reg;
 376
 377         reg = qspi_read32(priv->flags, &regs->mcr);
 378         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 379         qspi_write32(priv->flags, &regs->mcr, reg);
 380
 381         /*
 382          * The minimum delay : 1 AHB + 2 SFCK clocks.
 383          * Delay 1 us is enough.
 384          */
 385         udelay(1);
 386
 387         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 388         qspi_write32(priv->flags, &regs->mcr, reg);
 389 }
 390
 391 /* Read out the data from the AHB buffer. */
 392 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 393 {
 394         struct fsl_qspi_regs *regs = priv->regs;
 395         u32 mcr_reg;
 396         void *rx_addr;
 397
 398         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 399
 400         qspi_write32(priv->flags, &regs->mcr,
 401                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 402                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 403
 404         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 405         /* Read out the data directly from the AHB buffer. */
 406         memcpy(rxbuf, rx_addr, len);
 407
 408         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 409 }
 410
 411 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 412 {
 413         u32 reg, reg2;
 414         struct fsl_qspi_regs *regs = priv->regs;
 415
 416         reg = qspi_read32(priv->flags, &regs->mcr);
 417         /* Disable the module */
 418         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 419
 420         /* Set the Sampling Register for DDR */
 421         reg2 = qspi_read32(priv->flags, &regs->smpr);
 422         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 423         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 424         qspi_write32(priv->flags, &regs->smpr, reg2);
 425
 426         /* Enable the module again (enable the DDR too) */
 427         reg |= QSPI_MCR_DDR_EN_MASK;
 428         /* Enable bit 29 for imx6sx */
 429         reg |= BIT(29);
 430
 431         qspi_write32(priv->flags, &regs->mcr, reg);
 432 }
 433
 434 /*
 435  * There are two different ways to read out the data from the flash:
 436  *  the "IP Command Read" and the "AHB Command Read".
 437  *
 438  * The IC guy suggests we use the "AHB Command Read" which is faster
 439  * then the "IP Command Read". (What's more is that there is a bug in
 440  * the "IP Command Read" in the Vybrid.)
 441  *
 442  * After we set up the registers for the "AHB Command Read", we can use
 443  * the memcpy to read the data directly. A "missed" access to the buffer
 444  * causes the controller to clear the buffer, and use the sequence pointed
 445  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 446  */
 447 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 448 {
 449         struct fsl_qspi_regs *regs = priv->regs;
 450
 451         /* AHB configuration for access buffer 0/1/2 .*/
 452         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 453         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 454         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 455         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 456                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 457
 458         /* We only use the buffer3 */
 459         qspi_write32(priv->flags, &regs->buf0ind, 0);
 460         qspi_write32(priv->flags, &regs->buf1ind, 0);
 461         qspi_write32(priv->flags, &regs->buf2ind, 0);
 462
 463         /*
 464          * Set the default lut sequence for AHB Read.
 465          * Parallel mode is disabled.
 466          */
 467         qspi_write32(priv->flags, &regs->bfgencr,
 468                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 469
 470         /*Enable DDR Mode*/
 471         qspi_enable_ddr_mode(priv);
 472 }
 473 #endif
 474
 475 #ifdef CONFIG_SPI_FLASH_BAR
 476 /* Bank register read/write, EAR register read/write */
 477 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 478 {
 479         struct fsl_qspi_regs *regs = priv->regs;
 480         u32 reg, mcr_reg, data, seqid;
 481
 482         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 483         qspi_write32(priv->flags, &regs->mcr,
 484                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 485                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 486         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 487
 488         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 489
 490         if (priv->cur_seqid == QSPI_CMD_BRRD)
 491                 seqid = SEQID_BRRD;
 492         else
 493                 seqid = SEQID_RDEAR;
 494
 495         qspi_write32(priv->flags, &regs->ipcr,
 496                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 497
 498         /* Wait previous command complete */
 499         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 500                 ;
 501
 502         while (1) {
 503                 WATCHDOG_RESET();
 504
 505                 reg = qspi_read32(priv->flags, &regs->rbsr);
 506                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 507                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 508                         data = qspi_endian_xchg(data);
 509                         memcpy(rxbuf, &data, len);
 510                         qspi_write32(priv->flags, &regs->mcr,
 511                                      qspi_read32(priv->flags, &regs->mcr) |
 512                                      QSPI_MCR_CLR_RXF_MASK);
 513                         break;
 514                 }
 515         }
 516
 517         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 518 }
 519 #endif
 520
 521 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 522 {
 523         struct fsl_qspi_regs *regs = priv->regs;
 524         u32 mcr_reg, rbsr_reg, data, size;
 525         int i;
 526
 527         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 528         qspi_write32(priv->flags, &regs->mcr,
 529                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 530                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 531         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 532
 533         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 534
 535         qspi_write32(priv->flags, &regs->ipcr,
 536                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 537         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 538                 ;
 539
 540         i = 0;
 541         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 542                 WATCHDOG_RESET();
 543
 544                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 545                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 546                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 547                         data = qspi_endian_xchg(data);
 548                         size = (len < 4) ? len : 4;
 549                         memcpy(rxbuf, &data, size);
 550                         len -= size;
 551                         rxbuf++;
 552                         i++;
 553                 }
 554         }
 555
 556         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 557 }
 558
 559 /* If not use AHB read, read data from ip interface */
 560 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 561 {
 562         struct fsl_qspi_regs *regs = priv->regs;
 563         u32 mcr_reg, data;
 564         int i, size;
 565         u32 to_or_from;
 566         u32 seqid;
 567
 568         if (priv->cur_seqid == QSPI_CMD_RDAR)
 569                 seqid = SEQID_RDAR;
 570         else
 571                 seqid = SEQID_FAST_READ;
 572
 573         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 574         qspi_write32(priv->flags, &regs->mcr,
 575                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 576                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 577         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 578
 579         to_or_from = priv->sf_addr + priv->cur_amba_base;
 580
 581         while (len > 0) {
 582                 WATCHDOG_RESET();
 583
 584                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 585
 586                 size = (len > RX_BUFFER_SIZE) ?
 587                         RX_BUFFER_SIZE : len;
 588
 589                 qspi_write32(priv->flags, &regs->ipcr,
 590                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 591                              size);
 592                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 593                         ;
 594
 595                 to_or_from += size;
 596                 len -= size;
 597
 598                 i = 0;
 599                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 600                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 601                         data = qspi_endian_xchg(data);
 602                         if (size < 4)
 603                                 memcpy(rxbuf, &data, size);
 604                         else
 605                                 memcpy(rxbuf, &data, 4);
 606                         rxbuf++;
 607                         size -= 4;
 608                         i++;
 609                 }
 610                 qspi_write32(priv->flags, &regs->mcr,
 611                              qspi_read32(priv->flags, &regs->mcr) |
 612                              QSPI_MCR_CLR_RXF_MASK);
 613         }
 614
 615         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 616 }
 617
 618 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 619 {
 620         struct fsl_qspi_regs *regs = priv->regs;
 621         u32 mcr_reg, data, reg, status_reg, seqid;
 622         int i, size, tx_size;
 623         u32 to_or_from = 0;
 624
 625         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 626         qspi_write32(priv->flags, &regs->mcr,
 627                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 628                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 629         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 630
 631         status_reg = 0;
 632         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 633                 WATCHDOG_RESET();
 634
 635                 qspi_write32(priv->flags, &regs->ipcr,
 636                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 637                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 638                         ;
 639
 640                 qspi_write32(priv->flags, &regs->ipcr,
 641                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 642                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 643                         ;
 644
 645                 reg = qspi_read32(priv->flags, &regs->rbsr);
 646                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 647                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 648                         status_reg = qspi_endian_xchg(status_reg);
 649                 }
 650                 qspi_write32(priv->flags, &regs->mcr,
 651                              qspi_read32(priv->flags, &regs->mcr) |
 652                              QSPI_MCR_CLR_RXF_MASK);
 653         }
 654
 655         /* Default is page programming */
 656         seqid = SEQID_PP;
 657         if (priv->cur_seqid == QSPI_CMD_WRAR)
 658                 seqid = SEQID_WRAR;
 659 #ifdef CONFIG_SPI_FLASH_BAR
 660         if (priv->cur_seqid == QSPI_CMD_BRWR)
 661                 seqid = SEQID_BRWR;
 662         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 663                 seqid = SEQID_WREAR;
 664 #endif
 665
 666         to_or_from = priv->sf_addr + priv->cur_amba_base;
 667
 668         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 669
 670         tx_size = (len > TX_BUFFER_SIZE) ?
 671                 TX_BUFFER_SIZE : len;
 672
 673         size = tx_size / 16;
 674         /*
 675          * There must be atleast 128bit data
 676          * available in TX FIFO for any pop operation
 677          */
 678         if (tx_size % 16)
 679                 size++;
 680         for (i = 0; i < size * 4; i++) {
 681                 memcpy(&data, txbuf, 4);
 682                 data = qspi_endian_xchg(data);
 683                 qspi_write32(priv->flags, &regs->tbdr, data);
 684                 txbuf += 4;
 685         }
 686
 687         qspi_write32(priv->flags, &regs->ipcr,
 688                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 689         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 690                 ;
 691
 692         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 693 }
 694
 695 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 696 {
 697         struct fsl_qspi_regs *regs = priv->regs;
 698         u32 mcr_reg, reg, data;
 699
 700         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 701         qspi_write32(priv->flags, &regs->mcr,
 702                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 703                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 704         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 705
 706         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 707
 708         qspi_write32(priv->flags, &regs->ipcr,
 709                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 710         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 711                 ;
 712
 713         while (1) {
 714                 WATCHDOG_RESET();
 715
 716                 reg = qspi_read32(priv->flags, &regs->rbsr);
 717                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 718                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 719                         data = qspi_endian_xchg(data);
 720                         memcpy(rxbuf, &data, len);
 721                         qspi_write32(priv->flags, &regs->mcr,
 722                                      qspi_read32(priv->flags, &regs->mcr) |
 723                                      QSPI_MCR_CLR_RXF_MASK);
 724                         break;
 725                 }
 726         }
 727
 728         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 729 }
 730
 731 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 732 {
 733         struct fsl_qspi_regs *regs = priv->regs;
 734         u32 mcr_reg;
 735         u32 to_or_from = 0;
 736
 737         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 738         qspi_write32(priv->flags, &regs->mcr,
 739                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 740                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 741         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 742
 743         to_or_from = priv->sf_addr + priv->cur_amba_base;
 744         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 745
 746         qspi_write32(priv->flags, &regs->ipcr,
 747                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 748         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 749                 ;
 750
 751         if (priv->cur_seqid == QSPI_CMD_SE) {
 752                 qspi_write32(priv->flags, &regs->ipcr,
 753                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 754         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 755                 qspi_write32(priv->flags, &regs->ipcr,
 756                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 757         }
 758         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 759                 ;
 760
 761         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 762 }
 763
 764 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 765                 const void *dout, void *din, unsigned long flags)
 766 {
 767         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 768         static u32 wr_sfaddr;
 769         u32 txbuf;
 770
 771         WATCHDOG_RESET();
 772
 773         if (dout) {
 774                 if (flags & SPI_XFER_BEGIN) {
 775                         priv->cur_seqid = *(u8 *)dout;
 776                         memcpy(&txbuf, dout, 4);
 777                 }
 778
 779                 if (flags == SPI_XFER_END) {
 780                         priv->sf_addr = wr_sfaddr;
 781                         qspi_op_write(priv, (u8 *)dout, bytes);
 782                         return 0;
 783                 }
 784
 785                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 786                     priv->cur_seqid == QSPI_CMD_RDAR) {
 787                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 788                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 789                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 790                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 791                         qspi_op_erase(priv);
 792                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 793                            priv->cur_seqid == QSPI_CMD_WRAR) {
 794                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 795                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 796                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 797 #ifdef CONFIG_SPI_FLASH_BAR
 798                         wr_sfaddr = 0;
 799 #endif
 800                 }
 801         }
 802
 803         if (din) {
 804                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 805 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 806                         qspi_ahb_read(priv, din, bytes);
 807 #else
 808                         qspi_op_read(priv, din, bytes);
 809 #endif
 810                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 811                         qspi_op_read(priv, din, bytes);
 812                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 813                         qspi_op_rdid(priv, din, bytes);
 814                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 815                         qspi_op_rdsr(priv, din, bytes);
 816 #ifdef CONFIG_SPI_FLASH_BAR
 817                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 818                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 819                         priv->sf_addr = 0;
 820                         qspi_op_rdbank(priv, din, bytes);
 821                 }
 822 #endif
 823         }
 824
 825 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 826         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 827             (priv->cur_seqid == QSPI_CMD_PP) ||
 828             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 829             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 830             (priv->cur_seqid == QSPI_CMD_BRWR))
 831                 qspi_ahb_invalid(priv);
 832 #endif
 833
 834         return 0;
 835 }
 836
 837 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 838 {
 839         u32 mcr_val;
 840
 841         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 842         if (disable)
 843                 mcr_val |= QSPI_MCR_MDIS_MASK;
 844         else
 845                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 846         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 847 }
 848
 849 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 850 {
 851         u32 smpr_val;
 852
 853         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 854         smpr_val &= ~clear_bits;
 855         smpr_val |= set_bits;
 856         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 857 }
 858
 859 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 860 {
 861         struct spi_slave *slave = dev_get_parent_priv(dev);
 862
 863         slave->max_write_size = TX_BUFFER_SIZE;
 864
 865         return 0;
 866 }
 867
 868 static int fsl_qspi_probe(struct udevice *bus)
 869 {
 870         u32 mcr_val;
 871         u32 amba_size_per_chip;
 872         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 873         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 874         struct dm_spi_bus *dm_spi_bus;
 875         int i, ret;
 876
 877         dm_spi_bus = bus->uclass_priv;
 878
 879         dm_spi_bus->max_hz = plat->speed_hz;
 880
 881         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 882         priv->flags = plat->flags;
 883
 884         priv->speed_hz = plat->speed_hz;
 885         /*
 886          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 887          * AMBA memory zone should be located on the 0~4GB space
 888          * even on a 64bits cpu.
 889          */
 890         priv->amba_base[0] = (u32)plat->amba_base;
 891         priv->amba_total_size = (u32)plat->amba_total_size;
 892         priv->flash_num = plat->flash_num;
 893         priv->num_chipselect = plat->num_chipselect;
 894
 895         /* make sure controller is not busy anywhere */
 896         ret = is_controller_busy(priv);
 897
 898         if (ret) {
 899                 debug("ERROR : The controller is busy\n");
 900                 return ret;
 901         }
 902
 903         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 904
 905         /* Set endianness to LE for i.mx */
 906         if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
 907                 mcr_val = QSPI_MCR_END_CFD_LE;
 908
 909         qspi_write32(priv->flags, &priv->regs->mcr,
 910                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 911                      (mcr_val & QSPI_MCR_END_CFD_MASK));
 912
 913         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 914                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 915
 916         /*
 917          * Assign AMBA memory zone for every chipselect
 918          * QuadSPI has two channels, every channel has two chipselects.
 919          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
 920          * into two parts and assign to every channel. This indicate that every
 921          * channel only has one valid chipselect.
 922          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
 923          * into four parts and assign to every chipselect.
 924          * Every channel will has two valid chipselects.
 925          */
 926         amba_size_per_chip = priv->amba_total_size >>
 927                              (priv->num_chipselect >> 1);
 928         for (i = 1 ; i < priv->num_chipselect ; i++)
 929                 priv->amba_base[i] =
 930                         amba_size_per_chip + priv->amba_base[i - 1];
 931
 932         /*
 933          * Any read access to non-implemented addresses will provide
 934          * undefined results.
 935          *
 936          * In case single die flash devices, TOP_ADDR_MEMA2 and
 937          * TOP_ADDR_MEMB2 should be initialized/programmed to
 938          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 939          * setting the size of these devices to 0.  This would ensure
 940          * that the complete memory map is assigned to only one flash device.
 941          */
 942         qspi_write32(priv->flags, &priv->regs->sfa1ad,
 943                      priv->amba_base[0] + amba_size_per_chip);
 944         switch (priv->num_chipselect) {
 945         case 1:
 946                 break;
 947         case 2:
 948                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 949                              priv->amba_base[1]);
 950                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 951                              priv->amba_base[1] + amba_size_per_chip);
 952                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 953                              priv->amba_base[1] + amba_size_per_chip);
 954                 break;
 955         case 4:
 956                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 957                              priv->amba_base[2]);
 958                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 959                              priv->amba_base[3]);
 960                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 961                              priv->amba_base[3] + amba_size_per_chip);
 962                 break;
 963         default:
 964                 debug("Error: Unsupported chipselect number %u!\n",
 965                       priv->num_chipselect);
 966                 qspi_module_disable(priv, 1);
 967                 return -EINVAL;
 968         }
 969
 970         qspi_set_lut(priv);
 971
 972 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 973         qspi_init_ahb_read(priv);
 974 #endif
 975
 976         qspi_module_disable(priv, 0);
 977
 978         return 0;
 979 }
 980
 981 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 982 {
 983         struct fdt_resource res_regs, res_mem;
 984         struct fsl_qspi_platdata *plat = bus->platdata;
 985         const void *blob = gd->fdt_blob;
 986         int node = dev_of_offset(bus);
 987         int ret, flash_num = 0, subnode;
 988
 989         if (fdtdec_get_bool(blob, node, "big-endian"))
 990                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 991
 992         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 993                                      "QuadSPI", &res_regs);
 994         if (ret) {
 995                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
 996                 return -ENOMEM;
 997         }
 998         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 999                                      "QuadSPI-memory", &res_mem);
1000         if (ret) {
1001                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1002                 return -ENOMEM;
1003         }
1004
1005         /* Count flash numbers */
1006         fdt_for_each_subnode(subnode, blob, node)
1007                 ++flash_num;
1008
1009         if (flash_num == 0) {
1010                 debug("Error: Missing flashes!\n");
1011                 return -ENODEV;
1012         }
1013
1014         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1015                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1016         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1017                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1018
1019         plat->reg_base = res_regs.start;
1020         plat->amba_base = res_mem.start;
1021         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1022         plat->flash_num = flash_num;
1023
1024         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1025               __func__,
1026               (u64)plat->reg_base,
1027               (u64)plat->amba_base,
1028               (u64)plat->amba_total_size,
1029               plat->speed_hz,
1030               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1031               );
1032
1033         return 0;
1034 }
1035
1036 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1037                 const void *dout, void *din, unsigned long flags)
1038 {
1039         struct fsl_qspi_priv *priv;
1040         struct udevice *bus;
1041
1042         bus = dev->parent;
1043         priv = dev_get_priv(bus);
1044
1045         return qspi_xfer(priv, bitlen, dout, din, flags);
1046 }
1047
1048 static int fsl_qspi_claim_bus(struct udevice *dev)
1049 {
1050         struct fsl_qspi_priv *priv;
1051         struct udevice *bus;
1052         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1053         int ret;
1054
1055         bus = dev->parent;
1056         priv = dev_get_priv(bus);
1057
1058         /* make sure controller is not busy anywhere */
1059         ret = is_controller_busy(priv);
1060
1061         if (ret) {
1062                 debug("ERROR : The controller is busy\n");
1063                 return ret;
1064         }
1065
1066         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1067
1068         qspi_module_disable(priv, 0);
1069
1070         return 0;
1071 }
1072
1073 static int fsl_qspi_release_bus(struct udevice *dev)
1074 {
1075         struct fsl_qspi_priv *priv;
1076         struct udevice *bus;
1077
1078         bus = dev->parent;
1079         priv = dev_get_priv(bus);
1080
1081         qspi_module_disable(priv, 1);
1082
1083         return 0;
1084 }
1085
1086 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1087 {
1088         /* Nothing to do */
1089         return 0;
1090 }
1091
1092 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1093 {
1094         /* Nothing to do */
1095         return 0;
1096 }
1097
1098 static const struct dm_spi_ops fsl_qspi_ops = {
1099         .claim_bus      = fsl_qspi_claim_bus,
1100         .release_bus    = fsl_qspi_release_bus,
1101         .xfer           = fsl_qspi_xfer,
1102         .set_speed      = fsl_qspi_set_speed,
1103         .set_mode       = fsl_qspi_set_mode,
1104 };
1105
1106 static const struct udevice_id fsl_qspi_ids[] = {
1107         { .compatible = "fsl,vf610-qspi" },
1108         { .compatible = "fsl,imx6sx-qspi" },
1109         { .compatible = "fsl,imx6ul-qspi" },
1110         { .compatible = "fsl,imx7d-qspi" },
1111         { }
1112 };
1113
1114 U_BOOT_DRIVER(fsl_qspi) = {
1115         .name   = "fsl_qspi",
1116         .id     = UCLASS_SPI,
1117         .of_match = fsl_qspi_ids,
1118         .ops    = &fsl_qspi_ops,
1119         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1120         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1121         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1122         .probe  = fsl_qspi_probe,
1123         .child_pre_probe = fsl_qspi_child_pre_probe,
1124 };