drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <linux/iopoll.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include <wait_bit.h>
  18 #include "fsl_qspi.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  23
  24 #define FLASH_STATUS_WEL        0x02
  25
  26 /* SEQID */
  27 #define SEQID_WREN              1
  28 #define SEQID_FAST_READ         2
  29 #define SEQID_RDSR              3
  30 #define SEQID_SE                4
  31 #define SEQID_CHIP_ERASE        5
  32 #define SEQID_PP                6
  33 #define SEQID_RDID              7
  34 #define SEQID_BE_4K             8
  35 #ifdef CONFIG_SPI_FLASH_BAR
  36 #define SEQID_BRRD              9
  37 #define SEQID_BRWR              10
  38 #define SEQID_RDEAR             11
  39 #define SEQID_WREAR             12
  40 #endif
  41 #define SEQID_WRAR              13
  42 #define SEQID_RDAR              14
  43
  44 /* QSPI CMD */
  45 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  46 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  47 #define QSPI_CMD_WREN           0x06    /* Write enable */
  48 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  49 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  50 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  51 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  52 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  53
  54 /* Used for Micron, winbond and Macronix flashes */
  55 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  56 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  57
  58 /* Used for Spansion flashes only. */
  59 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  60 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  61
  62 /* Used for Spansion S25FS-S family flash only. */
  63 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  64 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  65
  66 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  67 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  68 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  69 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  70
  71 /* fsl_qspi_platdata flags */
  72 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  73
  74 /* default SCK frequency, unit: HZ */
  75 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  76
  77 /* QSPI max chipselect signals number */
  78 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  79
  80 /* Controller needs driver to swap endian */
  81 #define QUADSPI_QUIRK_SWAP_ENDIAN       BIT(0)
  82
  83 enum fsl_qspi_devtype {
  84         FSL_QUADSPI_VYBRID,
  85         FSL_QUADSPI_IMX6SX,
  86         FSL_QUADSPI_IMX6UL_7D,
  87 };
  88
  89 struct fsl_qspi_devtype_data {
  90         enum fsl_qspi_devtype devtype;
  91         u32 rxfifo;
  92         u32 txfifo;
  93         u32 ahb_buf_size;
  94         u32 driver_data;
  95 };
  96
  97 /**
  98  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  99  *
 100  * @flags: Flags for QSPI QSPI_FLAG_...
 101  * @speed_hz: Default SCK frequency
 102  * @reg_base: Base address of QSPI registers
 103  * @amba_base: Base address of QSPI memory mapping
 104  * @amba_total_size: size of QSPI memory mapping
 105  * @flash_num: Number of active slave devices
 106  * @num_chipselect: Number of QSPI chipselect signals
 107  */
 108 struct fsl_qspi_platdata {
 109         u32 flags;
 110         u32 speed_hz;
 111         fdt_addr_t reg_base;
 112         fdt_addr_t amba_base;
 113         fdt_size_t amba_total_size;
 114         u32 flash_num;
 115         u32 num_chipselect;
 116 };
 117
 118 /**
 119  * struct fsl_qspi_priv - private data for Freescale QSPI
 120  *
 121  * @flags: Flags for QSPI QSPI_FLAG_...
 122  * @bus_clk: QSPI input clk frequency
 123  * @speed_hz: Default SCK frequency
 124  * @cur_seqid: current LUT table sequence id
 125  * @sf_addr: flash access offset
 126  * @amba_base: Base address of QSPI memory mapping of every CS
 127  * @amba_total_size: size of QSPI memory mapping
 128  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 129  * @flash_num: Number of active slave devices
 130  * @num_chipselect: Number of QSPI chipselect signals
 131  * @regs: Point to QSPI register structure for I/O access
 132  */
 133 struct fsl_qspi_priv {
 134         u32 flags;
 135         u32 bus_clk;
 136         u32 speed_hz;
 137         u32 cur_seqid;
 138         u32 sf_addr;
 139         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 140         u32 amba_total_size;
 141         u32 cur_amba_base;
 142         u32 flash_num;
 143         u32 num_chipselect;
 144         struct fsl_qspi_regs *regs;
 145         struct fsl_qspi_devtype_data *devtype_data;
 146 };
 147
 148 static const struct fsl_qspi_devtype_data vybrid_data = {
 149         .devtype = FSL_QUADSPI_VYBRID,
 150         .rxfifo = 128,
 151         .txfifo = 64,
 152         .ahb_buf_size = 1024,
 153         .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
 154 };
 155
 156 static const struct fsl_qspi_devtype_data imx6sx_data = {
 157         .devtype = FSL_QUADSPI_IMX6SX,
 158         .rxfifo = 128,
 159         .txfifo = 512,
 160         .ahb_buf_size = 1024,
 161         .driver_data = 0,
 162 };
 163
 164 static const struct fsl_qspi_devtype_data imx6ul_7d_data = {
 165         .devtype = FSL_QUADSPI_IMX6UL_7D,
 166         .rxfifo = 128,
 167         .txfifo = 512,
 168         .ahb_buf_size = 1024,
 169         .driver_data = 0,
 170 };
 171
 172 static u32 qspi_read32(u32 flags, u32 *addr)
 173 {
 174         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 175                 in_be32(addr) : in_le32(addr);
 176 }
 177
 178 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 179 {
 180         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 181                 out_be32(addr, val) : out_le32(addr, val);
 182 }
 183
 184 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
 185 {
 186         u32 val;
 187         u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
 188                    QSPI_SR_IP_ACC_MASK;
 189
 190         if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
 191                 mask = (u32)cpu_to_be32(mask);
 192
 193         return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
 194 }
 195
 196 /* QSPI support swapping the flash read/write data
 197  * in hardware for LS102xA, but not for VF610 */
 198 static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data)
 199 {
 200         if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN)
 201                 return swab32(data);
 202         else
 203                 return data;
 204 }
 205
 206 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 207 {
 208         struct fsl_qspi_regs *regs = priv->regs;
 209         u32 lut_base;
 210
 211         /* Unlock the LUT */
 212         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 213         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 214
 215         /* Write Enable */
 216         lut_base = SEQID_WREN * 4;
 217         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 218                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 219         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 220         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 221         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 222
 223         /* Fast Read */
 224         lut_base = SEQID_FAST_READ * 4;
 225 #ifdef CONFIG_SPI_FLASH_BAR
 226         qspi_write32(priv->flags, &regs->lut[lut_base],
 227                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 228                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 229                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 230 #else
 231         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 232                 qspi_write32(priv->flags, &regs->lut[lut_base],
 233                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 234                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 235                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 236         else
 237                 qspi_write32(priv->flags, &regs->lut[lut_base],
 238                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 239                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 240                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 241                              INSTR1(LUT_ADDR));
 242 #endif
 243         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 244                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 245                      OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) |
 246                      INSTR1(LUT_READ));
 247         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 248         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 249
 250         /* Read Status */
 251         lut_base = SEQID_RDSR * 4;
 252         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 253                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 254                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 255         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 256         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 257         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 258
 259         /* Erase a sector */
 260         lut_base = SEQID_SE * 4;
 261 #ifdef CONFIG_SPI_FLASH_BAR
 262         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 263                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 264                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 265 #else
 266         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 267                 qspi_write32(priv->flags, &regs->lut[lut_base],
 268                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 269                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 270                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 271         else
 272                 qspi_write32(priv->flags, &regs->lut[lut_base],
 273                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 274                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 275                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 276 #endif
 277         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 278         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 279         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 280
 281         /* Erase the whole chip */
 282         lut_base = SEQID_CHIP_ERASE * 4;
 283         qspi_write32(priv->flags, &regs->lut[lut_base],
 284                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 285                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 286         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 287         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 288         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 289
 290         /* Page Program */
 291         lut_base = SEQID_PP * 4;
 292 #ifdef CONFIG_SPI_FLASH_BAR
 293         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 294                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 295                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 296 #else
 297         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 298                 qspi_write32(priv->flags, &regs->lut[lut_base],
 299                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 300                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 301                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 302         else
 303                 qspi_write32(priv->flags, &regs->lut[lut_base],
 304                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 305                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 306                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 307 #endif
 308         /* Use IDATSZ in IPCR to determine the size and here set 0. */
 309         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 310                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 311         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 312         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 313
 314         /* READ ID */
 315         lut_base = SEQID_RDID * 4;
 316         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 317                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 318                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 319         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 320         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 321         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 322
 323         /* SUB SECTOR 4K ERASE */
 324         lut_base = SEQID_BE_4K * 4;
 325         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 326                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 327                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 328
 329 #ifdef CONFIG_SPI_FLASH_BAR
 330         /*
 331          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 332          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 333          * initialization.
 334          */
 335         lut_base = SEQID_BRRD * 4;
 336         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 337                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 338                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 339
 340         lut_base = SEQID_BRWR * 4;
 341         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 342                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 343                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 344
 345         lut_base = SEQID_RDEAR * 4;
 346         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 347                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 348                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 349
 350         lut_base = SEQID_WREAR * 4;
 351         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 352                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 353                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 354 #endif
 355
 356         /*
 357          * Read any device register.
 358          * Used for Spansion S25FS-S family flash only.
 359          */
 360         lut_base = SEQID_RDAR * 4;
 361         qspi_write32(priv->flags, &regs->lut[lut_base],
 362                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 363                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 364                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 365         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 366                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 367                      OPRND1(1) | PAD1(LUT_PAD1) |
 368                      INSTR1(LUT_READ));
 369
 370         /*
 371          * Write any device register.
 372          * Used for Spansion S25FS-S family flash only.
 373          */
 374         lut_base = SEQID_WRAR * 4;
 375         qspi_write32(priv->flags, &regs->lut[lut_base],
 376                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 377                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 378                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 379         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 380                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 381
 382         /* Lock the LUT */
 383         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 384         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 385 }
 386
 387 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 388 /*
 389  * If we have changed the content of the flash by writing or erasing,
 390  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 391  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 392  * domain at the same time.
 393  */
 394 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 395 {
 396         struct fsl_qspi_regs *regs = priv->regs;
 397         u32 reg;
 398
 399         reg = qspi_read32(priv->flags, &regs->mcr);
 400         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 401         qspi_write32(priv->flags, &regs->mcr, reg);
 402
 403         /*
 404          * The minimum delay : 1 AHB + 2 SFCK clocks.
 405          * Delay 1 us is enough.
 406          */
 407         udelay(1);
 408
 409         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 410         qspi_write32(priv->flags, &regs->mcr, reg);
 411 }
 412
 413 /* Read out the data from the AHB buffer. */
 414 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 415 {
 416         struct fsl_qspi_regs *regs = priv->regs;
 417         u32 mcr_reg;
 418         void *rx_addr;
 419
 420         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 421
 422         qspi_write32(priv->flags, &regs->mcr,
 423                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 424                      mcr_reg);
 425
 426         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 427         /* Read out the data directly from the AHB buffer. */
 428         memcpy(rxbuf, rx_addr, len);
 429
 430         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 431 }
 432
 433 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 434 {
 435         u32 reg, reg2;
 436         struct fsl_qspi_regs *regs = priv->regs;
 437
 438         reg = qspi_read32(priv->flags, &regs->mcr);
 439         /* Disable the module */
 440         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 441
 442         /* Set the Sampling Register for DDR */
 443         reg2 = qspi_read32(priv->flags, &regs->smpr);
 444         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 445         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 446         qspi_write32(priv->flags, &regs->smpr, reg2);
 447
 448         /* Enable the module again (enable the DDR too) */
 449         reg |= QSPI_MCR_DDR_EN_MASK;
 450         /* Enable bit 29 for imx6sx */
 451         reg |= BIT(29);
 452         qspi_write32(priv->flags, &regs->mcr, reg);
 453
 454         /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
 455          * These two bits are reserved on other platforms
 456          */
 457         reg = qspi_read32(priv->flags, &regs->flshcr);
 458         reg &= ~(BIT(17));
 459         reg |= BIT(16);
 460         qspi_write32(priv->flags, &regs->flshcr, reg);
 461 }
 462
 463 /*
 464  * There are two different ways to read out the data from the flash:
 465  *  the "IP Command Read" and the "AHB Command Read".
 466  *
 467  * The IC guy suggests we use the "AHB Command Read" which is faster
 468  * then the "IP Command Read". (What's more is that there is a bug in
 469  * the "IP Command Read" in the Vybrid.)
 470  *
 471  * After we set up the registers for the "AHB Command Read", we can use
 472  * the memcpy to read the data directly. A "missed" access to the buffer
 473  * causes the controller to clear the buffer, and use the sequence pointed
 474  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 475  */
 476 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 477 {
 478         struct fsl_qspi_regs *regs = priv->regs;
 479
 480         /* AHB configuration for access buffer 0/1/2 .*/
 481         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 482         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 483         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 484         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 485                      ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT));
 486
 487         /* We only use the buffer3 */
 488         qspi_write32(priv->flags, &regs->buf0ind, 0);
 489         qspi_write32(priv->flags, &regs->buf1ind, 0);
 490         qspi_write32(priv->flags, &regs->buf2ind, 0);
 491
 492         /*
 493          * Set the default lut sequence for AHB Read.
 494          * Parallel mode is disabled.
 495          */
 496         qspi_write32(priv->flags, &regs->bfgencr,
 497                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 498
 499         /*Enable DDR Mode*/
 500         qspi_enable_ddr_mode(priv);
 501 }
 502 #endif
 503
 504 #ifdef CONFIG_SPI_FLASH_BAR
 505 /* Bank register read/write, EAR register read/write */
 506 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 507 {
 508         struct fsl_qspi_regs *regs = priv->regs;
 509         u32 reg, mcr_reg, data, seqid;
 510
 511         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 512         qspi_write32(priv->flags, &regs->mcr,
 513                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 514                      mcr_reg);
 515         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 516
 517         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 518
 519         if (priv->cur_seqid == QSPI_CMD_BRRD)
 520                 seqid = SEQID_BRRD;
 521         else
 522                 seqid = SEQID_RDEAR;
 523
 524         qspi_write32(priv->flags, &regs->ipcr,
 525                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 526
 527         /* Wait previous command complete */
 528         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 529                 ;
 530
 531         while (1) {
 532                 WATCHDOG_RESET();
 533
 534                 reg = qspi_read32(priv->flags, &regs->rbsr);
 535                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 536                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 537                         data = qspi_endian_xchg(priv, data);
 538                         memcpy(rxbuf, &data, len);
 539                         qspi_write32(priv->flags, &regs->mcr,
 540                                      qspi_read32(priv->flags, &regs->mcr) |
 541                                      QSPI_MCR_CLR_RXF_MASK);
 542                         break;
 543                 }
 544         }
 545
 546         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 547 }
 548 #endif
 549
 550 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 551 {
 552         struct fsl_qspi_regs *regs = priv->regs;
 553         u32 mcr_reg, rbsr_reg, data, size;
 554         int i;
 555
 556         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 557         qspi_write32(priv->flags, &regs->mcr,
 558                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 559                      mcr_reg);
 560         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 561
 562         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 563
 564         qspi_write32(priv->flags, &regs->ipcr,
 565                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 566         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 567                 ;
 568
 569         i = 0;
 570         while ((priv->devtype_data->rxfifo >= len) && (len > 0)) {
 571                 WATCHDOG_RESET();
 572
 573                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 574                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 575                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 576                         data = qspi_endian_xchg(priv, data);
 577                         size = (len < 4) ? len : 4;
 578                         memcpy(rxbuf, &data, size);
 579                         len -= size;
 580                         rxbuf++;
 581                         i++;
 582                 }
 583         }
 584
 585         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 586 }
 587
 588 /* If not use AHB read, read data from ip interface */
 589 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 590 {
 591         struct fsl_qspi_regs *regs = priv->regs;
 592         u32 mcr_reg, data;
 593         int i, size;
 594         u32 to_or_from;
 595         u32 seqid;
 596
 597         if (priv->cur_seqid == QSPI_CMD_RDAR)
 598                 seqid = SEQID_RDAR;
 599         else
 600                 seqid = SEQID_FAST_READ;
 601
 602         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 603         qspi_write32(priv->flags, &regs->mcr,
 604                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 605                      mcr_reg);
 606         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 607
 608         to_or_from = priv->sf_addr + priv->cur_amba_base;
 609
 610         while (len > 0) {
 611                 WATCHDOG_RESET();
 612
 613                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 614
 615                 size = (len > priv->devtype_data->rxfifo) ?
 616                         priv->devtype_data->rxfifo : len;
 617
 618                 qspi_write32(priv->flags, &regs->ipcr,
 619                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 620                              size);
 621                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 622                         ;
 623
 624                 to_or_from += size;
 625                 len -= size;
 626
 627                 i = 0;
 628                 while ((priv->devtype_data->rxfifo >= size) && (size > 0)) {
 629                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 630                         data = qspi_endian_xchg(priv, data);
 631                         if (size < 4)
 632                                 memcpy(rxbuf, &data, size);
 633                         else
 634                                 memcpy(rxbuf, &data, 4);
 635                         rxbuf++;
 636                         size -= 4;
 637                         i++;
 638                 }
 639                 qspi_write32(priv->flags, &regs->mcr,
 640                              qspi_read32(priv->flags, &regs->mcr) |
 641                              QSPI_MCR_CLR_RXF_MASK);
 642         }
 643
 644         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 645 }
 646
 647 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 648 {
 649         struct fsl_qspi_regs *regs = priv->regs;
 650         u32 mcr_reg, data, reg, status_reg, seqid;
 651         int i, size, tx_size;
 652         u32 to_or_from = 0;
 653
 654         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 655         qspi_write32(priv->flags, &regs->mcr,
 656                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 657                      mcr_reg);
 658         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 659
 660         status_reg = 0;
 661         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 662                 WATCHDOG_RESET();
 663
 664                 qspi_write32(priv->flags, &regs->ipcr,
 665                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 666                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 667                         ;
 668
 669                 qspi_write32(priv->flags, &regs->ipcr,
 670                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 671                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 672                         ;
 673
 674                 reg = qspi_read32(priv->flags, &regs->rbsr);
 675                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 676                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 677                         status_reg = qspi_endian_xchg(priv, status_reg);
 678                 }
 679                 qspi_write32(priv->flags, &regs->mcr,
 680                              qspi_read32(priv->flags, &regs->mcr) |
 681                              QSPI_MCR_CLR_RXF_MASK);
 682         }
 683
 684         /* Default is page programming */
 685         seqid = SEQID_PP;
 686         if (priv->cur_seqid == QSPI_CMD_WRAR)
 687                 seqid = SEQID_WRAR;
 688 #ifdef CONFIG_SPI_FLASH_BAR
 689         if (priv->cur_seqid == QSPI_CMD_BRWR)
 690                 seqid = SEQID_BRWR;
 691         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 692                 seqid = SEQID_WREAR;
 693 #endif
 694
 695         to_or_from = priv->sf_addr + priv->cur_amba_base;
 696
 697         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 698
 699         tx_size = (len > priv->devtype_data->txfifo) ?
 700                 priv->devtype_data->txfifo : len;
 701
 702         size = tx_size / 16;
 703         /*
 704          * There must be atleast 128bit data
 705          * available in TX FIFO for any pop operation
 706          */
 707         if (tx_size % 16)
 708                 size++;
 709         for (i = 0; i < size * 4; i++) {
 710                 memcpy(&data, txbuf, 4);
 711                 data = qspi_endian_xchg(priv, data);
 712                 qspi_write32(priv->flags, &regs->tbdr, data);
 713                 txbuf += 4;
 714         }
 715
 716         qspi_write32(priv->flags, &regs->ipcr,
 717                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 718         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 719                 ;
 720
 721         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 722 }
 723
 724 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 725 {
 726         struct fsl_qspi_regs *regs = priv->regs;
 727         u32 mcr_reg, reg, data;
 728
 729         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 730         qspi_write32(priv->flags, &regs->mcr,
 731                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 732                      mcr_reg);
 733         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 734
 735         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 736
 737         qspi_write32(priv->flags, &regs->ipcr,
 738                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 739         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 740                 ;
 741
 742         while (1) {
 743                 WATCHDOG_RESET();
 744
 745                 reg = qspi_read32(priv->flags, &regs->rbsr);
 746                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 747                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 748                         data = qspi_endian_xchg(priv, data);
 749                         memcpy(rxbuf, &data, len);
 750                         qspi_write32(priv->flags, &regs->mcr,
 751                                      qspi_read32(priv->flags, &regs->mcr) |
 752                                      QSPI_MCR_CLR_RXF_MASK);
 753                         break;
 754                 }
 755         }
 756
 757         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 758 }
 759
 760 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 761 {
 762         struct fsl_qspi_regs *regs = priv->regs;
 763         u32 mcr_reg;
 764         u32 to_or_from = 0;
 765
 766         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 767         qspi_write32(priv->flags, &regs->mcr,
 768                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 769                      mcr_reg);
 770         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 771
 772         to_or_from = priv->sf_addr + priv->cur_amba_base;
 773         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 774
 775         qspi_write32(priv->flags, &regs->ipcr,
 776                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 777         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 778                 ;
 779
 780         if (priv->cur_seqid == QSPI_CMD_SE) {
 781                 qspi_write32(priv->flags, &regs->ipcr,
 782                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 783         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 784                 qspi_write32(priv->flags, &regs->ipcr,
 785                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 786         }
 787         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 788                 ;
 789
 790         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 791 }
 792
 793 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 794                 const void *dout, void *din, unsigned long flags)
 795 {
 796         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 797         static u32 wr_sfaddr;
 798         u32 txbuf;
 799
 800         WATCHDOG_RESET();
 801
 802         if (dout) {
 803                 if (flags & SPI_XFER_BEGIN) {
 804                         priv->cur_seqid = *(u8 *)dout;
 805                         memcpy(&txbuf, dout, 4);
 806                 }
 807
 808                 if (flags == SPI_XFER_END) {
 809                         priv->sf_addr = wr_sfaddr;
 810                         qspi_op_write(priv, (u8 *)dout, bytes);
 811                         return 0;
 812                 }
 813
 814                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 815                     priv->cur_seqid == QSPI_CMD_RDAR) {
 816                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 817                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 818                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 819                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 820                         qspi_op_erase(priv);
 821                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 822                            priv->cur_seqid == QSPI_CMD_WRAR) {
 823                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 824                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 825                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 826 #ifdef CONFIG_SPI_FLASH_BAR
 827                         wr_sfaddr = 0;
 828 #endif
 829                 }
 830         }
 831
 832         if (din) {
 833                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 834 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 835                         qspi_ahb_read(priv, din, bytes);
 836 #else
 837                         qspi_op_read(priv, din, bytes);
 838 #endif
 839                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 840                         qspi_op_read(priv, din, bytes);
 841                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 842                         qspi_op_rdid(priv, din, bytes);
 843                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 844                         qspi_op_rdsr(priv, din, bytes);
 845 #ifdef CONFIG_SPI_FLASH_BAR
 846                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 847                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 848                         priv->sf_addr = 0;
 849                         qspi_op_rdbank(priv, din, bytes);
 850                 }
 851 #endif
 852         }
 853
 854 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 855         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 856             (priv->cur_seqid == QSPI_CMD_PP) ||
 857             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 858             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 859             (priv->cur_seqid == QSPI_CMD_BRWR))
 860                 qspi_ahb_invalid(priv);
 861 #endif
 862
 863         return 0;
 864 }
 865
 866 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 867 {
 868         u32 mcr_val;
 869
 870         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 871         if (disable)
 872                 mcr_val |= QSPI_MCR_MDIS_MASK;
 873         else
 874                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 875         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 876 }
 877
 878 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 879 {
 880         u32 smpr_val;
 881
 882         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 883         smpr_val &= ~clear_bits;
 884         smpr_val |= set_bits;
 885         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 886 }
 887
 888 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 889 {
 890         struct spi_slave *slave = dev_get_parent_priv(dev);
 891         struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev));
 892
 893         slave->max_write_size = priv->devtype_data->txfifo;
 894
 895         return 0;
 896 }
 897
 898 static int fsl_qspi_probe(struct udevice *bus)
 899 {
 900         u32 amba_size_per_chip;
 901         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 902         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 903         struct dm_spi_bus *dm_spi_bus;
 904         int i, ret;
 905
 906         dm_spi_bus = bus->uclass_priv;
 907
 908         dm_spi_bus->max_hz = plat->speed_hz;
 909
 910         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 911         priv->flags = plat->flags;
 912
 913         priv->speed_hz = plat->speed_hz;
 914         /*
 915          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 916          * AMBA memory zone should be located on the 0~4GB space
 917          * even on a 64bits cpu.
 918          */
 919         priv->amba_base[0] = (u32)plat->amba_base;
 920         priv->amba_total_size = (u32)plat->amba_total_size;
 921         priv->flash_num = plat->flash_num;
 922         priv->num_chipselect = plat->num_chipselect;
 923
 924         priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus);
 925         if (!priv->devtype_data) {
 926                 printf("ERROR : No devtype_data found\n");
 927                 return -ENODEV;
 928         }
 929
 930         debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n",
 931                 priv->devtype_data->devtype,
 932                 priv->devtype_data->txfifo,
 933                 priv->devtype_data->rxfifo,
 934                 priv->devtype_data->ahb_buf_size,
 935                 priv->devtype_data->driver_data);
 936
 937         /* make sure controller is not busy anywhere */
 938         ret = is_controller_busy(priv);
 939
 940         if (ret) {
 941                 debug("ERROR : The controller is busy\n");
 942                 return ret;
 943         }
 944
 945         qspi_write32(priv->flags, &priv->regs->mcr,
 946                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 947                      QSPI_MCR_END_CFD_LE);
 948
 949         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 950                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 951
 952         /*
 953          * Assign AMBA memory zone for every chipselect
 954          * QuadSPI has two channels, every channel has two chipselects.
 955          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
 956          * into two parts and assign to every channel. This indicate that every
 957          * channel only has one valid chipselect.
 958          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
 959          * into four parts and assign to every chipselect.
 960          * Every channel will has two valid chipselects.
 961          */
 962         amba_size_per_chip = priv->amba_total_size >>
 963                              (priv->num_chipselect >> 1);
 964         for (i = 1 ; i < priv->num_chipselect ; i++)
 965                 priv->amba_base[i] =
 966                         amba_size_per_chip + priv->amba_base[i - 1];
 967
 968         /*
 969          * Any read access to non-implemented addresses will provide
 970          * undefined results.
 971          *
 972          * In case single die flash devices, TOP_ADDR_MEMA2 and
 973          * TOP_ADDR_MEMB2 should be initialized/programmed to
 974          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 975          * setting the size of these devices to 0.  This would ensure
 976          * that the complete memory map is assigned to only one flash device.
 977          */
 978         qspi_write32(priv->flags, &priv->regs->sfa1ad,
 979                      priv->amba_base[0] + amba_size_per_chip);
 980         switch (priv->num_chipselect) {
 981         case 1:
 982                 break;
 983         case 2:
 984                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 985                              priv->amba_base[1]);
 986                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 987                              priv->amba_base[1] + amba_size_per_chip);
 988                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 989                              priv->amba_base[1] + amba_size_per_chip);
 990                 break;
 991         case 4:
 992                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 993                              priv->amba_base[2]);
 994                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 995                              priv->amba_base[3]);
 996                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 997                              priv->amba_base[3] + amba_size_per_chip);
 998                 break;
 999         default:
1000                 debug("Error: Unsupported chipselect number %u!\n",
1001                       priv->num_chipselect);
1002                 qspi_module_disable(priv, 1);
1003                 return -EINVAL;
1004         }
1005
1006         qspi_set_lut(priv);
1007
1008 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1009         qspi_init_ahb_read(priv);
1010 #endif
1011
1012         qspi_module_disable(priv, 0);
1013
1014         return 0;
1015 }
1016
1017 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1018 {
1019         struct fdt_resource res_regs, res_mem;
1020         struct fsl_qspi_platdata *plat = bus->platdata;
1021         const void *blob = gd->fdt_blob;
1022         int node = dev_of_offset(bus);
1023         int ret, flash_num = 0, subnode;
1024
1025         if (fdtdec_get_bool(blob, node, "big-endian"))
1026                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1027
1028         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1029                                      "QuadSPI", &res_regs);
1030         if (ret) {
1031                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1032                 return -ENOMEM;
1033         }
1034         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1035                                      "QuadSPI-memory", &res_mem);
1036         if (ret) {
1037                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1038                 return -ENOMEM;
1039         }
1040
1041         /* Count flash numbers */
1042         fdt_for_each_subnode(subnode, blob, node)
1043                 ++flash_num;
1044
1045         if (flash_num == 0) {
1046                 debug("Error: Missing flashes!\n");
1047                 return -ENODEV;
1048         }
1049
1050         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1051                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1052         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1053                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1054
1055         plat->reg_base = res_regs.start;
1056         plat->amba_base = res_mem.start;
1057         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1058         plat->flash_num = flash_num;
1059
1060         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1061               __func__,
1062               (u64)plat->reg_base,
1063               (u64)plat->amba_base,
1064               (u64)plat->amba_total_size,
1065               plat->speed_hz,
1066               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1067               );
1068
1069         return 0;
1070 }
1071
1072 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1073                 const void *dout, void *din, unsigned long flags)
1074 {
1075         struct fsl_qspi_priv *priv;
1076         struct udevice *bus;
1077
1078         bus = dev->parent;
1079         priv = dev_get_priv(bus);
1080
1081         return qspi_xfer(priv, bitlen, dout, din, flags);
1082 }
1083
1084 static int fsl_qspi_claim_bus(struct udevice *dev)
1085 {
1086         struct fsl_qspi_priv *priv;
1087         struct udevice *bus;
1088         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1089         int ret;
1090
1091         bus = dev->parent;
1092         priv = dev_get_priv(bus);
1093
1094         /* make sure controller is not busy anywhere */
1095         ret = is_controller_busy(priv);
1096
1097         if (ret) {
1098                 debug("ERROR : The controller is busy\n");
1099                 return ret;
1100         }
1101
1102         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1103
1104         qspi_module_disable(priv, 0);
1105
1106         return 0;
1107 }
1108
1109 static int fsl_qspi_release_bus(struct udevice *dev)
1110 {
1111         struct fsl_qspi_priv *priv;
1112         struct udevice *bus;
1113
1114         bus = dev->parent;
1115         priv = dev_get_priv(bus);
1116
1117         qspi_module_disable(priv, 1);
1118
1119         return 0;
1120 }
1121
1122 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1123 {
1124         /* Nothing to do */
1125         return 0;
1126 }
1127
1128 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1129 {
1130         /* Nothing to do */
1131         return 0;
1132 }
1133
1134 static const struct dm_spi_ops fsl_qspi_ops = {
1135         .claim_bus      = fsl_qspi_claim_bus,
1136         .release_bus    = fsl_qspi_release_bus,
1137         .xfer           = fsl_qspi_xfer,
1138         .set_speed      = fsl_qspi_set_speed,
1139         .set_mode       = fsl_qspi_set_mode,
1140 };
1141
1142 static const struct udevice_id fsl_qspi_ids[] = {
1143         { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data },
1144         { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data },
1145         { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data },
1146         { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data },
1147         { }
1148 };
1149
1150 U_BOOT_DRIVER(fsl_qspi) = {
1151         .name   = "fsl_qspi",
1152         .id     = UCLASS_SPI,
1153         .of_match = fsl_qspi_ids,
1154         .ops    = &fsl_qspi_ops,
1155         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1156         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1157         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1158         .probe  = fsl_qspi_probe,
1159         .child_pre_probe = fsl_qspi_child_pre_probe,
1160 };