drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15 #include <watchdog.h>
  16 #include <wait_bit.h>
  17 #include "fsl_qspi.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define RX_BUFFER_SIZE          0x80
  22 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
  23         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
  24 #define TX_BUFFER_SIZE          0x200
  25 #else
  26 #define TX_BUFFER_SIZE          0x40
  27 #endif
  28
  29 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  30
  31 #define FLASH_STATUS_WEL        0x02
  32
  33 /* SEQID */
  34 #define SEQID_WREN              1
  35 #define SEQID_FAST_READ         2
  36 #define SEQID_RDSR              3
  37 #define SEQID_SE                4
  38 #define SEQID_CHIP_ERASE        5
  39 #define SEQID_PP                6
  40 #define SEQID_RDID              7
  41 #define SEQID_BE_4K             8
  42 #ifdef CONFIG_SPI_FLASH_BAR
  43 #define SEQID_BRRD              9
  44 #define SEQID_BRWR              10
  45 #define SEQID_RDEAR             11
  46 #define SEQID_WREAR             12
  47 #endif
  48 #define SEQID_WRAR              13
  49 #define SEQID_RDAR              14
  50
  51 /* QSPI CMD */
  52 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  53 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  54 #define QSPI_CMD_WREN           0x06    /* Write enable */
  55 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  56 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  57 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  58 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  59 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  60
  61 /* Used for Micron, winbond and Macronix flashes */
  62 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  63 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  64
  65 /* Used for Spansion flashes only. */
  66 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  67 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  68
  69 /* Used for Spansion S25FS-S family flash only. */
  70 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  71 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  72
  73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  74 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  75 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  76 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  77
  78 /* fsl_qspi_platdata flags */
  79 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  80
  81 /* default SCK frequency, unit: HZ */
  82 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  83
  84 /* QSPI max chipselect signals number */
  85 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  86
  87 /**
  88  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  89  *
  90  * @flags: Flags for QSPI QSPI_FLAG_...
  91  * @speed_hz: Default SCK frequency
  92  * @reg_base: Base address of QSPI registers
  93  * @amba_base: Base address of QSPI memory mapping
  94  * @amba_total_size: size of QSPI memory mapping
  95  * @flash_num: Number of active slave devices
  96  * @num_chipselect: Number of QSPI chipselect signals
  97  */
  98 struct fsl_qspi_platdata {
  99         u32 flags;
 100         u32 speed_hz;
 101         fdt_addr_t reg_base;
 102         fdt_addr_t amba_base;
 103         fdt_size_t amba_total_size;
 104         u32 flash_num;
 105         u32 num_chipselect;
 106 };
 107
 108 /**
 109  * struct fsl_qspi_priv - private data for Freescale QSPI
 110  *
 111  * @flags: Flags for QSPI QSPI_FLAG_...
 112  * @bus_clk: QSPI input clk frequency
 113  * @speed_hz: Default SCK frequency
 114  * @cur_seqid: current LUT table sequence id
 115  * @sf_addr: flash access offset
 116  * @amba_base: Base address of QSPI memory mapping of every CS
 117  * @amba_total_size: size of QSPI memory mapping
 118  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 119  * @flash_num: Number of active slave devices
 120  * @num_chipselect: Number of QSPI chipselect signals
 121  * @regs: Point to QSPI register structure for I/O access
 122  */
 123 struct fsl_qspi_priv {
 124         u32 flags;
 125         u32 bus_clk;
 126         u32 speed_hz;
 127         u32 cur_seqid;
 128         u32 sf_addr;
 129         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 130         u32 amba_total_size;
 131         u32 cur_amba_base;
 132         u32 flash_num;
 133         u32 num_chipselect;
 134         struct fsl_qspi_regs *regs;
 135 };
 136
 137
 138 static u32 qspi_read32(u32 flags, u32 *addr)
 139 {
 140         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 141                 in_be32(addr) : in_le32(addr);
 142 }
 143
 144 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 145 {
 146         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 147                 out_be32(addr, val) : out_le32(addr, val);
 148 }
 149
 150 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
 151 {
 152         u32 val;
 153         const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
 154                          QSPI_SR_IP_ACC_MASK;
 155         unsigned long timeout = timer_get_us() + 1000;
 156
 157         do {
 158                 val = qspi_read32(priv->flags, &priv->regs->sr);
 159
 160                 if ((~val & mask) == mask)
 161                         return 0;
 162
 163                 if (timer_get_us() > timeout )
 164                         return -ETIMEDOUT;
 165         } while (1);
 166 }
 167
 168 /* QSPI support swapping the flash read/write data
 169  * in hardware for LS102xA, but not for VF610 */
 170 static inline u32 qspi_endian_xchg(u32 data)
 171 {
 172 #ifdef CONFIG_VF610
 173         return swab32(data);
 174 #else
 175         return data;
 176 #endif
 177 }
 178
 179 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 180 {
 181         struct fsl_qspi_regs *regs = priv->regs;
 182         u32 lut_base;
 183
 184         /* Unlock the LUT */
 185         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 186         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 187
 188         /* Write Enable */
 189         lut_base = SEQID_WREN * 4;
 190         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 191                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 192         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 193         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 194         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 195
 196         /* Fast Read */
 197         lut_base = SEQID_FAST_READ * 4;
 198 #ifdef CONFIG_SPI_FLASH_BAR
 199         qspi_write32(priv->flags, &regs->lut[lut_base],
 200                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 201                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 202                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 203 #else
 204         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 205                 qspi_write32(priv->flags, &regs->lut[lut_base],
 206                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 207                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 208                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 209         else
 210                 qspi_write32(priv->flags, &regs->lut[lut_base],
 211                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 212                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 213                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 214                              INSTR1(LUT_ADDR));
 215 #endif
 216         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 217                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 218                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 219                      INSTR1(LUT_READ));
 220         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 221         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 222
 223         /* Read Status */
 224         lut_base = SEQID_RDSR * 4;
 225         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 226                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 227                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 228         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 229         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 230         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 231
 232         /* Erase a sector */
 233         lut_base = SEQID_SE * 4;
 234 #ifdef CONFIG_SPI_FLASH_BAR
 235         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 236                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 237                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 238 #else
 239         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 240                 qspi_write32(priv->flags, &regs->lut[lut_base],
 241                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 242                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 243                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 244         else
 245                 qspi_write32(priv->flags, &regs->lut[lut_base],
 246                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 247                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 248                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 249 #endif
 250         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 251         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 252         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 253
 254         /* Erase the whole chip */
 255         lut_base = SEQID_CHIP_ERASE * 4;
 256         qspi_write32(priv->flags, &regs->lut[lut_base],
 257                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 258                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 259         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 260         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 261         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 262
 263         /* Page Program */
 264         lut_base = SEQID_PP * 4;
 265 #ifdef CONFIG_SPI_FLASH_BAR
 266         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 267                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 268                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 269 #else
 270         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 271                 qspi_write32(priv->flags, &regs->lut[lut_base],
 272                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 273                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 274                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 275         else
 276                 qspi_write32(priv->flags, &regs->lut[lut_base],
 277                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 278                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 279                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 280 #endif
 281 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
 282         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
 283         /*
 284          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 285          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 286          */
 287         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 288                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 289 #else
 290         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 291                      OPRND0(TX_BUFFER_SIZE) |
 292                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 293 #endif
 294         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 295         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 296
 297         /* READ ID */
 298         lut_base = SEQID_RDID * 4;
 299         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 300                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 301                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 302         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 303         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 304         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 305
 306         /* SUB SECTOR 4K ERASE */
 307         lut_base = SEQID_BE_4K * 4;
 308         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 309                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 310                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 311
 312 #ifdef CONFIG_SPI_FLASH_BAR
 313         /*
 314          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 315          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 316          * initialization.
 317          */
 318         lut_base = SEQID_BRRD * 4;
 319         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 320                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 321                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 322
 323         lut_base = SEQID_BRWR * 4;
 324         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 325                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 326                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 327
 328         lut_base = SEQID_RDEAR * 4;
 329         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 330                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 331                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 332
 333         lut_base = SEQID_WREAR * 4;
 334         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 335                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 336                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 337 #endif
 338
 339         /*
 340          * Read any device register.
 341          * Used for Spansion S25FS-S family flash only.
 342          */
 343         lut_base = SEQID_RDAR * 4;
 344         qspi_write32(priv->flags, &regs->lut[lut_base],
 345                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 346                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 347                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 348         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 349                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 350                      OPRND1(1) | PAD1(LUT_PAD1) |
 351                      INSTR1(LUT_READ));
 352
 353         /*
 354          * Write any device register.
 355          * Used for Spansion S25FS-S family flash only.
 356          */
 357         lut_base = SEQID_WRAR * 4;
 358         qspi_write32(priv->flags, &regs->lut[lut_base],
 359                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 360                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 361                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 362         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 363                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 364
 365         /* Lock the LUT */
 366         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 367         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 368 }
 369
 370 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 371 /*
 372  * If we have changed the content of the flash by writing or erasing,
 373  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 374  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 375  * domain at the same time.
 376  */
 377 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 378 {
 379         struct fsl_qspi_regs *regs = priv->regs;
 380         u32 reg;
 381
 382         reg = qspi_read32(priv->flags, &regs->mcr);
 383         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 384         qspi_write32(priv->flags, &regs->mcr, reg);
 385
 386         /*
 387          * The minimum delay : 1 AHB + 2 SFCK clocks.
 388          * Delay 1 us is enough.
 389          */
 390         udelay(1);
 391
 392         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 393         qspi_write32(priv->flags, &regs->mcr, reg);
 394 }
 395
 396 /* Read out the data from the AHB buffer. */
 397 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 398 {
 399         struct fsl_qspi_regs *regs = priv->regs;
 400         u32 mcr_reg;
 401         void *rx_addr;
 402
 403         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 404
 405         qspi_write32(priv->flags, &regs->mcr,
 406                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 407                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 408
 409         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 410         /* Read out the data directly from the AHB buffer. */
 411         memcpy(rxbuf, rx_addr, len);
 412
 413         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 414 }
 415
 416 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 417 {
 418         u32 reg, reg2;
 419         struct fsl_qspi_regs *regs = priv->regs;
 420
 421         reg = qspi_read32(priv->flags, &regs->mcr);
 422         /* Disable the module */
 423         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 424
 425         /* Set the Sampling Register for DDR */
 426         reg2 = qspi_read32(priv->flags, &regs->smpr);
 427         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 428         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 429         qspi_write32(priv->flags, &regs->smpr, reg2);
 430
 431         /* Enable the module again (enable the DDR too) */
 432         reg |= QSPI_MCR_DDR_EN_MASK;
 433         /* Enable bit 29 for imx6sx */
 434         reg |= BIT(29);
 435
 436         qspi_write32(priv->flags, &regs->mcr, reg);
 437 }
 438
 439 /*
 440  * There are two different ways to read out the data from the flash:
 441  *  the "IP Command Read" and the "AHB Command Read".
 442  *
 443  * The IC guy suggests we use the "AHB Command Read" which is faster
 444  * then the "IP Command Read". (What's more is that there is a bug in
 445  * the "IP Command Read" in the Vybrid.)
 446  *
 447  * After we set up the registers for the "AHB Command Read", we can use
 448  * the memcpy to read the data directly. A "missed" access to the buffer
 449  * causes the controller to clear the buffer, and use the sequence pointed
 450  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 451  */
 452 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 453 {
 454         struct fsl_qspi_regs *regs = priv->regs;
 455
 456         /* AHB configuration for access buffer 0/1/2 .*/
 457         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 458         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 459         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 460         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 461                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 462
 463         /* We only use the buffer3 */
 464         qspi_write32(priv->flags, &regs->buf0ind, 0);
 465         qspi_write32(priv->flags, &regs->buf1ind, 0);
 466         qspi_write32(priv->flags, &regs->buf2ind, 0);
 467
 468         /*
 469          * Set the default lut sequence for AHB Read.
 470          * Parallel mode is disabled.
 471          */
 472         qspi_write32(priv->flags, &regs->bfgencr,
 473                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 474
 475         /*Enable DDR Mode*/
 476         qspi_enable_ddr_mode(priv);
 477 }
 478 #endif
 479
 480 #ifdef CONFIG_SPI_FLASH_BAR
 481 /* Bank register read/write, EAR register read/write */
 482 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 483 {
 484         struct fsl_qspi_regs *regs = priv->regs;
 485         u32 reg, mcr_reg, data, seqid;
 486
 487         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 488         qspi_write32(priv->flags, &regs->mcr,
 489                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 490                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 491         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 492
 493         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 494
 495         if (priv->cur_seqid == QSPI_CMD_BRRD)
 496                 seqid = SEQID_BRRD;
 497         else
 498                 seqid = SEQID_RDEAR;
 499
 500         qspi_write32(priv->flags, &regs->ipcr,
 501                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 502
 503         /* Wait previous command complete */
 504         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 505                 ;
 506
 507         while (1) {
 508                 WATCHDOG_RESET();
 509
 510                 reg = qspi_read32(priv->flags, &regs->rbsr);
 511                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 512                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 513                         data = qspi_endian_xchg(data);
 514                         memcpy(rxbuf, &data, len);
 515                         qspi_write32(priv->flags, &regs->mcr,
 516                                      qspi_read32(priv->flags, &regs->mcr) |
 517                                      QSPI_MCR_CLR_RXF_MASK);
 518                         break;
 519                 }
 520         }
 521
 522         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 523 }
 524 #endif
 525
 526 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 527 {
 528         struct fsl_qspi_regs *regs = priv->regs;
 529         u32 mcr_reg, rbsr_reg, data, size;
 530         int i;
 531
 532         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 533         qspi_write32(priv->flags, &regs->mcr,
 534                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 535                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 536         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 537
 538         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 539
 540         qspi_write32(priv->flags, &regs->ipcr,
 541                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 542         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 543                 ;
 544
 545         i = 0;
 546         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 547                 WATCHDOG_RESET();
 548
 549                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 550                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 551                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 552                         data = qspi_endian_xchg(data);
 553                         size = (len < 4) ? len : 4;
 554                         memcpy(rxbuf, &data, size);
 555                         len -= size;
 556                         rxbuf++;
 557                         i++;
 558                 }
 559         }
 560
 561         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 562 }
 563
 564 /* If not use AHB read, read data from ip interface */
 565 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 566 {
 567         struct fsl_qspi_regs *regs = priv->regs;
 568         u32 mcr_reg, data;
 569         int i, size;
 570         u32 to_or_from;
 571         u32 seqid;
 572
 573         if (priv->cur_seqid == QSPI_CMD_RDAR)
 574                 seqid = SEQID_RDAR;
 575         else
 576                 seqid = SEQID_FAST_READ;
 577
 578         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 579         qspi_write32(priv->flags, &regs->mcr,
 580                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 581                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 582         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 583
 584         to_or_from = priv->sf_addr + priv->cur_amba_base;
 585
 586         while (len > 0) {
 587                 WATCHDOG_RESET();
 588
 589                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 590
 591                 size = (len > RX_BUFFER_SIZE) ?
 592                         RX_BUFFER_SIZE : len;
 593
 594                 qspi_write32(priv->flags, &regs->ipcr,
 595                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 596                              size);
 597                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 598                         ;
 599
 600                 to_or_from += size;
 601                 len -= size;
 602
 603                 i = 0;
 604                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 605                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 606                         data = qspi_endian_xchg(data);
 607                         if (size < 4)
 608                                 memcpy(rxbuf, &data, size);
 609                         else
 610                                 memcpy(rxbuf, &data, 4);
 611                         rxbuf++;
 612                         size -= 4;
 613                         i++;
 614                 }
 615                 qspi_write32(priv->flags, &regs->mcr,
 616                              qspi_read32(priv->flags, &regs->mcr) |
 617                              QSPI_MCR_CLR_RXF_MASK);
 618         }
 619
 620         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 621 }
 622
 623 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 624 {
 625         struct fsl_qspi_regs *regs = priv->regs;
 626         u32 mcr_reg, data, reg, status_reg, seqid;
 627         int i, size, tx_size;
 628         u32 to_or_from = 0;
 629
 630         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 631         qspi_write32(priv->flags, &regs->mcr,
 632                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 633                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 634         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 635
 636         status_reg = 0;
 637         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 638                 WATCHDOG_RESET();
 639
 640                 qspi_write32(priv->flags, &regs->ipcr,
 641                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 642                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 643                         ;
 644
 645                 qspi_write32(priv->flags, &regs->ipcr,
 646                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 647                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 648                         ;
 649
 650                 reg = qspi_read32(priv->flags, &regs->rbsr);
 651                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 652                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 653                         status_reg = qspi_endian_xchg(status_reg);
 654                 }
 655                 qspi_write32(priv->flags, &regs->mcr,
 656                              qspi_read32(priv->flags, &regs->mcr) |
 657                              QSPI_MCR_CLR_RXF_MASK);
 658         }
 659
 660         /* Default is page programming */
 661         seqid = SEQID_PP;
 662         if (priv->cur_seqid == QSPI_CMD_WRAR)
 663                 seqid = SEQID_WRAR;
 664 #ifdef CONFIG_SPI_FLASH_BAR
 665         if (priv->cur_seqid == QSPI_CMD_BRWR)
 666                 seqid = SEQID_BRWR;
 667         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 668                 seqid = SEQID_WREAR;
 669 #endif
 670
 671         to_or_from = priv->sf_addr + priv->cur_amba_base;
 672
 673         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 674
 675         tx_size = (len > TX_BUFFER_SIZE) ?
 676                 TX_BUFFER_SIZE : len;
 677
 678         size = tx_size / 16;
 679         /*
 680          * There must be atleast 128bit data
 681          * available in TX FIFO for any pop operation
 682          */
 683         if (tx_size % 16)
 684                 size++;
 685         for (i = 0; i < size * 4; i++) {
 686                 memcpy(&data, txbuf, 4);
 687                 data = qspi_endian_xchg(data);
 688                 qspi_write32(priv->flags, &regs->tbdr, data);
 689                 txbuf += 4;
 690         }
 691
 692         qspi_write32(priv->flags, &regs->ipcr,
 693                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 694         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 695                 ;
 696
 697         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 698 }
 699
 700 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 701 {
 702         struct fsl_qspi_regs *regs = priv->regs;
 703         u32 mcr_reg, reg, data;
 704
 705         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 706         qspi_write32(priv->flags, &regs->mcr,
 707                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 708                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 709         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 710
 711         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 712
 713         qspi_write32(priv->flags, &regs->ipcr,
 714                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 715         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 716                 ;
 717
 718         while (1) {
 719                 WATCHDOG_RESET();
 720
 721                 reg = qspi_read32(priv->flags, &regs->rbsr);
 722                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 723                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 724                         data = qspi_endian_xchg(data);
 725                         memcpy(rxbuf, &data, len);
 726                         qspi_write32(priv->flags, &regs->mcr,
 727                                      qspi_read32(priv->flags, &regs->mcr) |
 728                                      QSPI_MCR_CLR_RXF_MASK);
 729                         break;
 730                 }
 731         }
 732
 733         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 734 }
 735
 736 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 737 {
 738         struct fsl_qspi_regs *regs = priv->regs;
 739         u32 mcr_reg;
 740         u32 to_or_from = 0;
 741
 742         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 743         qspi_write32(priv->flags, &regs->mcr,
 744                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 745                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 746         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 747
 748         to_or_from = priv->sf_addr + priv->cur_amba_base;
 749         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 750
 751         qspi_write32(priv->flags, &regs->ipcr,
 752                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 753         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 754                 ;
 755
 756         if (priv->cur_seqid == QSPI_CMD_SE) {
 757                 qspi_write32(priv->flags, &regs->ipcr,
 758                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 759         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 760                 qspi_write32(priv->flags, &regs->ipcr,
 761                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 762         }
 763         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 764                 ;
 765
 766         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 767 }
 768
 769 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 770                 const void *dout, void *din, unsigned long flags)
 771 {
 772         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 773         static u32 wr_sfaddr;
 774         u32 txbuf;
 775
 776         WATCHDOG_RESET();
 777
 778         if (dout) {
 779                 if (flags & SPI_XFER_BEGIN) {
 780                         priv->cur_seqid = *(u8 *)dout;
 781                         memcpy(&txbuf, dout, 4);
 782                 }
 783
 784                 if (flags == SPI_XFER_END) {
 785                         priv->sf_addr = wr_sfaddr;
 786                         qspi_op_write(priv, (u8 *)dout, bytes);
 787                         return 0;
 788                 }
 789
 790                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 791                     priv->cur_seqid == QSPI_CMD_RDAR) {
 792                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 793                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 794                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 795                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 796                         qspi_op_erase(priv);
 797                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 798                            priv->cur_seqid == QSPI_CMD_WRAR) {
 799                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 800                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 801                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 802 #ifdef CONFIG_SPI_FLASH_BAR
 803                         wr_sfaddr = 0;
 804 #endif
 805                 }
 806         }
 807
 808         if (din) {
 809                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 810 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 811                         qspi_ahb_read(priv, din, bytes);
 812 #else
 813                         qspi_op_read(priv, din, bytes);
 814 #endif
 815                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 816                         qspi_op_read(priv, din, bytes);
 817                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 818                         qspi_op_rdid(priv, din, bytes);
 819                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 820                         qspi_op_rdsr(priv, din, bytes);
 821 #ifdef CONFIG_SPI_FLASH_BAR
 822                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 823                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 824                         priv->sf_addr = 0;
 825                         qspi_op_rdbank(priv, din, bytes);
 826                 }
 827 #endif
 828         }
 829
 830 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 831         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 832             (priv->cur_seqid == QSPI_CMD_PP) ||
 833             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 834             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 835             (priv->cur_seqid == QSPI_CMD_BRWR))
 836                 qspi_ahb_invalid(priv);
 837 #endif
 838
 839         return 0;
 840 }
 841
 842 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 843 {
 844         u32 mcr_val;
 845
 846         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 847         if (disable)
 848                 mcr_val |= QSPI_MCR_MDIS_MASK;
 849         else
 850                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 851         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 852 }
 853
 854 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 855 {
 856         u32 smpr_val;
 857
 858         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 859         smpr_val &= ~clear_bits;
 860         smpr_val |= set_bits;
 861         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 862 }
 863
 864 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 865 {
 866         struct spi_slave *slave = dev_get_parent_priv(dev);
 867
 868         slave->max_write_size = TX_BUFFER_SIZE;
 869
 870         return 0;
 871 }
 872
 873 static int fsl_qspi_probe(struct udevice *bus)
 874 {
 875         u32 mcr_val;
 876         u32 amba_size_per_chip;
 877         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 878         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 879         struct dm_spi_bus *dm_spi_bus;
 880         int i, ret;
 881
 882         dm_spi_bus = bus->uclass_priv;
 883
 884         dm_spi_bus->max_hz = plat->speed_hz;
 885
 886         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 887         priv->flags = plat->flags;
 888
 889         priv->speed_hz = plat->speed_hz;
 890         /*
 891          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 892          * AMBA memory zone should be located on the 0~4GB space
 893          * even on a 64bits cpu.
 894          */
 895         priv->amba_base[0] = (u32)plat->amba_base;
 896         priv->amba_total_size = (u32)plat->amba_total_size;
 897         priv->flash_num = plat->flash_num;
 898         priv->num_chipselect = plat->num_chipselect;
 899
 900         /* make sure controller is not busy anywhere */
 901         ret = is_controller_busy(priv);
 902
 903         if (ret) {
 904                 debug("ERROR : The controller is busy\n");
 905                 return ret;
 906         }
 907
 908         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 909
 910         /* Set endianness to LE for i.mx */
 911         if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
 912                 mcr_val = QSPI_MCR_END_CFD_LE;
 913
 914         qspi_write32(priv->flags, &priv->regs->mcr,
 915                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 916                      (mcr_val & QSPI_MCR_END_CFD_MASK));
 917
 918         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 919                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 920
 921         /*
 922          * Assign AMBA memory zone for every chipselect
 923          * QuadSPI has two channels, every channel has two chipselects.
 924          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
 925          * into two parts and assign to every channel. This indicate that every
 926          * channel only has one valid chipselect.
 927          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
 928          * into four parts and assign to every chipselect.
 929          * Every channel will has two valid chipselects.
 930          */
 931         amba_size_per_chip = priv->amba_total_size >>
 932                              (priv->num_chipselect >> 1);
 933         for (i = 1 ; i < priv->num_chipselect ; i++)
 934                 priv->amba_base[i] =
 935                         amba_size_per_chip + priv->amba_base[i - 1];
 936
 937         /*
 938          * Any read access to non-implemented addresses will provide
 939          * undefined results.
 940          *
 941          * In case single die flash devices, TOP_ADDR_MEMA2 and
 942          * TOP_ADDR_MEMB2 should be initialized/programmed to
 943          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 944          * setting the size of these devices to 0.  This would ensure
 945          * that the complete memory map is assigned to only one flash device.
 946          */
 947         qspi_write32(priv->flags, &priv->regs->sfa1ad,
 948                      priv->amba_base[0] + amba_size_per_chip);
 949         switch (priv->num_chipselect) {
 950         case 1:
 951                 break;
 952         case 2:
 953                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 954                              priv->amba_base[1]);
 955                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 956                              priv->amba_base[1] + amba_size_per_chip);
 957                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 958                              priv->amba_base[1] + amba_size_per_chip);
 959                 break;
 960         case 4:
 961                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 962                              priv->amba_base[2]);
 963                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 964                              priv->amba_base[3]);
 965                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 966                              priv->amba_base[3] + amba_size_per_chip);
 967                 break;
 968         default:
 969                 debug("Error: Unsupported chipselect number %u!\n",
 970                       priv->num_chipselect);
 971                 qspi_module_disable(priv, 1);
 972                 return -EINVAL;
 973         }
 974
 975         qspi_set_lut(priv);
 976
 977 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 978         qspi_init_ahb_read(priv);
 979 #endif
 980
 981         qspi_module_disable(priv, 0);
 982
 983         return 0;
 984 }
 985
 986 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 987 {
 988         struct fdt_resource res_regs, res_mem;
 989         struct fsl_qspi_platdata *plat = bus->platdata;
 990         const void *blob = gd->fdt_blob;
 991         int node = dev_of_offset(bus);
 992         int ret, flash_num = 0, subnode;
 993
 994         if (fdtdec_get_bool(blob, node, "big-endian"))
 995                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 996
 997         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 998                                      "QuadSPI", &res_regs);
 999         if (ret) {
1000                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1001                 return -ENOMEM;
1002         }
1003         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1004                                      "QuadSPI-memory", &res_mem);
1005         if (ret) {
1006                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1007                 return -ENOMEM;
1008         }
1009
1010         /* Count flash numbers */
1011         fdt_for_each_subnode(subnode, blob, node)
1012                 ++flash_num;
1013
1014         if (flash_num == 0) {
1015                 debug("Error: Missing flashes!\n");
1016                 return -ENODEV;
1017         }
1018
1019         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1020                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1021         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1022                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1023
1024         plat->reg_base = res_regs.start;
1025         plat->amba_base = res_mem.start;
1026         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1027         plat->flash_num = flash_num;
1028
1029         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1030               __func__,
1031               (u64)plat->reg_base,
1032               (u64)plat->amba_base,
1033               (u64)plat->amba_total_size,
1034               plat->speed_hz,
1035               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1036               );
1037
1038         return 0;
1039 }
1040
1041 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1042                 const void *dout, void *din, unsigned long flags)
1043 {
1044         struct fsl_qspi_priv *priv;
1045         struct udevice *bus;
1046
1047         bus = dev->parent;
1048         priv = dev_get_priv(bus);
1049
1050         return qspi_xfer(priv, bitlen, dout, din, flags);
1051 }
1052
1053 static int fsl_qspi_claim_bus(struct udevice *dev)
1054 {
1055         struct fsl_qspi_priv *priv;
1056         struct udevice *bus;
1057         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1058         int ret;
1059
1060         bus = dev->parent;
1061         priv = dev_get_priv(bus);
1062
1063         /* make sure controller is not busy anywhere */
1064         ret = is_controller_busy(priv);
1065
1066         if (ret) {
1067                 debug("ERROR : The controller is busy\n");
1068                 return ret;
1069         }
1070
1071         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1072
1073         qspi_module_disable(priv, 0);
1074
1075         return 0;
1076 }
1077
1078 static int fsl_qspi_release_bus(struct udevice *dev)
1079 {
1080         struct fsl_qspi_priv *priv;
1081         struct udevice *bus;
1082
1083         bus = dev->parent;
1084         priv = dev_get_priv(bus);
1085
1086         qspi_module_disable(priv, 1);
1087
1088         return 0;
1089 }
1090
1091 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1092 {
1093         /* Nothing to do */
1094         return 0;
1095 }
1096
1097 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1098 {
1099         /* Nothing to do */
1100         return 0;
1101 }
1102
1103 static const struct dm_spi_ops fsl_qspi_ops = {
1104         .claim_bus      = fsl_qspi_claim_bus,
1105         .release_bus    = fsl_qspi_release_bus,
1106         .xfer           = fsl_qspi_xfer,
1107         .set_speed      = fsl_qspi_set_speed,
1108         .set_mode       = fsl_qspi_set_mode,
1109 };
1110
1111 static const struct udevice_id fsl_qspi_ids[] = {
1112         { .compatible = "fsl,vf610-qspi" },
1113         { .compatible = "fsl,imx6sx-qspi" },
1114         { .compatible = "fsl,imx6ul-qspi" },
1115         { .compatible = "fsl,imx7d-qspi" },
1116         { }
1117 };
1118
1119 U_BOOT_DRIVER(fsl_qspi) = {
1120         .name   = "fsl_qspi",
1121         .id     = UCLASS_SPI,
1122         .of_match = fsl_qspi_ids,
1123         .ops    = &fsl_qspi_ops,
1124         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1125         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1126         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1127         .probe  = fsl_qspi_probe,
1128         .child_pre_probe = fsl_qspi_child_pre_probe,
1129 };