drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <linux/iopoll.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include <wait_bit.h>
  18 #include "fsl_qspi.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define RX_BUFFER_SIZE          0x80
  23 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
  24         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
  25 #define TX_BUFFER_SIZE          0x200
  26 #else
  27 #define TX_BUFFER_SIZE          0x40
  28 #endif
  29
  30 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  31
  32 #define FLASH_STATUS_WEL        0x02
  33
  34 /* SEQID */
  35 #define SEQID_WREN              1
  36 #define SEQID_FAST_READ         2
  37 #define SEQID_RDSR              3
  38 #define SEQID_SE                4
  39 #define SEQID_CHIP_ERASE        5
  40 #define SEQID_PP                6
  41 #define SEQID_RDID              7
  42 #define SEQID_BE_4K             8
  43 #ifdef CONFIG_SPI_FLASH_BAR
  44 #define SEQID_BRRD              9
  45 #define SEQID_BRWR              10
  46 #define SEQID_RDEAR             11
  47 #define SEQID_WREAR             12
  48 #endif
  49 #define SEQID_WRAR              13
  50 #define SEQID_RDAR              14
  51
  52 /* QSPI CMD */
  53 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  54 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  55 #define QSPI_CMD_WREN           0x06    /* Write enable */
  56 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  57 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  58 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  59 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  60 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  61
  62 /* Used for Micron, winbond and Macronix flashes */
  63 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  64 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  65
  66 /* Used for Spansion flashes only. */
  67 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  68 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  69
  70 /* Used for Spansion S25FS-S family flash only. */
  71 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  72 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  73
  74 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  75 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  76 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  77 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  78
  79 /* fsl_qspi_platdata flags */
  80 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  81
  82 /* default SCK frequency, unit: HZ */
  83 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  84
  85 /* QSPI max chipselect signals number */
  86 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  87
  88 /**
  89  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  90  *
  91  * @flags: Flags for QSPI QSPI_FLAG_...
  92  * @speed_hz: Default SCK frequency
  93  * @reg_base: Base address of QSPI registers
  94  * @amba_base: Base address of QSPI memory mapping
  95  * @amba_total_size: size of QSPI memory mapping
  96  * @flash_num: Number of active slave devices
  97  * @num_chipselect: Number of QSPI chipselect signals
  98  */
  99 struct fsl_qspi_platdata {
 100         u32 flags;
 101         u32 speed_hz;
 102         fdt_addr_t reg_base;
 103         fdt_addr_t amba_base;
 104         fdt_size_t amba_total_size;
 105         u32 flash_num;
 106         u32 num_chipselect;
 107 };
 108
 109 /**
 110  * struct fsl_qspi_priv - private data for Freescale QSPI
 111  *
 112  * @flags: Flags for QSPI QSPI_FLAG_...
 113  * @bus_clk: QSPI input clk frequency
 114  * @speed_hz: Default SCK frequency
 115  * @cur_seqid: current LUT table sequence id
 116  * @sf_addr: flash access offset
 117  * @amba_base: Base address of QSPI memory mapping of every CS
 118  * @amba_total_size: size of QSPI memory mapping
 119  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 120  * @flash_num: Number of active slave devices
 121  * @num_chipselect: Number of QSPI chipselect signals
 122  * @regs: Point to QSPI register structure for I/O access
 123  */
 124 struct fsl_qspi_priv {
 125         u32 flags;
 126         u32 bus_clk;
 127         u32 speed_hz;
 128         u32 cur_seqid;
 129         u32 sf_addr;
 130         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 131         u32 amba_total_size;
 132         u32 cur_amba_base;
 133         u32 flash_num;
 134         u32 num_chipselect;
 135         struct fsl_qspi_regs *regs;
 136 };
 137
 138
 139 static u32 qspi_read32(u32 flags, u32 *addr)
 140 {
 141         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 142                 in_be32(addr) : in_le32(addr);
 143 }
 144
 145 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 146 {
 147         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 148                 out_be32(addr, val) : out_le32(addr, val);
 149 }
 150
 151 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
 152 {
 153         u32 val;
 154         u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
 155                    QSPI_SR_IP_ACC_MASK;
 156
 157         if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
 158                 mask = (u32)cpu_to_be32(mask);
 159
 160         return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
 161 }
 162
 163 /* QSPI support swapping the flash read/write data
 164  * in hardware for LS102xA, but not for VF610 */
 165 static inline u32 qspi_endian_xchg(u32 data)
 166 {
 167 #ifdef CONFIG_VF610
 168         return swab32(data);
 169 #else
 170         return data;
 171 #endif
 172 }
 173
 174 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 175 {
 176         struct fsl_qspi_regs *regs = priv->regs;
 177         u32 lut_base;
 178
 179         /* Unlock the LUT */
 180         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 181         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 182
 183         /* Write Enable */
 184         lut_base = SEQID_WREN * 4;
 185         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 186                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 187         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 188         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 189         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 190
 191         /* Fast Read */
 192         lut_base = SEQID_FAST_READ * 4;
 193 #ifdef CONFIG_SPI_FLASH_BAR
 194         qspi_write32(priv->flags, &regs->lut[lut_base],
 195                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 196                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 197                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 198 #else
 199         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 200                 qspi_write32(priv->flags, &regs->lut[lut_base],
 201                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 202                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 203                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 204         else
 205                 qspi_write32(priv->flags, &regs->lut[lut_base],
 206                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 207                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 208                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 209                              INSTR1(LUT_ADDR));
 210 #endif
 211         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 212                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 213                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 214                      INSTR1(LUT_READ));
 215         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 216         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 217
 218         /* Read Status */
 219         lut_base = SEQID_RDSR * 4;
 220         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 221                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 222                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 223         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 224         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 225         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 226
 227         /* Erase a sector */
 228         lut_base = SEQID_SE * 4;
 229 #ifdef CONFIG_SPI_FLASH_BAR
 230         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 231                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 232                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 233 #else
 234         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 235                 qspi_write32(priv->flags, &regs->lut[lut_base],
 236                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 237                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 238                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 239         else
 240                 qspi_write32(priv->flags, &regs->lut[lut_base],
 241                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 242                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 243                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 244 #endif
 245         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 246         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 247         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 248
 249         /* Erase the whole chip */
 250         lut_base = SEQID_CHIP_ERASE * 4;
 251         qspi_write32(priv->flags, &regs->lut[lut_base],
 252                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 253                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 254         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 255         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 256         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 257
 258         /* Page Program */
 259         lut_base = SEQID_PP * 4;
 260 #ifdef CONFIG_SPI_FLASH_BAR
 261         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 262                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 263                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 264 #else
 265         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 266                 qspi_write32(priv->flags, &regs->lut[lut_base],
 267                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 268                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 269                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 270         else
 271                 qspi_write32(priv->flags, &regs->lut[lut_base],
 272                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 273                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 274                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 275 #endif
 276         /* Use IDATSZ in IPCR to determine the size and here set 0. */
 277         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 278                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 279         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 280         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 281
 282         /* READ ID */
 283         lut_base = SEQID_RDID * 4;
 284         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 285                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 286                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 287         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 288         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 289         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 290
 291         /* SUB SECTOR 4K ERASE */
 292         lut_base = SEQID_BE_4K * 4;
 293         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 294                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 295                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 296
 297 #ifdef CONFIG_SPI_FLASH_BAR
 298         /*
 299          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 300          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 301          * initialization.
 302          */
 303         lut_base = SEQID_BRRD * 4;
 304         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 305                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 306                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 307
 308         lut_base = SEQID_BRWR * 4;
 309         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 310                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 311                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 312
 313         lut_base = SEQID_RDEAR * 4;
 314         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 315                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 316                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 317
 318         lut_base = SEQID_WREAR * 4;
 319         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 320                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 321                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 322 #endif
 323
 324         /*
 325          * Read any device register.
 326          * Used for Spansion S25FS-S family flash only.
 327          */
 328         lut_base = SEQID_RDAR * 4;
 329         qspi_write32(priv->flags, &regs->lut[lut_base],
 330                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 331                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 332                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 333         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 334                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 335                      OPRND1(1) | PAD1(LUT_PAD1) |
 336                      INSTR1(LUT_READ));
 337
 338         /*
 339          * Write any device register.
 340          * Used for Spansion S25FS-S family flash only.
 341          */
 342         lut_base = SEQID_WRAR * 4;
 343         qspi_write32(priv->flags, &regs->lut[lut_base],
 344                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 345                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 346                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 347         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 348                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 349
 350         /* Lock the LUT */
 351         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 352         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 353 }
 354
 355 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 356 /*
 357  * If we have changed the content of the flash by writing or erasing,
 358  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 359  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 360  * domain at the same time.
 361  */
 362 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 363 {
 364         struct fsl_qspi_regs *regs = priv->regs;
 365         u32 reg;
 366
 367         reg = qspi_read32(priv->flags, &regs->mcr);
 368         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 369         qspi_write32(priv->flags, &regs->mcr, reg);
 370
 371         /*
 372          * The minimum delay : 1 AHB + 2 SFCK clocks.
 373          * Delay 1 us is enough.
 374          */
 375         udelay(1);
 376
 377         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 378         qspi_write32(priv->flags, &regs->mcr, reg);
 379 }
 380
 381 /* Read out the data from the AHB buffer. */
 382 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 383 {
 384         struct fsl_qspi_regs *regs = priv->regs;
 385         u32 mcr_reg;
 386         void *rx_addr;
 387
 388         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 389
 390         qspi_write32(priv->flags, &regs->mcr,
 391                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 392                      mcr_reg);
 393
 394         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 395         /* Read out the data directly from the AHB buffer. */
 396         memcpy(rxbuf, rx_addr, len);
 397
 398         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 399 }
 400
 401 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 402 {
 403         u32 reg, reg2;
 404         struct fsl_qspi_regs *regs = priv->regs;
 405
 406         reg = qspi_read32(priv->flags, &regs->mcr);
 407         /* Disable the module */
 408         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 409
 410         /* Set the Sampling Register for DDR */
 411         reg2 = qspi_read32(priv->flags, &regs->smpr);
 412         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 413         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 414         qspi_write32(priv->flags, &regs->smpr, reg2);
 415
 416         /* Enable the module again (enable the DDR too) */
 417         reg |= QSPI_MCR_DDR_EN_MASK;
 418         /* Enable bit 29 for imx6sx */
 419         reg |= BIT(29);
 420
 421         qspi_write32(priv->flags, &regs->mcr, reg);
 422
 423         /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
 424          * These two bits are reserved on other platforms
 425          */
 426         reg = qspi_read32(priv->flags, &regs->flshcr);
 427         reg &= ~(BIT(17));
 428         reg |= BIT(16);
 429         qspi_write32(priv->flags, &regs->flshcr, reg);
 430 }
 431
 432 /*
 433  * There are two different ways to read out the data from the flash:
 434  *  the "IP Command Read" and the "AHB Command Read".
 435  *
 436  * The IC guy suggests we use the "AHB Command Read" which is faster
 437  * then the "IP Command Read". (What's more is that there is a bug in
 438  * the "IP Command Read" in the Vybrid.)
 439  *
 440  * After we set up the registers for the "AHB Command Read", we can use
 441  * the memcpy to read the data directly. A "missed" access to the buffer
 442  * causes the controller to clear the buffer, and use the sequence pointed
 443  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 444  */
 445 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 446 {
 447         struct fsl_qspi_regs *regs = priv->regs;
 448
 449         /* AHB configuration for access buffer 0/1/2 .*/
 450         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 451         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 452         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 453         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 454                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 455
 456         /* We only use the buffer3 */
 457         qspi_write32(priv->flags, &regs->buf0ind, 0);
 458         qspi_write32(priv->flags, &regs->buf1ind, 0);
 459         qspi_write32(priv->flags, &regs->buf2ind, 0);
 460
 461         /*
 462          * Set the default lut sequence for AHB Read.
 463          * Parallel mode is disabled.
 464          */
 465         qspi_write32(priv->flags, &regs->bfgencr,
 466                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 467
 468         /*Enable DDR Mode*/
 469         qspi_enable_ddr_mode(priv);
 470 }
 471 #endif
 472
 473 #ifdef CONFIG_SPI_FLASH_BAR
 474 /* Bank register read/write, EAR register read/write */
 475 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 476 {
 477         struct fsl_qspi_regs *regs = priv->regs;
 478         u32 reg, mcr_reg, data, seqid;
 479
 480         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 481         qspi_write32(priv->flags, &regs->mcr,
 482                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 483                      mcr_reg);
 484         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 485
 486         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 487
 488         if (priv->cur_seqid == QSPI_CMD_BRRD)
 489                 seqid = SEQID_BRRD;
 490         else
 491                 seqid = SEQID_RDEAR;
 492
 493         qspi_write32(priv->flags, &regs->ipcr,
 494                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 495
 496         /* Wait previous command complete */
 497         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 498                 ;
 499
 500         while (1) {
 501                 WATCHDOG_RESET();
 502
 503                 reg = qspi_read32(priv->flags, &regs->rbsr);
 504                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 505                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 506                         data = qspi_endian_xchg(data);
 507                         memcpy(rxbuf, &data, len);
 508                         qspi_write32(priv->flags, &regs->mcr,
 509                                      qspi_read32(priv->flags, &regs->mcr) |
 510                                      QSPI_MCR_CLR_RXF_MASK);
 511                         break;
 512                 }
 513         }
 514
 515         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 516 }
 517 #endif
 518
 519 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 520 {
 521         struct fsl_qspi_regs *regs = priv->regs;
 522         u32 mcr_reg, rbsr_reg, data, size;
 523         int i;
 524
 525         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 526         qspi_write32(priv->flags, &regs->mcr,
 527                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 528                      mcr_reg);
 529         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 530
 531         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 532
 533         qspi_write32(priv->flags, &regs->ipcr,
 534                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 535         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 536                 ;
 537
 538         i = 0;
 539         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 540                 WATCHDOG_RESET();
 541
 542                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 543                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 544                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 545                         data = qspi_endian_xchg(data);
 546                         size = (len < 4) ? len : 4;
 547                         memcpy(rxbuf, &data, size);
 548                         len -= size;
 549                         rxbuf++;
 550                         i++;
 551                 }
 552         }
 553
 554         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 555 }
 556
 557 /* If not use AHB read, read data from ip interface */
 558 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 559 {
 560         struct fsl_qspi_regs *regs = priv->regs;
 561         u32 mcr_reg, data;
 562         int i, size;
 563         u32 to_or_from;
 564         u32 seqid;
 565
 566         if (priv->cur_seqid == QSPI_CMD_RDAR)
 567                 seqid = SEQID_RDAR;
 568         else
 569                 seqid = SEQID_FAST_READ;
 570
 571         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 572         qspi_write32(priv->flags, &regs->mcr,
 573                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 574                      mcr_reg);
 575         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 576
 577         to_or_from = priv->sf_addr + priv->cur_amba_base;
 578
 579         while (len > 0) {
 580                 WATCHDOG_RESET();
 581
 582                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 583
 584                 size = (len > RX_BUFFER_SIZE) ?
 585                         RX_BUFFER_SIZE : len;
 586
 587                 qspi_write32(priv->flags, &regs->ipcr,
 588                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 589                              size);
 590                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 591                         ;
 592
 593                 to_or_from += size;
 594                 len -= size;
 595
 596                 i = 0;
 597                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 598                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 599                         data = qspi_endian_xchg(data);
 600                         if (size < 4)
 601                                 memcpy(rxbuf, &data, size);
 602                         else
 603                                 memcpy(rxbuf, &data, 4);
 604                         rxbuf++;
 605                         size -= 4;
 606                         i++;
 607                 }
 608                 qspi_write32(priv->flags, &regs->mcr,
 609                              qspi_read32(priv->flags, &regs->mcr) |
 610                              QSPI_MCR_CLR_RXF_MASK);
 611         }
 612
 613         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 614 }
 615
 616 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 617 {
 618         struct fsl_qspi_regs *regs = priv->regs;
 619         u32 mcr_reg, data, reg, status_reg, seqid;
 620         int i, size, tx_size;
 621         u32 to_or_from = 0;
 622
 623         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 624         qspi_write32(priv->flags, &regs->mcr,
 625                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 626                      mcr_reg);
 627         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 628
 629         status_reg = 0;
 630         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 631                 WATCHDOG_RESET();
 632
 633                 qspi_write32(priv->flags, &regs->ipcr,
 634                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 635                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 636                         ;
 637
 638                 qspi_write32(priv->flags, &regs->ipcr,
 639                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 640                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 641                         ;
 642
 643                 reg = qspi_read32(priv->flags, &regs->rbsr);
 644                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 645                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 646                         status_reg = qspi_endian_xchg(status_reg);
 647                 }
 648                 qspi_write32(priv->flags, &regs->mcr,
 649                              qspi_read32(priv->flags, &regs->mcr) |
 650                              QSPI_MCR_CLR_RXF_MASK);
 651         }
 652
 653         /* Default is page programming */
 654         seqid = SEQID_PP;
 655         if (priv->cur_seqid == QSPI_CMD_WRAR)
 656                 seqid = SEQID_WRAR;
 657 #ifdef CONFIG_SPI_FLASH_BAR
 658         if (priv->cur_seqid == QSPI_CMD_BRWR)
 659                 seqid = SEQID_BRWR;
 660         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 661                 seqid = SEQID_WREAR;
 662 #endif
 663
 664         to_or_from = priv->sf_addr + priv->cur_amba_base;
 665
 666         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 667
 668         tx_size = (len > TX_BUFFER_SIZE) ?
 669                 TX_BUFFER_SIZE : len;
 670
 671         size = tx_size / 16;
 672         /*
 673          * There must be atleast 128bit data
 674          * available in TX FIFO for any pop operation
 675          */
 676         if (tx_size % 16)
 677                 size++;
 678         for (i = 0; i < size * 4; i++) {
 679                 memcpy(&data, txbuf, 4);
 680                 data = qspi_endian_xchg(data);
 681                 qspi_write32(priv->flags, &regs->tbdr, data);
 682                 txbuf += 4;
 683         }
 684
 685         qspi_write32(priv->flags, &regs->ipcr,
 686                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 687         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 688                 ;
 689
 690         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 691 }
 692
 693 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 694 {
 695         struct fsl_qspi_regs *regs = priv->regs;
 696         u32 mcr_reg, reg, data;
 697
 698         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 699         qspi_write32(priv->flags, &regs->mcr,
 700                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 701                      mcr_reg);
 702         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 703
 704         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 705
 706         qspi_write32(priv->flags, &regs->ipcr,
 707                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 708         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 709                 ;
 710
 711         while (1) {
 712                 WATCHDOG_RESET();
 713
 714                 reg = qspi_read32(priv->flags, &regs->rbsr);
 715                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 716                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 717                         data = qspi_endian_xchg(data);
 718                         memcpy(rxbuf, &data, len);
 719                         qspi_write32(priv->flags, &regs->mcr,
 720                                      qspi_read32(priv->flags, &regs->mcr) |
 721                                      QSPI_MCR_CLR_RXF_MASK);
 722                         break;
 723                 }
 724         }
 725
 726         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 727 }
 728
 729 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 730 {
 731         struct fsl_qspi_regs *regs = priv->regs;
 732         u32 mcr_reg;
 733         u32 to_or_from = 0;
 734
 735         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 736         qspi_write32(priv->flags, &regs->mcr,
 737                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 738                      mcr_reg);
 739         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 740
 741         to_or_from = priv->sf_addr + priv->cur_amba_base;
 742         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 743
 744         qspi_write32(priv->flags, &regs->ipcr,
 745                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 746         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 747                 ;
 748
 749         if (priv->cur_seqid == QSPI_CMD_SE) {
 750                 qspi_write32(priv->flags, &regs->ipcr,
 751                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 752         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 753                 qspi_write32(priv->flags, &regs->ipcr,
 754                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 755         }
 756         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 757                 ;
 758
 759         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 760 }
 761
 762 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 763                 const void *dout, void *din, unsigned long flags)
 764 {
 765         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 766         static u32 wr_sfaddr;
 767         u32 txbuf;
 768
 769         WATCHDOG_RESET();
 770
 771         if (dout) {
 772                 if (flags & SPI_XFER_BEGIN) {
 773                         priv->cur_seqid = *(u8 *)dout;
 774                         memcpy(&txbuf, dout, 4);
 775                 }
 776
 777                 if (flags == SPI_XFER_END) {
 778                         priv->sf_addr = wr_sfaddr;
 779                         qspi_op_write(priv, (u8 *)dout, bytes);
 780                         return 0;
 781                 }
 782
 783                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 784                     priv->cur_seqid == QSPI_CMD_RDAR) {
 785                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 786                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 787                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 788                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 789                         qspi_op_erase(priv);
 790                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 791                            priv->cur_seqid == QSPI_CMD_WRAR) {
 792                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 793                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 794                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 795 #ifdef CONFIG_SPI_FLASH_BAR
 796                         wr_sfaddr = 0;
 797 #endif
 798                 }
 799         }
 800
 801         if (din) {
 802                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 803 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 804                         qspi_ahb_read(priv, din, bytes);
 805 #else
 806                         qspi_op_read(priv, din, bytes);
 807 #endif
 808                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 809                         qspi_op_read(priv, din, bytes);
 810                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 811                         qspi_op_rdid(priv, din, bytes);
 812                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 813                         qspi_op_rdsr(priv, din, bytes);
 814 #ifdef CONFIG_SPI_FLASH_BAR
 815                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 816                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 817                         priv->sf_addr = 0;
 818                         qspi_op_rdbank(priv, din, bytes);
 819                 }
 820 #endif
 821         }
 822
 823 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 824         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 825             (priv->cur_seqid == QSPI_CMD_PP) ||
 826             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 827             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 828             (priv->cur_seqid == QSPI_CMD_BRWR))
 829                 qspi_ahb_invalid(priv);
 830 #endif
 831
 832         return 0;
 833 }
 834
 835 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 836 {
 837         u32 mcr_val;
 838
 839         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 840         if (disable)
 841                 mcr_val |= QSPI_MCR_MDIS_MASK;
 842         else
 843                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 844         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 845 }
 846
 847 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 848 {
 849         u32 smpr_val;
 850
 851         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 852         smpr_val &= ~clear_bits;
 853         smpr_val |= set_bits;
 854         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 855 }
 856
 857 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 858 {
 859         struct spi_slave *slave = dev_get_parent_priv(dev);
 860
 861         slave->max_write_size = TX_BUFFER_SIZE;
 862
 863         return 0;
 864 }
 865
 866 static int fsl_qspi_probe(struct udevice *bus)
 867 {
 868         u32 amba_size_per_chip;
 869         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 870         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 871         struct dm_spi_bus *dm_spi_bus;
 872         int i, ret;
 873
 874         dm_spi_bus = bus->uclass_priv;
 875
 876         dm_spi_bus->max_hz = plat->speed_hz;
 877
 878         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 879         priv->flags = plat->flags;
 880
 881         priv->speed_hz = plat->speed_hz;
 882         /*
 883          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 884          * AMBA memory zone should be located on the 0~4GB space
 885          * even on a 64bits cpu.
 886          */
 887         priv->amba_base[0] = (u32)plat->amba_base;
 888         priv->amba_total_size = (u32)plat->amba_total_size;
 889         priv->flash_num = plat->flash_num;
 890         priv->num_chipselect = plat->num_chipselect;
 891
 892         /* make sure controller is not busy anywhere */
 893         ret = is_controller_busy(priv);
 894
 895         if (ret) {
 896                 debug("ERROR : The controller is busy\n");
 897                 return ret;
 898         }
 899
 900         qspi_write32(priv->flags, &priv->regs->mcr,
 901                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 902                      QSPI_MCR_END_CFD_LE);
 903
 904         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 905                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 906
 907         /*
 908          * Assign AMBA memory zone for every chipselect
 909          * QuadSPI has two channels, every channel has two chipselects.
 910          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
 911          * into two parts and assign to every channel. This indicate that every
 912          * channel only has one valid chipselect.
 913          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
 914          * into four parts and assign to every chipselect.
 915          * Every channel will has two valid chipselects.
 916          */
 917         amba_size_per_chip = priv->amba_total_size >>
 918                              (priv->num_chipselect >> 1);
 919         for (i = 1 ; i < priv->num_chipselect ; i++)
 920                 priv->amba_base[i] =
 921                         amba_size_per_chip + priv->amba_base[i - 1];
 922
 923         /*
 924          * Any read access to non-implemented addresses will provide
 925          * undefined results.
 926          *
 927          * In case single die flash devices, TOP_ADDR_MEMA2 and
 928          * TOP_ADDR_MEMB2 should be initialized/programmed to
 929          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 930          * setting the size of these devices to 0.  This would ensure
 931          * that the complete memory map is assigned to only one flash device.
 932          */
 933         qspi_write32(priv->flags, &priv->regs->sfa1ad,
 934                      priv->amba_base[0] + amba_size_per_chip);
 935         switch (priv->num_chipselect) {
 936         case 1:
 937                 break;
 938         case 2:
 939                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 940                              priv->amba_base[1]);
 941                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 942                              priv->amba_base[1] + amba_size_per_chip);
 943                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 944                              priv->amba_base[1] + amba_size_per_chip);
 945                 break;
 946         case 4:
 947                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 948                              priv->amba_base[2]);
 949                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 950                              priv->amba_base[3]);
 951                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 952                              priv->amba_base[3] + amba_size_per_chip);
 953                 break;
 954         default:
 955                 debug("Error: Unsupported chipselect number %u!\n",
 956                       priv->num_chipselect);
 957                 qspi_module_disable(priv, 1);
 958                 return -EINVAL;
 959         }
 960
 961         qspi_set_lut(priv);
 962
 963 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 964         qspi_init_ahb_read(priv);
 965 #endif
 966
 967         qspi_module_disable(priv, 0);
 968
 969         return 0;
 970 }
 971
 972 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 973 {
 974         struct fdt_resource res_regs, res_mem;
 975         struct fsl_qspi_platdata *plat = bus->platdata;
 976         const void *blob = gd->fdt_blob;
 977         int node = dev_of_offset(bus);
 978         int ret, flash_num = 0, subnode;
 979
 980         if (fdtdec_get_bool(blob, node, "big-endian"))
 981                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 982
 983         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 984                                      "QuadSPI", &res_regs);
 985         if (ret) {
 986                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
 987                 return -ENOMEM;
 988         }
 989         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 990                                      "QuadSPI-memory", &res_mem);
 991         if (ret) {
 992                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
 993                 return -ENOMEM;
 994         }
 995
 996         /* Count flash numbers */
 997         fdt_for_each_subnode(subnode, blob, node)
 998                 ++flash_num;
 999
1000         if (flash_num == 0) {
1001                 debug("Error: Missing flashes!\n");
1002                 return -ENODEV;
1003         }
1004
1005         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1006                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1007         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1008                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1009
1010         plat->reg_base = res_regs.start;
1011         plat->amba_base = res_mem.start;
1012         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1013         plat->flash_num = flash_num;
1014
1015         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1016               __func__,
1017               (u64)plat->reg_base,
1018               (u64)plat->amba_base,
1019               (u64)plat->amba_total_size,
1020               plat->speed_hz,
1021               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1022               );
1023
1024         return 0;
1025 }
1026
1027 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1028                 const void *dout, void *din, unsigned long flags)
1029 {
1030         struct fsl_qspi_priv *priv;
1031         struct udevice *bus;
1032
1033         bus = dev->parent;
1034         priv = dev_get_priv(bus);
1035
1036         return qspi_xfer(priv, bitlen, dout, din, flags);
1037 }
1038
1039 static int fsl_qspi_claim_bus(struct udevice *dev)
1040 {
1041         struct fsl_qspi_priv *priv;
1042         struct udevice *bus;
1043         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1044         int ret;
1045
1046         bus = dev->parent;
1047         priv = dev_get_priv(bus);
1048
1049         /* make sure controller is not busy anywhere */
1050         ret = is_controller_busy(priv);
1051
1052         if (ret) {
1053                 debug("ERROR : The controller is busy\n");
1054                 return ret;
1055         }
1056
1057         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1058
1059         qspi_module_disable(priv, 0);
1060
1061         return 0;
1062 }
1063
1064 static int fsl_qspi_release_bus(struct udevice *dev)
1065 {
1066         struct fsl_qspi_priv *priv;
1067         struct udevice *bus;
1068
1069         bus = dev->parent;
1070         priv = dev_get_priv(bus);
1071
1072         qspi_module_disable(priv, 1);
1073
1074         return 0;
1075 }
1076
1077 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1078 {
1079         /* Nothing to do */
1080         return 0;
1081 }
1082
1083 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1084 {
1085         /* Nothing to do */
1086         return 0;
1087 }
1088
1089 static const struct dm_spi_ops fsl_qspi_ops = {
1090         .claim_bus      = fsl_qspi_claim_bus,
1091         .release_bus    = fsl_qspi_release_bus,
1092         .xfer           = fsl_qspi_xfer,
1093         .set_speed      = fsl_qspi_set_speed,
1094         .set_mode       = fsl_qspi_set_mode,
1095 };
1096
1097 static const struct udevice_id fsl_qspi_ids[] = {
1098         { .compatible = "fsl,vf610-qspi" },
1099         { .compatible = "fsl,imx6sx-qspi" },
1100         { .compatible = "fsl,imx6ul-qspi" },
1101         { .compatible = "fsl,imx7d-qspi" },
1102         { }
1103 };
1104
1105 U_BOOT_DRIVER(fsl_qspi) = {
1106         .name   = "fsl_qspi",
1107         .id     = UCLASS_SPI,
1108         .of_match = fsl_qspi_ids,
1109         .ops    = &fsl_qspi_ops,
1110         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1111         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1112         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1113         .probe  = fsl_qspi_probe,
1114         .child_pre_probe = fsl_qspi_child_pre_probe,
1115 };