1 // SPDX-License-Identifier: GPL-2.0+
4 * Freescale QuadSPI driver.
6 * Copyright (C) 2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2018 Bootlin
8 * Copyright (C) 2018 exceet electronics GmbH
9 * Copyright (C) 2018 Kontron Electronics GmbH
10 * Copyright 2019-2020 NXP
12 * This driver is a ported version of Linux Freescale QSPI driver taken from
13 * v5.5-rc1 tag having following information.
15 * Transition to SPI MEM interface:
17 * Boris Brezillon <bbrezillon@kernel.org>
18 * Frieder Schrempf <frieder.schrempf@kontron.de>
19 * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
20 * Suresh Gupta <suresh.gupta@nxp.com>
22 * Based on the original fsl-quadspi.c spi-nor driver.
23 * Transition to spi-mem in spi-fsl-qspi.c
29 #include <linux/iopoll.h>
30 #include <linux/sizes.h>
31 #include <linux/err.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 * The driver only uses one single LUT entry, that is updated on
39 * each call of exec_op(). Index 0 is preset at boot with a basic
40 * read operation, so let's use the last entry (15).
44 /* Registers used by the driver */
45 #define QUADSPI_MCR 0x00
46 #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
47 #define QUADSPI_MCR_MDIS_MASK BIT(14)
48 #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
49 #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
50 #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
51 #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
52 #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
53 #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
55 #define QUADSPI_IPCR 0x08
56 #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
57 #define QUADSPI_FLSHCR 0x0c
58 #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
59 #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
60 #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
62 #define QUADSPI_BUF3CR 0x1c
63 #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
64 #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
65 #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
67 #define QUADSPI_BFGENCR 0x20
68 #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
70 #define QUADSPI_BUF0IND 0x30
71 #define QUADSPI_BUF1IND 0x34
72 #define QUADSPI_BUF2IND 0x38
73 #define QUADSPI_SFAR 0x100
75 #define QUADSPI_SMPR 0x108
76 #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
77 #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
78 #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
79 #define QUADSPI_SMPR_HSENA_MASK BIT(0)
81 #define QUADSPI_RBCT 0x110
82 #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
83 #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
85 #define QUADSPI_TBDR 0x154
87 #define QUADSPI_SR 0x15c
88 #define QUADSPI_SR_IP_ACC_MASK BIT(1)
89 #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
91 #define QUADSPI_FR 0x160
92 #define QUADSPI_FR_TFF_MASK BIT(0)
94 #define QUADSPI_RSER 0x164
95 #define QUADSPI_RSER_TFIE BIT(0)
97 #define QUADSPI_SPTRCLR 0x16c
98 #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
99 #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
101 #define QUADSPI_SFA1AD 0x180
102 #define QUADSPI_SFA2AD 0x184
103 #define QUADSPI_SFB1AD 0x188
104 #define QUADSPI_SFB2AD 0x18c
105 #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
107 #define QUADSPI_LUTKEY 0x300
108 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
110 #define QUADSPI_LCKCR 0x304
111 #define QUADSPI_LCKER_LOCK BIT(0)
112 #define QUADSPI_LCKER_UNLOCK BIT(1)
114 #define QUADSPI_LUT_BASE 0x310
115 #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
116 #define QUADSPI_LUT_REG(idx) \
117 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
119 /* Instruction set for the LUT register */
127 #define LUT_FSL_READ 7
128 #define LUT_FSL_WRITE 8
129 #define LUT_JMP_ON_CS 9
130 #define LUT_ADDR_DDR 10
131 #define LUT_MODE_DDR 11
132 #define LUT_MODE2_DDR 12
133 #define LUT_MODE4_DDR 13
134 #define LUT_FSL_READ_DDR 14
135 #define LUT_FSL_WRITE_DDR 15
136 #define LUT_DATA_LEARN 16
139 * The PAD definitions for LUT register.
141 * The pad stands for the number of IO lines [0:3].
142 * For example, the quad read needs four IO lines,
143 * so you should use LUT_PAD(4).
145 #define LUT_PAD(x) (fls(x) - 1)
148 * Macro for constructing the LUT entries with the following
151 * ---------------------------------------------------
152 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
153 * ---------------------------------------------------
155 #define LUT_DEF(idx, ins, pad, opr) \
156 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
158 /* Controller needs driver to swap endianness */
159 #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
161 /* Controller needs 4x internal clock */
162 #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
165 * TKT253890, the controller needs the driver to fill the txfifo with
166 * 16 bytes at least to trigger a data transfer, even though the extra
167 * data won't be transferred.
169 #define QUADSPI_QUIRK_TKT253890 BIT(2)
171 /* TKT245618, the controller cannot wake up from wait mode */
172 #define QUADSPI_QUIRK_TKT245618 BIT(3)
175 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
176 * internally. No need to add it when setting SFXXAD and SFAR registers
178 #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
181 * Controller uses TDH bits in register QUADSPI_FLSHCR.
182 * They need to be set in accordance with the DDR/SDR mode.
184 #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
186 struct fsl_qspi_devtype_data {
189 unsigned int ahb_buf_size;
194 static const struct fsl_qspi_devtype_data vybrid_data = {
197 .ahb_buf_size = SZ_1K,
198 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
199 .little_endian = true,
202 static const struct fsl_qspi_devtype_data imx6sx_data = {
205 .ahb_buf_size = SZ_1K,
206 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
207 .little_endian = true,
210 static const struct fsl_qspi_devtype_data imx7d_data = {
213 .ahb_buf_size = SZ_1K,
214 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
215 QUADSPI_QUIRK_USE_TDH_SETTING,
216 .little_endian = true,
219 static const struct fsl_qspi_devtype_data imx6ul_data = {
222 .ahb_buf_size = SZ_1K,
223 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
224 QUADSPI_QUIRK_USE_TDH_SETTING,
225 .little_endian = true,
228 static const struct fsl_qspi_devtype_data ls1021a_data = {
231 .ahb_buf_size = SZ_1K,
233 .little_endian = false,
236 static const struct fsl_qspi_devtype_data ls1088a_data = {
239 .ahb_buf_size = SZ_1K,
240 .quirks = QUADSPI_QUIRK_TKT253890,
241 .little_endian = true,
244 static const struct fsl_qspi_devtype_data ls2080a_data = {
247 .ahb_buf_size = SZ_1K,
248 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
249 .little_endian = true,
254 void __iomem *iobase;
255 void __iomem *ahb_addr;
257 const struct fsl_qspi_devtype_data *devtype_data;
261 static inline int needs_swap_endian(struct fsl_qspi *q)
263 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
266 static inline int needs_4x_clock(struct fsl_qspi *q)
268 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
271 static inline int needs_fill_txfifo(struct fsl_qspi *q)
273 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
276 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
278 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
281 static inline int needs_amba_base_offset(struct fsl_qspi *q)
283 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
286 static inline int needs_tdh_setting(struct fsl_qspi *q)
288 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
292 * An IC bug makes it necessary to rearrange the 32-bit data.
293 * Later chips, such as IMX6SLX, have fixed this bug.
295 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
297 return needs_swap_endian(q) ? __swab32(a) : a;
301 * R/W functions for big- or little-endian registers:
302 * The QSPI controller's endianness is independent of
303 * the CPU core's endianness. So far, although the CPU
304 * core is little-endian the QSPI controller can use
305 * big-endian or little-endian.
307 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
309 if (q->devtype_data->little_endian)
315 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
317 if (q->devtype_data->little_endian)
318 return in_le32(addr);
320 return in_be32(addr);
323 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
335 static bool fsl_qspi_supports_op(struct spi_slave *slave,
336 const struct spi_mem_op *op)
338 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
341 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
344 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
346 if (op->dummy.nbytes)
347 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
350 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
356 * The number of instructions needed for the op, needs
357 * to fit into a single LUT entry.
359 if (op->addr.nbytes +
360 (op->dummy.nbytes ? 1 : 0) +
361 (op->data.nbytes ? 1 : 0) > 6)
364 /* Max 64 dummy clock cycles supported */
365 if (op->dummy.nbytes &&
366 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
369 /* Max data length, check controller limits and alignment */
370 if (op->data.dir == SPI_MEM_DATA_IN &&
371 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
372 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
373 !IS_ALIGNED(op->data.nbytes, 8))))
376 if (op->data.dir == SPI_MEM_DATA_OUT &&
377 op->data.nbytes > q->devtype_data->txfifo)
383 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
384 const struct spi_mem_op *op)
386 void __iomem *base = q->iobase;
390 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
394 * For some unknown reason, using LUT_ADDR doesn't work in some
395 * cases (at least with only one byte long addresses), so
396 * let's use LUT_MODE to write the address bytes one by one
398 for (i = 0; i < op->addr.nbytes; i++) {
399 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
401 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
402 LUT_PAD(op->addr.buswidth),
407 if (op->dummy.nbytes) {
408 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
409 LUT_PAD(op->dummy.buswidth),
410 op->dummy.nbytes * 8 /
415 if (op->data.nbytes) {
416 lutval[lutidx / 2] |= LUT_DEF(lutidx,
417 op->data.dir == SPI_MEM_DATA_IN ?
418 LUT_FSL_READ : LUT_FSL_WRITE,
419 LUT_PAD(op->data.buswidth),
424 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
427 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
428 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
430 dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
431 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
434 for (i = 0; i < ARRAY_SIZE(lutval); i++)
435 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
438 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
439 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
443 * If we have changed the content of the flash by writing or erasing, or if we
444 * read from flash with a different offset into the page buffer, we need to
445 * invalidate the AHB buffer. If we do not do so, we may read out the wrong
446 * data. The spec tells us reset the AHB domain and Serial Flash domain at
449 static void fsl_qspi_invalidate(struct fsl_qspi *q)
453 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
454 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
455 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
458 * The minimum delay : 1 AHB + 2 SFCK clocks.
459 * Delay 1 us is enough.
463 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
464 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
467 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
469 struct dm_spi_slave_platdata *plat =
470 dev_get_parent_platdata(slave->dev);
472 if (q->selected == plat->cs)
475 q->selected = plat->cs;
476 fsl_qspi_invalidate(q);
479 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
481 memcpy_fromio(op->data.buf.in,
482 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
486 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
487 const struct spi_mem_op *op)
489 void __iomem *base = q->iobase;
493 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
494 memcpy(&val, op->data.buf.out + i, 4);
495 val = fsl_qspi_endian_xchg(q, val);
496 qspi_writel(q, val, base + QUADSPI_TBDR);
499 if (i < op->data.nbytes) {
500 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
501 val = fsl_qspi_endian_xchg(q, val);
502 qspi_writel(q, val, base + QUADSPI_TBDR);
505 if (needs_fill_txfifo(q)) {
506 for (i = op->data.nbytes; i < 16; i += 4)
507 qspi_writel(q, 0, base + QUADSPI_TBDR);
511 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
512 const struct spi_mem_op *op)
514 void __iomem *base = q->iobase;
516 u8 *buf = op->data.buf.in;
519 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
520 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
521 val = fsl_qspi_endian_xchg(q, val);
522 memcpy(buf + i, &val, 4);
525 if (i < op->data.nbytes) {
526 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
527 val = fsl_qspi_endian_xchg(q, val);
528 memcpy(buf + i, &val, op->data.nbytes - i);
532 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
533 u32 mask, u32 delay_us, u32 timeout_us)
537 if (!q->devtype_data->little_endian)
538 mask = (u32)cpu_to_be32(mask);
540 return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
543 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
545 void __iomem *base = q->iobase;
549 * Always start the sequence at the same index since we update
550 * the LUT at each exec_op() call. And also specify the DATA
551 * length, since it's has not been specified in the LUT.
553 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
554 base + QUADSPI_IPCR);
556 /* wait for the controller being ready */
557 err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
558 (QUADSPI_SR_IP_ACC_MASK |
559 QUADSPI_SR_AHB_ACC_MASK),
562 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
563 fsl_qspi_read_rxfifo(q, op);
568 static int fsl_qspi_exec_op(struct spi_slave *slave,
569 const struct spi_mem_op *op)
571 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
572 void __iomem *base = q->iobase;
576 /* wait for the controller being ready */
577 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
578 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
580 fsl_qspi_select_mem(q, slave);
582 if (needs_amba_base_offset(q))
583 addr_offset = q->memmap_phy;
586 q->selected * q->devtype_data->ahb_buf_size + addr_offset,
587 base + QUADSPI_SFAR);
589 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
590 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
593 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
594 base + QUADSPI_SPTRCLR);
596 fsl_qspi_prepare_lut(q, op);
599 * If we have large chunks of data, we read them through the AHB bus
600 * by accessing the mapped memory. In all other cases we use
601 * IP commands to access the flash.
603 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
604 op->data.dir == SPI_MEM_DATA_IN) {
605 fsl_qspi_read_ahb(q, op);
607 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
608 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
610 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
611 fsl_qspi_fill_txfifo(q, op);
613 err = fsl_qspi_do_op(q, op);
616 /* Invalidate the data in the AHB buffer. */
617 fsl_qspi_invalidate(q);
622 static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
623 struct spi_mem_op *op)
625 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
627 if (op->data.dir == SPI_MEM_DATA_OUT) {
628 if (op->data.nbytes > q->devtype_data->txfifo)
629 op->data.nbytes = q->devtype_data->txfifo;
631 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
632 op->data.nbytes = q->devtype_data->ahb_buf_size;
633 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
634 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
640 static int fsl_qspi_default_setup(struct fsl_qspi *q)
642 void __iomem *base = q->iobase;
643 u32 reg, addr_offset = 0;
645 /* Reset the module */
646 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
650 /* Disable the module */
651 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
655 * Previous boot stages (BootROM, bootloader) might have used DDR
656 * mode and did not clear the TDH bits. As we currently use SDR mode
657 * only, clear the TDH bits if necessary.
659 if (needs_tdh_setting(q))
660 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
661 ~QUADSPI_FLSHCR_TDH_MASK,
662 base + QUADSPI_FLSHCR);
664 reg = qspi_readl(q, base + QUADSPI_SMPR);
665 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
666 | QUADSPI_SMPR_FSPHS_MASK
667 | QUADSPI_SMPR_HSENA_MASK
668 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
670 /* We only use the buffer3 for AHB read */
671 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
672 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
673 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
675 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
676 q->iobase + QUADSPI_BFGENCR);
677 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
678 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
679 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
680 base + QUADSPI_BUF3CR);
682 if (needs_amba_base_offset(q))
683 addr_offset = q->memmap_phy;
686 * In HW there can be a maximum of four chips on two buses with
687 * two chip selects on each bus. We use four chip selects in SW
688 * to differentiate between the four chips.
689 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
690 * SFB2AD accordingly.
692 qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
693 base + QUADSPI_SFA1AD);
694 qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
695 base + QUADSPI_SFA2AD);
696 qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
697 base + QUADSPI_SFB1AD);
698 qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
699 base + QUADSPI_SFB2AD);
703 /* Enable the module */
704 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
709 static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
710 .adjust_op_size = fsl_qspi_adjust_op_size,
711 .supports_op = fsl_qspi_supports_op,
712 .exec_op = fsl_qspi_exec_op,
715 static int fsl_qspi_probe(struct udevice *bus)
717 struct dm_spi_bus *dm_bus = bus->uclass_priv;
718 struct fsl_qspi *q = dev_get_priv(bus);
719 const void *blob = gd->fdt_blob;
720 int node = dev_of_offset(bus);
721 struct fdt_resource res;
725 q->devtype_data = (struct fsl_qspi_devtype_data *)
726 dev_get_driver_data(bus);
728 /* find the resources */
729 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
732 dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
736 q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
738 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
739 "QuadSPI-memory", &res);
741 dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
745 q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
746 q->memmap_phy = res.start;
748 dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
751 fsl_qspi_default_setup(q);
756 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
757 const void *dout, void *din, unsigned long flags)
762 static int fsl_qspi_claim_bus(struct udevice *dev)
767 static int fsl_qspi_release_bus(struct udevice *dev)
772 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
777 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
782 static const struct dm_spi_ops fsl_qspi_ops = {
783 .claim_bus = fsl_qspi_claim_bus,
784 .release_bus = fsl_qspi_release_bus,
785 .xfer = fsl_qspi_xfer,
786 .set_speed = fsl_qspi_set_speed,
787 .set_mode = fsl_qspi_set_mode,
788 .mem_ops = &fsl_qspi_mem_ops,
791 static const struct udevice_id fsl_qspi_ids[] = {
792 { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
793 { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
794 { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
795 { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
796 { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
797 { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
798 { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
802 U_BOOT_DRIVER(fsl_qspi) = {
805 .of_match = fsl_qspi_ids,
806 .ops = &fsl_qspi_ops,
807 .priv_auto_alloc_size = sizeof(struct fsl_qspi),
808 .probe = fsl_qspi_probe,