drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15 #include <watchdog.h>
  16 #include <wait_bit.h>
  17 #include "fsl_qspi.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define RX_BUFFER_SIZE          0x80
  22 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
  23         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
  24 #define TX_BUFFER_SIZE          0x200
  25 #else
  26 #define TX_BUFFER_SIZE          0x40
  27 #endif
  28
  29 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  30
  31 #define FLASH_STATUS_WEL        0x02
  32
  33 /* SEQID */
  34 #define SEQID_WREN              1
  35 #define SEQID_FAST_READ         2
  36 #define SEQID_RDSR              3
  37 #define SEQID_SE                4
  38 #define SEQID_CHIP_ERASE        5
  39 #define SEQID_PP                6
  40 #define SEQID_RDID              7
  41 #define SEQID_BE_4K             8
  42 #ifdef CONFIG_SPI_FLASH_BAR
  43 #define SEQID_BRRD              9
  44 #define SEQID_BRWR              10
  45 #define SEQID_RDEAR             11
  46 #define SEQID_WREAR             12
  47 #endif
  48 #define SEQID_WRAR              13
  49 #define SEQID_RDAR              14
  50
  51 /* QSPI CMD */
  52 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  53 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  54 #define QSPI_CMD_WREN           0x06    /* Write enable */
  55 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  56 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  57 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  58 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  59 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  60
  61 /* Used for Micron, winbond and Macronix flashes */
  62 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  63 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  64
  65 /* Used for Spansion flashes only. */
  66 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  67 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  68
  69 /* Used for Spansion S25FS-S family flash only. */
  70 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  71 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  72
  73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  74 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  75 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  76 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  77
  78 /* fsl_qspi_platdata flags */
  79 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  80
  81 /* default SCK frequency, unit: HZ */
  82 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  83
  84 /* QSPI max chipselect signals number */
  85 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  86
  87 #ifdef CONFIG_DM_SPI
  88 /**
  89  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  90  *
  91  * @flags: Flags for QSPI QSPI_FLAG_...
  92  * @speed_hz: Default SCK frequency
  93  * @reg_base: Base address of QSPI registers
  94  * @amba_base: Base address of QSPI memory mapping
  95  * @amba_total_size: size of QSPI memory mapping
  96  * @flash_num: Number of active slave devices
  97  * @num_chipselect: Number of QSPI chipselect signals
  98  */
  99 struct fsl_qspi_platdata {
 100         u32 flags;
 101         u32 speed_hz;
 102         fdt_addr_t reg_base;
 103         fdt_addr_t amba_base;
 104         fdt_size_t amba_total_size;
 105         u32 flash_num;
 106         u32 num_chipselect;
 107 };
 108 #endif
 109
 110 /**
 111  * struct fsl_qspi_priv - private data for Freescale QSPI
 112  *
 113  * @flags: Flags for QSPI QSPI_FLAG_...
 114  * @bus_clk: QSPI input clk frequency
 115  * @speed_hz: Default SCK frequency
 116  * @cur_seqid: current LUT table sequence id
 117  * @sf_addr: flash access offset
 118  * @amba_base: Base address of QSPI memory mapping of every CS
 119  * @amba_total_size: size of QSPI memory mapping
 120  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 121  * @flash_num: Number of active slave devices
 122  * @num_chipselect: Number of QSPI chipselect signals
 123  * @regs: Point to QSPI register structure for I/O access
 124  */
 125 struct fsl_qspi_priv {
 126         u32 flags;
 127         u32 bus_clk;
 128         u32 speed_hz;
 129         u32 cur_seqid;
 130         u32 sf_addr;
 131         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 132         u32 amba_total_size;
 133         u32 cur_amba_base;
 134         u32 flash_num;
 135         u32 num_chipselect;
 136         struct fsl_qspi_regs *regs;
 137 };
 138
 139 #ifndef CONFIG_DM_SPI
 140 struct fsl_qspi {
 141         struct spi_slave slave;
 142         struct fsl_qspi_priv priv;
 143 };
 144 #endif
 145
 146 static u32 qspi_read32(u32 flags, u32 *addr)
 147 {
 148         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 149                 in_be32(addr) : in_le32(addr);
 150 }
 151
 152 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 153 {
 154         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 155                 out_be32(addr, val) : out_le32(addr, val);
 156 }
 157
 158 /* QSPI support swapping the flash read/write data
 159  * in hardware for LS102xA, but not for VF610 */
 160 static inline u32 qspi_endian_xchg(u32 data)
 161 {
 162 #ifdef CONFIG_VF610
 163         return swab32(data);
 164 #else
 165         return data;
 166 #endif
 167 }
 168
 169 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 170 {
 171         struct fsl_qspi_regs *regs = priv->regs;
 172         u32 lut_base;
 173
 174         /* Unlock the LUT */
 175         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 176         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 177
 178         /* Write Enable */
 179         lut_base = SEQID_WREN * 4;
 180         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 181                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 182         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 183         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 184         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 185
 186         /* Fast Read */
 187         lut_base = SEQID_FAST_READ * 4;
 188 #ifdef CONFIG_SPI_FLASH_BAR
 189         qspi_write32(priv->flags, &regs->lut[lut_base],
 190                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 191                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 192                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 193 #else
 194         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 195                 qspi_write32(priv->flags, &regs->lut[lut_base],
 196                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 197                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 198                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 199         else
 200                 qspi_write32(priv->flags, &regs->lut[lut_base],
 201                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 202                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 203                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 204                              INSTR1(LUT_ADDR));
 205 #endif
 206         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 207                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 208                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 209                      INSTR1(LUT_READ));
 210         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 211         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 212
 213         /* Read Status */
 214         lut_base = SEQID_RDSR * 4;
 215         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 216                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 217                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 218         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 219         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 220         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 221
 222         /* Erase a sector */
 223         lut_base = SEQID_SE * 4;
 224 #ifdef CONFIG_SPI_FLASH_BAR
 225         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 226                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 227                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 228 #else
 229         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 230                 qspi_write32(priv->flags, &regs->lut[lut_base],
 231                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 232                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 233                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 234         else
 235                 qspi_write32(priv->flags, &regs->lut[lut_base],
 236                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 237                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 238                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 239 #endif
 240         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 241         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 242         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 243
 244         /* Erase the whole chip */
 245         lut_base = SEQID_CHIP_ERASE * 4;
 246         qspi_write32(priv->flags, &regs->lut[lut_base],
 247                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 248                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 249         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 250         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 251         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 252
 253         /* Page Program */
 254         lut_base = SEQID_PP * 4;
 255 #ifdef CONFIG_SPI_FLASH_BAR
 256         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 257                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 258                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 259 #else
 260         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 261                 qspi_write32(priv->flags, &regs->lut[lut_base],
 262                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 263                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 264                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 265         else
 266                 qspi_write32(priv->flags, &regs->lut[lut_base],
 267                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 268                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 269                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 270 #endif
 271 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
 272         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
 273         /*
 274          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 275          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 276          */
 277         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 278                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 279 #else
 280         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 281                      OPRND0(TX_BUFFER_SIZE) |
 282                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 283 #endif
 284         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 285         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 286
 287         /* READ ID */
 288         lut_base = SEQID_RDID * 4;
 289         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 290                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 291                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 292         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 293         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 294         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 295
 296         /* SUB SECTOR 4K ERASE */
 297         lut_base = SEQID_BE_4K * 4;
 298         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 299                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 300                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 301
 302 #ifdef CONFIG_SPI_FLASH_BAR
 303         /*
 304          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 305          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 306          * initialization.
 307          */
 308         lut_base = SEQID_BRRD * 4;
 309         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 310                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 311                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 312
 313         lut_base = SEQID_BRWR * 4;
 314         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 315                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 316                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 317
 318         lut_base = SEQID_RDEAR * 4;
 319         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 320                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 321                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 322
 323         lut_base = SEQID_WREAR * 4;
 324         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 325                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 326                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 327 #endif
 328
 329         /*
 330          * Read any device register.
 331          * Used for Spansion S25FS-S family flash only.
 332          */
 333         lut_base = SEQID_RDAR * 4;
 334         qspi_write32(priv->flags, &regs->lut[lut_base],
 335                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 336                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 337                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 338         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 339                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 340                      OPRND1(1) | PAD1(LUT_PAD1) |
 341                      INSTR1(LUT_READ));
 342
 343         /*
 344          * Write any device register.
 345          * Used for Spansion S25FS-S family flash only.
 346          */
 347         lut_base = SEQID_WRAR * 4;
 348         qspi_write32(priv->flags, &regs->lut[lut_base],
 349                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 350                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 351                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 352         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 353                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 354
 355         /* Lock the LUT */
 356         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 357         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 358 }
 359
 360 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 361 /*
 362  * If we have changed the content of the flash by writing or erasing,
 363  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 364  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 365  * domain at the same time.
 366  */
 367 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 368 {
 369         struct fsl_qspi_regs *regs = priv->regs;
 370         u32 reg;
 371
 372         reg = qspi_read32(priv->flags, &regs->mcr);
 373         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 374         qspi_write32(priv->flags, &regs->mcr, reg);
 375
 376         /*
 377          * The minimum delay : 1 AHB + 2 SFCK clocks.
 378          * Delay 1 us is enough.
 379          */
 380         udelay(1);
 381
 382         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 383         qspi_write32(priv->flags, &regs->mcr, reg);
 384 }
 385
 386 /* Read out the data from the AHB buffer. */
 387 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 388 {
 389         struct fsl_qspi_regs *regs = priv->regs;
 390         u32 mcr_reg;
 391         void *rx_addr = NULL;
 392
 393         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 394
 395         qspi_write32(priv->flags, &regs->mcr,
 396                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 397                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 398
 399         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 400         /* Read out the data directly from the AHB buffer. */
 401         memcpy(rxbuf, rx_addr, len);
 402
 403         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 404 }
 405
 406 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 407 {
 408         u32 reg, reg2;
 409         struct fsl_qspi_regs *regs = priv->regs;
 410
 411         reg = qspi_read32(priv->flags, &regs->mcr);
 412         /* Disable the module */
 413         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 414
 415         /* Set the Sampling Register for DDR */
 416         reg2 = qspi_read32(priv->flags, &regs->smpr);
 417         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 418         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 419         qspi_write32(priv->flags, &regs->smpr, reg2);
 420
 421         /* Enable the module again (enable the DDR too) */
 422         reg |= QSPI_MCR_DDR_EN_MASK;
 423         /* Enable bit 29 for imx6sx */
 424         reg |= BIT(29);
 425
 426         qspi_write32(priv->flags, &regs->mcr, reg);
 427 }
 428
 429 /*
 430  * There are two different ways to read out the data from the flash:
 431  *  the "IP Command Read" and the "AHB Command Read".
 432  *
 433  * The IC guy suggests we use the "AHB Command Read" which is faster
 434  * then the "IP Command Read". (What's more is that there is a bug in
 435  * the "IP Command Read" in the Vybrid.)
 436  *
 437  * After we set up the registers for the "AHB Command Read", we can use
 438  * the memcpy to read the data directly. A "missed" access to the buffer
 439  * causes the controller to clear the buffer, and use the sequence pointed
 440  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 441  */
 442 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 443 {
 444         struct fsl_qspi_regs *regs = priv->regs;
 445
 446         /* AHB configuration for access buffer 0/1/2 .*/
 447         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 448         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 449         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 450         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 451                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 452
 453         /* We only use the buffer3 */
 454         qspi_write32(priv->flags, &regs->buf0ind, 0);
 455         qspi_write32(priv->flags, &regs->buf1ind, 0);
 456         qspi_write32(priv->flags, &regs->buf2ind, 0);
 457
 458         /*
 459          * Set the default lut sequence for AHB Read.
 460          * Parallel mode is disabled.
 461          */
 462         qspi_write32(priv->flags, &regs->bfgencr,
 463                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 464
 465         /*Enable DDR Mode*/
 466         qspi_enable_ddr_mode(priv);
 467 }
 468 #endif
 469
 470 #ifdef CONFIG_SPI_FLASH_BAR
 471 /* Bank register read/write, EAR register read/write */
 472 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 473 {
 474         struct fsl_qspi_regs *regs = priv->regs;
 475         u32 reg, mcr_reg, data, seqid;
 476
 477         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 478         qspi_write32(priv->flags, &regs->mcr,
 479                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 480                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 481         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 482
 483         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 484
 485         if (priv->cur_seqid == QSPI_CMD_BRRD)
 486                 seqid = SEQID_BRRD;
 487         else
 488                 seqid = SEQID_RDEAR;
 489
 490         qspi_write32(priv->flags, &regs->ipcr,
 491                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 492
 493         /* Wait previous command complete */
 494         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 495                 ;
 496
 497         while (1) {
 498                 WATCHDOG_RESET();
 499
 500                 reg = qspi_read32(priv->flags, &regs->rbsr);
 501                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 502                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 503                         data = qspi_endian_xchg(data);
 504                         memcpy(rxbuf, &data, len);
 505                         qspi_write32(priv->flags, &regs->mcr,
 506                                      qspi_read32(priv->flags, &regs->mcr) |
 507                                      QSPI_MCR_CLR_RXF_MASK);
 508                         break;
 509                 }
 510         }
 511
 512         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 513 }
 514 #endif
 515
 516 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 517 {
 518         struct fsl_qspi_regs *regs = priv->regs;
 519         u32 mcr_reg, rbsr_reg, data, size;
 520         int i;
 521
 522         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 523         qspi_write32(priv->flags, &regs->mcr,
 524                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 525                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 526         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 527
 528         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 529
 530         qspi_write32(priv->flags, &regs->ipcr,
 531                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 532         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 533                 ;
 534
 535         i = 0;
 536         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 537                 WATCHDOG_RESET();
 538
 539                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 540                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 541                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 542                         data = qspi_endian_xchg(data);
 543                         size = (len < 4) ? len : 4;
 544                         memcpy(rxbuf, &data, size);
 545                         len -= size;
 546                         rxbuf++;
 547                         i++;
 548                 }
 549         }
 550
 551         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 552 }
 553
 554 /* If not use AHB read, read data from ip interface */
 555 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 556 {
 557         struct fsl_qspi_regs *regs = priv->regs;
 558         u32 mcr_reg, data;
 559         int i, size;
 560         u32 to_or_from;
 561         u32 seqid;
 562
 563         if (priv->cur_seqid == QSPI_CMD_RDAR)
 564                 seqid = SEQID_RDAR;
 565         else
 566                 seqid = SEQID_FAST_READ;
 567
 568         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 569         qspi_write32(priv->flags, &regs->mcr,
 570                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 571                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 572         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 573
 574         to_or_from = priv->sf_addr + priv->cur_amba_base;
 575
 576         while (len > 0) {
 577                 WATCHDOG_RESET();
 578
 579                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 580
 581                 size = (len > RX_BUFFER_SIZE) ?
 582                         RX_BUFFER_SIZE : len;
 583
 584                 qspi_write32(priv->flags, &regs->ipcr,
 585                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 586                              size);
 587                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 588                         ;
 589
 590                 to_or_from += size;
 591                 len -= size;
 592
 593                 i = 0;
 594                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 595                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 596                         data = qspi_endian_xchg(data);
 597                         if (size < 4)
 598                                 memcpy(rxbuf, &data, size);
 599                         else
 600                                 memcpy(rxbuf, &data, 4);
 601                         rxbuf++;
 602                         size -= 4;
 603                         i++;
 604                 }
 605                 qspi_write32(priv->flags, &regs->mcr,
 606                              qspi_read32(priv->flags, &regs->mcr) |
 607                              QSPI_MCR_CLR_RXF_MASK);
 608         }
 609
 610         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 611 }
 612
 613 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 614 {
 615         struct fsl_qspi_regs *regs = priv->regs;
 616         u32 mcr_reg, data, reg, status_reg, seqid;
 617         int i, size, tx_size;
 618         u32 to_or_from = 0;
 619
 620         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 621         qspi_write32(priv->flags, &regs->mcr,
 622                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 623                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 624         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 625
 626         status_reg = 0;
 627         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 628                 WATCHDOG_RESET();
 629
 630                 qspi_write32(priv->flags, &regs->ipcr,
 631                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 632                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 633                         ;
 634
 635                 qspi_write32(priv->flags, &regs->ipcr,
 636                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 637                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 638                         ;
 639
 640                 reg = qspi_read32(priv->flags, &regs->rbsr);
 641                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 642                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 643                         status_reg = qspi_endian_xchg(status_reg);
 644                 }
 645                 qspi_write32(priv->flags, &regs->mcr,
 646                              qspi_read32(priv->flags, &regs->mcr) |
 647                              QSPI_MCR_CLR_RXF_MASK);
 648         }
 649
 650         /* Default is page programming */
 651         seqid = SEQID_PP;
 652         if (priv->cur_seqid == QSPI_CMD_WRAR)
 653                 seqid = SEQID_WRAR;
 654 #ifdef CONFIG_SPI_FLASH_BAR
 655         if (priv->cur_seqid == QSPI_CMD_BRWR)
 656                 seqid = SEQID_BRWR;
 657         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 658                 seqid = SEQID_WREAR;
 659 #endif
 660
 661         to_or_from = priv->sf_addr + priv->cur_amba_base;
 662
 663         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 664
 665         tx_size = (len > TX_BUFFER_SIZE) ?
 666                 TX_BUFFER_SIZE : len;
 667
 668         size = tx_size / 16;
 669         /*
 670          * There must be atleast 128bit data
 671          * available in TX FIFO for any pop operation
 672          */
 673         if (tx_size % 16)
 674                 size++;
 675         for (i = 0; i < size * 4; i++) {
 676                 memcpy(&data, txbuf, 4);
 677                 data = qspi_endian_xchg(data);
 678                 qspi_write32(priv->flags, &regs->tbdr, data);
 679                 txbuf += 4;
 680         }
 681
 682         qspi_write32(priv->flags, &regs->ipcr,
 683                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 684         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 685                 ;
 686
 687         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 688 }
 689
 690 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 691 {
 692         struct fsl_qspi_regs *regs = priv->regs;
 693         u32 mcr_reg, reg, data;
 694
 695         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 696         qspi_write32(priv->flags, &regs->mcr,
 697                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 698                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 699         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 700
 701         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 702
 703         qspi_write32(priv->flags, &regs->ipcr,
 704                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 705         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 706                 ;
 707
 708         while (1) {
 709                 WATCHDOG_RESET();
 710
 711                 reg = qspi_read32(priv->flags, &regs->rbsr);
 712                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 713                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 714                         data = qspi_endian_xchg(data);
 715                         memcpy(rxbuf, &data, len);
 716                         qspi_write32(priv->flags, &regs->mcr,
 717                                      qspi_read32(priv->flags, &regs->mcr) |
 718                                      QSPI_MCR_CLR_RXF_MASK);
 719                         break;
 720                 }
 721         }
 722
 723         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 724 }
 725
 726 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 727 {
 728         struct fsl_qspi_regs *regs = priv->regs;
 729         u32 mcr_reg;
 730         u32 to_or_from = 0;
 731
 732         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 733         qspi_write32(priv->flags, &regs->mcr,
 734                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 735                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 736         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 737
 738         to_or_from = priv->sf_addr + priv->cur_amba_base;
 739         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 740
 741         qspi_write32(priv->flags, &regs->ipcr,
 742                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 743         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 744                 ;
 745
 746         if (priv->cur_seqid == QSPI_CMD_SE) {
 747                 qspi_write32(priv->flags, &regs->ipcr,
 748                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 749         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 750                 qspi_write32(priv->flags, &regs->ipcr,
 751                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 752         }
 753         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 754                 ;
 755
 756         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 757 }
 758
 759 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 760                 const void *dout, void *din, unsigned long flags)
 761 {
 762         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 763         static u32 wr_sfaddr;
 764         u32 txbuf;
 765
 766         WATCHDOG_RESET();
 767
 768         if (dout) {
 769                 if (flags & SPI_XFER_BEGIN) {
 770                         priv->cur_seqid = *(u8 *)dout;
 771                         memcpy(&txbuf, dout, 4);
 772                 }
 773
 774                 if (flags == SPI_XFER_END) {
 775                         priv->sf_addr = wr_sfaddr;
 776                         qspi_op_write(priv, (u8 *)dout, bytes);
 777                         return 0;
 778                 }
 779
 780                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 781                     priv->cur_seqid == QSPI_CMD_RDAR) {
 782                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 783                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 784                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 785                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 786                         qspi_op_erase(priv);
 787                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 788                            priv->cur_seqid == QSPI_CMD_WRAR) {
 789                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 790                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 791                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 792 #ifdef CONFIG_SPI_FLASH_BAR
 793                         wr_sfaddr = 0;
 794 #endif
 795                 }
 796         }
 797
 798         if (din) {
 799                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 800 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 801                         qspi_ahb_read(priv, din, bytes);
 802 #else
 803                         qspi_op_read(priv, din, bytes);
 804 #endif
 805                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 806                         qspi_op_read(priv, din, bytes);
 807                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 808                         qspi_op_rdid(priv, din, bytes);
 809                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 810                         qspi_op_rdsr(priv, din, bytes);
 811 #ifdef CONFIG_SPI_FLASH_BAR
 812                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 813                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 814                         priv->sf_addr = 0;
 815                         qspi_op_rdbank(priv, din, bytes);
 816                 }
 817 #endif
 818         }
 819
 820 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 821         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 822             (priv->cur_seqid == QSPI_CMD_PP) ||
 823             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 824             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 825             (priv->cur_seqid == QSPI_CMD_BRWR))
 826                 qspi_ahb_invalid(priv);
 827 #endif
 828
 829         return 0;
 830 }
 831
 832 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 833 {
 834         u32 mcr_val;
 835
 836         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 837         if (disable)
 838                 mcr_val |= QSPI_MCR_MDIS_MASK;
 839         else
 840                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 841         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 842 }
 843
 844 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 845 {
 846         u32 smpr_val;
 847
 848         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 849         smpr_val &= ~clear_bits;
 850         smpr_val |= set_bits;
 851         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 852 }
 853 #ifndef CONFIG_DM_SPI
 854 static unsigned long spi_bases[] = {
 855         QSPI0_BASE_ADDR,
 856 #ifdef CONFIG_MX6SX
 857         QSPI1_BASE_ADDR,
 858 #endif
 859 };
 860
 861 static unsigned long amba_bases[] = {
 862         QSPI0_AMBA_BASE,
 863 #ifdef CONFIG_MX6SX
 864         QSPI1_AMBA_BASE,
 865 #endif
 866 };
 867
 868 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
 869 {
 870         return container_of(slave, struct fsl_qspi, slave);
 871 }
 872
 873 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 874                 unsigned int max_hz, unsigned int mode)
 875 {
 876         u32 mcr_val;
 877         struct fsl_qspi *qspi;
 878         struct fsl_qspi_regs *regs;
 879         u32 total_size;
 880
 881         if (bus >= ARRAY_SIZE(spi_bases))
 882                 return NULL;
 883
 884         if (cs >= FSL_QSPI_FLASH_NUM)
 885                 return NULL;
 886
 887         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
 888         if (!qspi)
 889                 return NULL;
 890
 891 #ifdef CONFIG_SYS_FSL_QSPI_BE
 892         qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 893 #endif
 894
 895         regs = (struct fsl_qspi_regs *)spi_bases[bus];
 896         qspi->priv.regs = regs;
 897         /*
 898          * According cs, use different amba_base to choose the
 899          * corresponding flash devices.
 900          *
 901          * If not, only one flash device is used even if passing
 902          * different cs using `sf probe`
 903          */
 904         qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 905
 906         qspi->slave.max_write_size = TX_BUFFER_SIZE;
 907
 908         mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
 909
 910         /* Set endianness to LE for i.mx */
 911         if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
 912                 mcr_val = QSPI_MCR_END_CFD_LE;
 913
 914         qspi_write32(qspi->priv.flags, &regs->mcr,
 915                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 916                      (mcr_val & QSPI_MCR_END_CFD_MASK));
 917
 918         qspi_cfg_smpr(&qspi->priv,
 919                       ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 920                       QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 921
 922         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 923         /*
 924          * Any read access to non-implemented addresses will provide
 925          * undefined results.
 926          *
 927          * In case single die flash devices, TOP_ADDR_MEMA2 and
 928          * TOP_ADDR_MEMB2 should be initialized/programmed to
 929          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 930          * setting the size of these devices to 0.  This would ensure
 931          * that the complete memory map is assigned to only one flash device.
 932          */
 933         qspi_write32(qspi->priv.flags, &regs->sfa1ad,
 934                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 935         qspi_write32(qspi->priv.flags, &regs->sfa2ad,
 936                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 937         qspi_write32(qspi->priv.flags, &regs->sfb1ad,
 938                      total_size | amba_bases[bus]);
 939         qspi_write32(qspi->priv.flags, &regs->sfb2ad,
 940                      total_size | amba_bases[bus]);
 941
 942         qspi_set_lut(&qspi->priv);
 943
 944 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 945         qspi_init_ahb_read(&qspi->priv);
 946 #endif
 947
 948         qspi_module_disable(&qspi->priv, 0);
 949
 950         return &qspi->slave;
 951 }
 952
 953 void spi_free_slave(struct spi_slave *slave)
 954 {
 955         struct fsl_qspi *qspi = to_qspi_spi(slave);
 956
 957         free(qspi);
 958 }
 959
 960 int spi_claim_bus(struct spi_slave *slave)
 961 {
 962         return 0;
 963 }
 964
 965 void spi_release_bus(struct spi_slave *slave)
 966 {
 967         /* Nothing to do */
 968 }
 969
 970 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 971                 const void *dout, void *din, unsigned long flags)
 972 {
 973         struct fsl_qspi *qspi = to_qspi_spi(slave);
 974
 975         return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
 976 }
 977
 978 void spi_init(void)
 979 {
 980         /* Nothing to do */
 981 }
 982 #else
 983 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 984 {
 985         struct spi_slave *slave = dev_get_parent_priv(dev);
 986
 987         slave->max_write_size = TX_BUFFER_SIZE;
 988
 989         return 0;
 990 }
 991
 992 static int fsl_qspi_probe(struct udevice *bus)
 993 {
 994         u32 mcr_val;
 995         u32 amba_size_per_chip;
 996         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 997         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 998         struct dm_spi_bus *dm_spi_bus;
 999         int i, ret;
1000
1001         dm_spi_bus = bus->uclass_priv;
1002
1003         dm_spi_bus->max_hz = plat->speed_hz;
1004
1005         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
1006         priv->flags = plat->flags;
1007
1008         priv->speed_hz = plat->speed_hz;
1009         /*
1010          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
1011          * AMBA memory zone should be located on the 0~4GB space
1012          * even on a 64bits cpu.
1013          */
1014         priv->amba_base[0] = (u32)plat->amba_base;
1015         priv->amba_total_size = (u32)plat->amba_total_size;
1016         priv->flash_num = plat->flash_num;
1017         priv->num_chipselect = plat->num_chipselect;
1018
1019         /* make sure controller is not busy anywhere */
1020         ret = wait_for_bit_le32(&priv->regs->sr,
1021                                 QSPI_SR_BUSY_MASK |
1022                                 QSPI_SR_AHB_ACC_MASK |
1023                                 QSPI_SR_IP_ACC_MASK,
1024                                 false, 100, false);
1025
1026         if (ret) {
1027                 debug("ERROR : The controller is busy\n");
1028                 return ret;
1029         }
1030
1031         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
1032
1033         /* Set endianness to LE for i.mx */
1034         if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
1035                 mcr_val = QSPI_MCR_END_CFD_LE;
1036
1037         qspi_write32(priv->flags, &priv->regs->mcr,
1038                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
1039                      (mcr_val & QSPI_MCR_END_CFD_MASK));
1040
1041         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1042                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1043
1044         /*
1045          * Assign AMBA memory zone for every chipselect
1046          * QuadSPI has two channels, every channel has two chipselects.
1047          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1048          * into two parts and assign to every channel. This indicate that every
1049          * channel only has one valid chipselect.
1050          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1051          * into four parts and assign to every chipselect.
1052          * Every channel will has two valid chipselects.
1053          */
1054         amba_size_per_chip = priv->amba_total_size >>
1055                              (priv->num_chipselect >> 1);
1056         for (i = 1 ; i < priv->num_chipselect ; i++)
1057                 priv->amba_base[i] =
1058                         amba_size_per_chip + priv->amba_base[i - 1];
1059
1060         /*
1061          * Any read access to non-implemented addresses will provide
1062          * undefined results.
1063          *
1064          * In case single die flash devices, TOP_ADDR_MEMA2 and
1065          * TOP_ADDR_MEMB2 should be initialized/programmed to
1066          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1067          * setting the size of these devices to 0.  This would ensure
1068          * that the complete memory map is assigned to only one flash device.
1069          */
1070         qspi_write32(priv->flags, &priv->regs->sfa1ad,
1071                      priv->amba_base[0] + amba_size_per_chip);
1072         switch (priv->num_chipselect) {
1073         case 1:
1074                 break;
1075         case 2:
1076                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1077                              priv->amba_base[1]);
1078                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1079                              priv->amba_base[1] + amba_size_per_chip);
1080                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1081                              priv->amba_base[1] + amba_size_per_chip);
1082                 break;
1083         case 4:
1084                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1085                              priv->amba_base[2]);
1086                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1087                              priv->amba_base[3]);
1088                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1089                              priv->amba_base[3] + amba_size_per_chip);
1090                 break;
1091         default:
1092                 debug("Error: Unsupported chipselect number %u!\n",
1093                       priv->num_chipselect);
1094                 qspi_module_disable(priv, 1);
1095                 return -EINVAL;
1096         }
1097
1098         qspi_set_lut(priv);
1099
1100 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1101         qspi_init_ahb_read(priv);
1102 #endif
1103
1104         qspi_module_disable(priv, 0);
1105
1106         return 0;
1107 }
1108
1109 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1110 {
1111         struct fdt_resource res_regs, res_mem;
1112         struct fsl_qspi_platdata *plat = bus->platdata;
1113         const void *blob = gd->fdt_blob;
1114         int node = dev_of_offset(bus);
1115         int ret, flash_num = 0, subnode;
1116
1117         if (fdtdec_get_bool(blob, node, "big-endian"))
1118                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1119
1120         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1121                                      "QuadSPI", &res_regs);
1122         if (ret) {
1123                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1124                 return -ENOMEM;
1125         }
1126         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1127                                      "QuadSPI-memory", &res_mem);
1128         if (ret) {
1129                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1130                 return -ENOMEM;
1131         }
1132
1133         /* Count flash numbers */
1134         fdt_for_each_subnode(subnode, blob, node)
1135                 ++flash_num;
1136
1137         if (flash_num == 0) {
1138                 debug("Error: Missing flashes!\n");
1139                 return -ENODEV;
1140         }
1141
1142         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1143                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1144         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1145                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1146
1147         plat->reg_base = res_regs.start;
1148         plat->amba_base = res_mem.start;
1149         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1150         plat->flash_num = flash_num;
1151
1152         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1153               __func__,
1154               (u64)plat->reg_base,
1155               (u64)plat->amba_base,
1156               (u64)plat->amba_total_size,
1157               plat->speed_hz,
1158               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1159               );
1160
1161         return 0;
1162 }
1163
1164 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1165                 const void *dout, void *din, unsigned long flags)
1166 {
1167         struct fsl_qspi_priv *priv;
1168         struct udevice *bus;
1169
1170         bus = dev->parent;
1171         priv = dev_get_priv(bus);
1172
1173         return qspi_xfer(priv, bitlen, dout, din, flags);
1174 }
1175
1176 static int fsl_qspi_claim_bus(struct udevice *dev)
1177 {
1178         struct fsl_qspi_priv *priv;
1179         struct udevice *bus;
1180         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1181         int ret;
1182
1183         bus = dev->parent;
1184         priv = dev_get_priv(bus);
1185
1186         /* make sure controller is not busy anywhere */
1187         ret = wait_for_bit_le32(&priv->regs->sr,
1188                                 QSPI_SR_BUSY_MASK |
1189                                 QSPI_SR_AHB_ACC_MASK |
1190                                 QSPI_SR_IP_ACC_MASK,
1191                                 false, 100, false);
1192
1193         if (ret) {
1194                 debug("ERROR : The controller is busy\n");
1195                 return ret;
1196         }
1197
1198         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1199
1200         qspi_module_disable(priv, 0);
1201
1202         return 0;
1203 }
1204
1205 static int fsl_qspi_release_bus(struct udevice *dev)
1206 {
1207         struct fsl_qspi_priv *priv;
1208         struct udevice *bus;
1209
1210         bus = dev->parent;
1211         priv = dev_get_priv(bus);
1212
1213         qspi_module_disable(priv, 1);
1214
1215         return 0;
1216 }
1217
1218 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1219 {
1220         /* Nothing to do */
1221         return 0;
1222 }
1223
1224 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1225 {
1226         /* Nothing to do */
1227         return 0;
1228 }
1229
1230 static const struct dm_spi_ops fsl_qspi_ops = {
1231         .claim_bus      = fsl_qspi_claim_bus,
1232         .release_bus    = fsl_qspi_release_bus,
1233         .xfer           = fsl_qspi_xfer,
1234         .set_speed      = fsl_qspi_set_speed,
1235         .set_mode       = fsl_qspi_set_mode,
1236 };
1237
1238 static const struct udevice_id fsl_qspi_ids[] = {
1239         { .compatible = "fsl,vf610-qspi" },
1240         { .compatible = "fsl,imx6sx-qspi" },
1241         { .compatible = "fsl,imx6ul-qspi" },
1242         { .compatible = "fsl,imx7d-qspi" },
1243         { }
1244 };
1245
1246 U_BOOT_DRIVER(fsl_qspi) = {
1247         .name   = "fsl_qspi",
1248         .id     = UCLASS_SPI,
1249         .of_match = fsl_qspi_ids,
1250         .ops    = &fsl_qspi_ops,
1251         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1252         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1253         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1254         .probe  = fsl_qspi_probe,
1255         .child_pre_probe = fsl_qspi_child_pre_probe,
1256 };
1257 #endif