1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013-2015 Freescale Semiconductor, Inc.
5 * Freescale Quad Serial Peripheral Interface (QSPI) driver
12 #include <linux/sizes.h>
13 #include <linux/iopoll.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define RX_BUFFER_SIZE 0x80
23 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
24 defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
25 #define TX_BUFFER_SIZE 0x200
27 #define TX_BUFFER_SIZE 0x40
30 #define OFFSET_BITS_MASK GENMASK(23, 0)
32 #define FLASH_STATUS_WEL 0x02
36 #define SEQID_FAST_READ 2
39 #define SEQID_CHIP_ERASE 5
43 #ifdef CONFIG_SPI_FLASH_BAR
46 #define SEQID_RDEAR 11
47 #define SEQID_WREAR 12
53 #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
54 #define QSPI_CMD_RDSR 0x05 /* Read status register */
55 #define QSPI_CMD_WREN 0x06 /* Write enable */
56 #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
57 #define QSPI_CMD_BE_4K 0x20 /* 4K erase */
58 #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
59 #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
60 #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
62 /* Used for Micron, winbond and Macronix flashes */
63 #define QSPI_CMD_WREAR 0xc5 /* EAR register write */
64 #define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
66 /* Used for Spansion flashes only. */
67 #define QSPI_CMD_BRRD 0x16 /* Bank register read */
68 #define QSPI_CMD_BRWR 0x17 /* Bank register write */
70 /* Used for Spansion S25FS-S family flash only. */
71 #define QSPI_CMD_RDAR 0x65 /* Read any device register */
72 #define QSPI_CMD_WRAR 0x71 /* Write any device register */
74 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
75 #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
76 #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
77 #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
79 /* fsl_qspi_platdata flags */
80 #define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
82 /* default SCK frequency, unit: HZ */
83 #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
85 /* QSPI max chipselect signals number */
86 #define FSL_QSPI_MAX_CHIPSELECT_NUM 4
89 * struct fsl_qspi_platdata - platform data for Freescale QSPI
91 * @flags: Flags for QSPI QSPI_FLAG_...
92 * @speed_hz: Default SCK frequency
93 * @reg_base: Base address of QSPI registers
94 * @amba_base: Base address of QSPI memory mapping
95 * @amba_total_size: size of QSPI memory mapping
96 * @flash_num: Number of active slave devices
97 * @num_chipselect: Number of QSPI chipselect signals
99 struct fsl_qspi_platdata {
103 fdt_addr_t amba_base;
104 fdt_size_t amba_total_size;
110 * struct fsl_qspi_priv - private data for Freescale QSPI
112 * @flags: Flags for QSPI QSPI_FLAG_...
113 * @bus_clk: QSPI input clk frequency
114 * @speed_hz: Default SCK frequency
115 * @cur_seqid: current LUT table sequence id
116 * @sf_addr: flash access offset
117 * @amba_base: Base address of QSPI memory mapping of every CS
118 * @amba_total_size: size of QSPI memory mapping
119 * @cur_amba_base: Base address of QSPI memory mapping of current CS
120 * @flash_num: Number of active slave devices
121 * @num_chipselect: Number of QSPI chipselect signals
122 * @regs: Point to QSPI register structure for I/O access
124 struct fsl_qspi_priv {
130 u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
135 struct fsl_qspi_regs *regs;
139 static u32 qspi_read32(u32 flags, u32 *addr)
141 return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
142 in_be32(addr) : in_le32(addr);
145 static void qspi_write32(u32 flags, u32 *addr, u32 val)
147 flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
148 out_be32(addr, val) : out_le32(addr, val);
151 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
154 u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
157 if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
158 mask = (u32)cpu_to_be32(mask);
160 return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
163 /* QSPI support swapping the flash read/write data
164 * in hardware for LS102xA, but not for VF610 */
165 static inline u32 qspi_endian_xchg(u32 data)
174 static void qspi_set_lut(struct fsl_qspi_priv *priv)
176 struct fsl_qspi_regs *regs = priv->regs;
180 qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE);
181 qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_UNLOCK);
184 lut_base = SEQID_WREN * 4;
185 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
186 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
187 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0);
188 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
189 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
192 lut_base = SEQID_FAST_READ * 4;
193 #ifdef CONFIG_SPI_FLASH_BAR
194 qspi_write32(priv->flags, ®s->lut[lut_base],
195 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
196 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
197 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
199 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
200 qspi_write32(priv->flags, ®s->lut[lut_base],
201 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
202 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
203 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
205 qspi_write32(priv->flags, ®s->lut[lut_base],
206 OPRND0(QSPI_CMD_FAST_READ_4B) |
207 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
208 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
211 qspi_write32(priv->flags, ®s->lut[lut_base + 1],
212 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
213 OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
215 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
216 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
219 lut_base = SEQID_RDSR * 4;
220 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
221 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
222 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
223 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0);
224 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
225 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
228 lut_base = SEQID_SE * 4;
229 #ifdef CONFIG_SPI_FLASH_BAR
230 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
231 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
232 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
234 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
235 qspi_write32(priv->flags, ®s->lut[lut_base],
236 OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
237 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
238 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
240 qspi_write32(priv->flags, ®s->lut[lut_base],
241 OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
242 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
243 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
245 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0);
246 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
247 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
249 /* Erase the whole chip */
250 lut_base = SEQID_CHIP_ERASE * 4;
251 qspi_write32(priv->flags, ®s->lut[lut_base],
252 OPRND0(QSPI_CMD_CHIP_ERASE) |
253 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
254 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0);
255 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
256 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
259 lut_base = SEQID_PP * 4;
260 #ifdef CONFIG_SPI_FLASH_BAR
261 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
262 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
263 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
265 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
266 qspi_write32(priv->flags, ®s->lut[lut_base],
267 OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
268 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
269 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
271 qspi_write32(priv->flags, ®s->lut[lut_base],
272 OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
273 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
274 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
276 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
277 defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
279 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
280 * So, Use IDATSZ in IPCR to determine the size and here set 0.
282 qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) |
283 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
285 qspi_write32(priv->flags, ®s->lut[lut_base + 1],
286 OPRND0(TX_BUFFER_SIZE) |
287 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
289 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
290 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
293 lut_base = SEQID_RDID * 4;
294 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
295 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
296 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
297 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0);
298 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
299 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
301 /* SUB SECTOR 4K ERASE */
302 lut_base = SEQID_BE_4K * 4;
303 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
304 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
305 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
307 #ifdef CONFIG_SPI_FLASH_BAR
309 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
310 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
313 lut_base = SEQID_BRRD * 4;
314 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
315 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
316 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
318 lut_base = SEQID_BRWR * 4;
319 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
320 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
321 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
323 lut_base = SEQID_RDEAR * 4;
324 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
325 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
326 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
328 lut_base = SEQID_WREAR * 4;
329 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
330 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
331 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
335 * Read any device register.
336 * Used for Spansion S25FS-S family flash only.
338 lut_base = SEQID_RDAR * 4;
339 qspi_write32(priv->flags, ®s->lut[lut_base],
340 OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
341 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
342 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
343 qspi_write32(priv->flags, ®s->lut[lut_base + 1],
344 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
345 OPRND1(1) | PAD1(LUT_PAD1) |
349 * Write any device register.
350 * Used for Spansion S25FS-S family flash only.
352 lut_base = SEQID_WRAR * 4;
353 qspi_write32(priv->flags, ®s->lut[lut_base],
354 OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
355 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
356 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
357 qspi_write32(priv->flags, ®s->lut[lut_base + 1],
358 OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
361 qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE);
362 qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK);
365 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
367 * If we have changed the content of the flash by writing or erasing,
368 * we need to invalidate the AHB buffer. If we do not do so, we may read out
369 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
370 * domain at the same time.
372 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
374 struct fsl_qspi_regs *regs = priv->regs;
377 reg = qspi_read32(priv->flags, ®s->mcr);
378 reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
379 qspi_write32(priv->flags, ®s->mcr, reg);
382 * The minimum delay : 1 AHB + 2 SFCK clocks.
383 * Delay 1 us is enough.
387 reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
388 qspi_write32(priv->flags, ®s->mcr, reg);
391 /* Read out the data from the AHB buffer. */
392 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
394 struct fsl_qspi_regs *regs = priv->regs;
398 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
400 qspi_write32(priv->flags, ®s->mcr,
401 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
404 rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
405 /* Read out the data directly from the AHB buffer. */
406 memcpy(rxbuf, rx_addr, len);
408 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
411 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
414 struct fsl_qspi_regs *regs = priv->regs;
416 reg = qspi_read32(priv->flags, ®s->mcr);
417 /* Disable the module */
418 qspi_write32(priv->flags, ®s->mcr, reg | QSPI_MCR_MDIS_MASK);
420 /* Set the Sampling Register for DDR */
421 reg2 = qspi_read32(priv->flags, ®s->smpr);
422 reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
423 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
424 qspi_write32(priv->flags, ®s->smpr, reg2);
426 /* Enable the module again (enable the DDR too) */
427 reg |= QSPI_MCR_DDR_EN_MASK;
428 /* Enable bit 29 for imx6sx */
431 qspi_write32(priv->flags, ®s->mcr, reg);
433 /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
434 * These two bits are reserved on other platforms
436 reg = qspi_read32(priv->flags, ®s->flshcr);
439 qspi_write32(priv->flags, ®s->flshcr, reg);
443 * There are two different ways to read out the data from the flash:
444 * the "IP Command Read" and the "AHB Command Read".
446 * The IC guy suggests we use the "AHB Command Read" which is faster
447 * then the "IP Command Read". (What's more is that there is a bug in
448 * the "IP Command Read" in the Vybrid.)
450 * After we set up the registers for the "AHB Command Read", we can use
451 * the memcpy to read the data directly. A "missed" access to the buffer
452 * causes the controller to clear the buffer, and use the sequence pointed
453 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
455 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
457 struct fsl_qspi_regs *regs = priv->regs;
459 /* AHB configuration for access buffer 0/1/2 .*/
460 qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
461 qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
462 qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
463 qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
464 (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
466 /* We only use the buffer3 */
467 qspi_write32(priv->flags, ®s->buf0ind, 0);
468 qspi_write32(priv->flags, ®s->buf1ind, 0);
469 qspi_write32(priv->flags, ®s->buf2ind, 0);
472 * Set the default lut sequence for AHB Read.
473 * Parallel mode is disabled.
475 qspi_write32(priv->flags, ®s->bfgencr,
476 SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
479 qspi_enable_ddr_mode(priv);
483 #ifdef CONFIG_SPI_FLASH_BAR
484 /* Bank register read/write, EAR register read/write */
485 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
487 struct fsl_qspi_regs *regs = priv->regs;
488 u32 reg, mcr_reg, data, seqid;
490 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
491 qspi_write32(priv->flags, ®s->mcr,
492 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
494 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
496 qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
498 if (priv->cur_seqid == QSPI_CMD_BRRD)
503 qspi_write32(priv->flags, ®s->ipcr,
504 (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
506 /* Wait previous command complete */
507 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
513 reg = qspi_read32(priv->flags, ®s->rbsr);
514 if (reg & QSPI_RBSR_RDBFL_MASK) {
515 data = qspi_read32(priv->flags, ®s->rbdr[0]);
516 data = qspi_endian_xchg(data);
517 memcpy(rxbuf, &data, len);
518 qspi_write32(priv->flags, ®s->mcr,
519 qspi_read32(priv->flags, ®s->mcr) |
520 QSPI_MCR_CLR_RXF_MASK);
525 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
529 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
531 struct fsl_qspi_regs *regs = priv->regs;
532 u32 mcr_reg, rbsr_reg, data, size;
535 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
536 qspi_write32(priv->flags, ®s->mcr,
537 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
539 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
541 qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
543 qspi_write32(priv->flags, ®s->ipcr,
544 (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
545 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
549 while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
552 rbsr_reg = qspi_read32(priv->flags, ®s->rbsr);
553 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
554 data = qspi_read32(priv->flags, ®s->rbdr[i]);
555 data = qspi_endian_xchg(data);
556 size = (len < 4) ? len : 4;
557 memcpy(rxbuf, &data, size);
564 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
567 /* If not use AHB read, read data from ip interface */
568 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
570 struct fsl_qspi_regs *regs = priv->regs;
576 if (priv->cur_seqid == QSPI_CMD_RDAR)
579 seqid = SEQID_FAST_READ;
581 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
582 qspi_write32(priv->flags, ®s->mcr,
583 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
585 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
587 to_or_from = priv->sf_addr + priv->cur_amba_base;
592 qspi_write32(priv->flags, ®s->sfar, to_or_from);
594 size = (len > RX_BUFFER_SIZE) ?
595 RX_BUFFER_SIZE : len;
597 qspi_write32(priv->flags, ®s->ipcr,
598 (seqid << QSPI_IPCR_SEQID_SHIFT) |
600 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
607 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
608 data = qspi_read32(priv->flags, ®s->rbdr[i]);
609 data = qspi_endian_xchg(data);
611 memcpy(rxbuf, &data, size);
613 memcpy(rxbuf, &data, 4);
618 qspi_write32(priv->flags, ®s->mcr,
619 qspi_read32(priv->flags, ®s->mcr) |
620 QSPI_MCR_CLR_RXF_MASK);
623 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
626 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
628 struct fsl_qspi_regs *regs = priv->regs;
629 u32 mcr_reg, data, reg, status_reg, seqid;
630 int i, size, tx_size;
633 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
634 qspi_write32(priv->flags, ®s->mcr,
635 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
637 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
640 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
643 qspi_write32(priv->flags, ®s->ipcr,
644 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
645 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
648 qspi_write32(priv->flags, ®s->ipcr,
649 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
650 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
653 reg = qspi_read32(priv->flags, ®s->rbsr);
654 if (reg & QSPI_RBSR_RDBFL_MASK) {
655 status_reg = qspi_read32(priv->flags, ®s->rbdr[0]);
656 status_reg = qspi_endian_xchg(status_reg);
658 qspi_write32(priv->flags, ®s->mcr,
659 qspi_read32(priv->flags, ®s->mcr) |
660 QSPI_MCR_CLR_RXF_MASK);
663 /* Default is page programming */
665 if (priv->cur_seqid == QSPI_CMD_WRAR)
667 #ifdef CONFIG_SPI_FLASH_BAR
668 if (priv->cur_seqid == QSPI_CMD_BRWR)
670 else if (priv->cur_seqid == QSPI_CMD_WREAR)
674 to_or_from = priv->sf_addr + priv->cur_amba_base;
676 qspi_write32(priv->flags, ®s->sfar, to_or_from);
678 tx_size = (len > TX_BUFFER_SIZE) ?
679 TX_BUFFER_SIZE : len;
683 * There must be atleast 128bit data
684 * available in TX FIFO for any pop operation
688 for (i = 0; i < size * 4; i++) {
689 memcpy(&data, txbuf, 4);
690 data = qspi_endian_xchg(data);
691 qspi_write32(priv->flags, ®s->tbdr, data);
695 qspi_write32(priv->flags, ®s->ipcr,
696 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
697 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
700 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
703 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
705 struct fsl_qspi_regs *regs = priv->regs;
706 u32 mcr_reg, reg, data;
708 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
709 qspi_write32(priv->flags, ®s->mcr,
710 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
712 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
714 qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
716 qspi_write32(priv->flags, ®s->ipcr,
717 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
718 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
724 reg = qspi_read32(priv->flags, ®s->rbsr);
725 if (reg & QSPI_RBSR_RDBFL_MASK) {
726 data = qspi_read32(priv->flags, ®s->rbdr[0]);
727 data = qspi_endian_xchg(data);
728 memcpy(rxbuf, &data, len);
729 qspi_write32(priv->flags, ®s->mcr,
730 qspi_read32(priv->flags, ®s->mcr) |
731 QSPI_MCR_CLR_RXF_MASK);
736 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
739 static void qspi_op_erase(struct fsl_qspi_priv *priv)
741 struct fsl_qspi_regs *regs = priv->regs;
745 mcr_reg = qspi_read32(priv->flags, ®s->mcr);
746 qspi_write32(priv->flags, ®s->mcr,
747 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
749 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
751 to_or_from = priv->sf_addr + priv->cur_amba_base;
752 qspi_write32(priv->flags, ®s->sfar, to_or_from);
754 qspi_write32(priv->flags, ®s->ipcr,
755 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
756 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
759 if (priv->cur_seqid == QSPI_CMD_SE) {
760 qspi_write32(priv->flags, ®s->ipcr,
761 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
762 } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
763 qspi_write32(priv->flags, ®s->ipcr,
764 (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
766 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
769 qspi_write32(priv->flags, ®s->mcr, mcr_reg);
772 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
773 const void *dout, void *din, unsigned long flags)
775 u32 bytes = DIV_ROUND_UP(bitlen, 8);
776 static u32 wr_sfaddr;
782 if (flags & SPI_XFER_BEGIN) {
783 priv->cur_seqid = *(u8 *)dout;
784 memcpy(&txbuf, dout, 4);
787 if (flags == SPI_XFER_END) {
788 priv->sf_addr = wr_sfaddr;
789 qspi_op_write(priv, (u8 *)dout, bytes);
793 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
794 priv->cur_seqid == QSPI_CMD_RDAR) {
795 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
796 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
797 (priv->cur_seqid == QSPI_CMD_BE_4K)) {
798 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
800 } else if (priv->cur_seqid == QSPI_CMD_PP ||
801 priv->cur_seqid == QSPI_CMD_WRAR) {
802 wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
803 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
804 (priv->cur_seqid == QSPI_CMD_WREAR)) {
805 #ifdef CONFIG_SPI_FLASH_BAR
812 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
813 #ifdef CONFIG_SYS_FSL_QSPI_AHB
814 qspi_ahb_read(priv, din, bytes);
816 qspi_op_read(priv, din, bytes);
818 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
819 qspi_op_read(priv, din, bytes);
820 } else if (priv->cur_seqid == QSPI_CMD_RDID)
821 qspi_op_rdid(priv, din, bytes);
822 else if (priv->cur_seqid == QSPI_CMD_RDSR)
823 qspi_op_rdsr(priv, din, bytes);
824 #ifdef CONFIG_SPI_FLASH_BAR
825 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
826 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
828 qspi_op_rdbank(priv, din, bytes);
833 #ifdef CONFIG_SYS_FSL_QSPI_AHB
834 if ((priv->cur_seqid == QSPI_CMD_SE) ||
835 (priv->cur_seqid == QSPI_CMD_PP) ||
836 (priv->cur_seqid == QSPI_CMD_BE_4K) ||
837 (priv->cur_seqid == QSPI_CMD_WREAR) ||
838 (priv->cur_seqid == QSPI_CMD_BRWR))
839 qspi_ahb_invalid(priv);
845 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
849 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
851 mcr_val |= QSPI_MCR_MDIS_MASK;
853 mcr_val &= ~QSPI_MCR_MDIS_MASK;
854 qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
857 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
861 smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
862 smpr_val &= ~clear_bits;
863 smpr_val |= set_bits;
864 qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
867 static int fsl_qspi_child_pre_probe(struct udevice *dev)
869 struct spi_slave *slave = dev_get_parent_priv(dev);
871 slave->max_write_size = TX_BUFFER_SIZE;
876 static int fsl_qspi_probe(struct udevice *bus)
878 u32 amba_size_per_chip;
879 struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
880 struct fsl_qspi_priv *priv = dev_get_priv(bus);
881 struct dm_spi_bus *dm_spi_bus;
884 dm_spi_bus = bus->uclass_priv;
886 dm_spi_bus->max_hz = plat->speed_hz;
888 priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
889 priv->flags = plat->flags;
891 priv->speed_hz = plat->speed_hz;
893 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
894 * AMBA memory zone should be located on the 0~4GB space
895 * even on a 64bits cpu.
897 priv->amba_base[0] = (u32)plat->amba_base;
898 priv->amba_total_size = (u32)plat->amba_total_size;
899 priv->flash_num = plat->flash_num;
900 priv->num_chipselect = plat->num_chipselect;
902 /* make sure controller is not busy anywhere */
903 ret = is_controller_busy(priv);
906 debug("ERROR : The controller is busy\n");
910 qspi_write32(priv->flags, &priv->regs->mcr,
911 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
912 QSPI_MCR_END_CFD_LE);
914 qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
915 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
918 * Assign AMBA memory zone for every chipselect
919 * QuadSPI has two channels, every channel has two chipselects.
920 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
921 * into two parts and assign to every channel. This indicate that every
922 * channel only has one valid chipselect.
923 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
924 * into four parts and assign to every chipselect.
925 * Every channel will has two valid chipselects.
927 amba_size_per_chip = priv->amba_total_size >>
928 (priv->num_chipselect >> 1);
929 for (i = 1 ; i < priv->num_chipselect ; i++)
931 amba_size_per_chip + priv->amba_base[i - 1];
934 * Any read access to non-implemented addresses will provide
937 * In case single die flash devices, TOP_ADDR_MEMA2 and
938 * TOP_ADDR_MEMB2 should be initialized/programmed to
939 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
940 * setting the size of these devices to 0. This would ensure
941 * that the complete memory map is assigned to only one flash device.
943 qspi_write32(priv->flags, &priv->regs->sfa1ad,
944 priv->amba_base[0] + amba_size_per_chip);
945 switch (priv->num_chipselect) {
949 qspi_write32(priv->flags, &priv->regs->sfa2ad,
951 qspi_write32(priv->flags, &priv->regs->sfb1ad,
952 priv->amba_base[1] + amba_size_per_chip);
953 qspi_write32(priv->flags, &priv->regs->sfb2ad,
954 priv->amba_base[1] + amba_size_per_chip);
957 qspi_write32(priv->flags, &priv->regs->sfa2ad,
959 qspi_write32(priv->flags, &priv->regs->sfb1ad,
961 qspi_write32(priv->flags, &priv->regs->sfb2ad,
962 priv->amba_base[3] + amba_size_per_chip);
965 debug("Error: Unsupported chipselect number %u!\n",
966 priv->num_chipselect);
967 qspi_module_disable(priv, 1);
973 #ifdef CONFIG_SYS_FSL_QSPI_AHB
974 qspi_init_ahb_read(priv);
977 qspi_module_disable(priv, 0);
982 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
984 struct fdt_resource res_regs, res_mem;
985 struct fsl_qspi_platdata *plat = bus->platdata;
986 const void *blob = gd->fdt_blob;
987 int node = dev_of_offset(bus);
988 int ret, flash_num = 0, subnode;
990 if (fdtdec_get_bool(blob, node, "big-endian"))
991 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
993 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
994 "QuadSPI", &res_regs);
996 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
999 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1000 "QuadSPI-memory", &res_mem);
1002 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1006 /* Count flash numbers */
1007 fdt_for_each_subnode(subnode, blob, node)
1010 if (flash_num == 0) {
1011 debug("Error: Missing flashes!\n");
1015 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1016 FSL_QSPI_DEFAULT_SCK_FREQ);
1017 plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1018 FSL_QSPI_MAX_CHIPSELECT_NUM);
1020 plat->reg_base = res_regs.start;
1021 plat->amba_base = res_mem.start;
1022 plat->amba_total_size = res_mem.end - res_mem.start + 1;
1023 plat->flash_num = flash_num;
1025 debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1027 (u64)plat->reg_base,
1028 (u64)plat->amba_base,
1029 (u64)plat->amba_total_size,
1031 plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1037 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1038 const void *dout, void *din, unsigned long flags)
1040 struct fsl_qspi_priv *priv;
1041 struct udevice *bus;
1044 priv = dev_get_priv(bus);
1046 return qspi_xfer(priv, bitlen, dout, din, flags);
1049 static int fsl_qspi_claim_bus(struct udevice *dev)
1051 struct fsl_qspi_priv *priv;
1052 struct udevice *bus;
1053 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1057 priv = dev_get_priv(bus);
1059 /* make sure controller is not busy anywhere */
1060 ret = is_controller_busy(priv);
1063 debug("ERROR : The controller is busy\n");
1067 priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1069 qspi_module_disable(priv, 0);
1074 static int fsl_qspi_release_bus(struct udevice *dev)
1076 struct fsl_qspi_priv *priv;
1077 struct udevice *bus;
1080 priv = dev_get_priv(bus);
1082 qspi_module_disable(priv, 1);
1087 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1093 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1099 static const struct dm_spi_ops fsl_qspi_ops = {
1100 .claim_bus = fsl_qspi_claim_bus,
1101 .release_bus = fsl_qspi_release_bus,
1102 .xfer = fsl_qspi_xfer,
1103 .set_speed = fsl_qspi_set_speed,
1104 .set_mode = fsl_qspi_set_mode,
1107 static const struct udevice_id fsl_qspi_ids[] = {
1108 { .compatible = "fsl,vf610-qspi" },
1109 { .compatible = "fsl,imx6sx-qspi" },
1110 { .compatible = "fsl,imx6ul-qspi" },
1111 { .compatible = "fsl,imx7d-qspi" },
1115 U_BOOT_DRIVER(fsl_qspi) = {
1118 .of_match = fsl_qspi_ids,
1119 .ops = &fsl_qspi_ops,
1120 .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1121 .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1122 .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1123 .probe = fsl_qspi_probe,
1124 .child_pre_probe = fsl_qspi_child_pre_probe,