1 // SPDX-License-Identifier: GPL-2.0+
4 * Freescale QuadSPI driver.
6 * Copyright (C) 2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2018 Bootlin
8 * Copyright (C) 2018 exceet electronics GmbH
9 * Copyright (C) 2018 Kontron Electronics GmbH
10 * Copyright 2019-2020 NXP
12 * This driver is a ported version of Linux Freescale QSPI driver taken from
13 * v5.5-rc1 tag having following information.
15 * Transition to SPI MEM interface:
17 * Boris Brezillon <bbrezillon@kernel.org>
18 * Frieder Schrempf <frieder.schrempf@kontron.de>
19 * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
20 * Suresh Gupta <suresh.gupta@nxp.com>
22 * Based on the original fsl-quadspi.c spi-nor driver.
23 * Transition to spi-mem in spi-fsl-qspi.c
28 #include <dm/device_compat.h>
32 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <linux/libfdt.h>
35 #include <linux/sizes.h>
36 #include <linux/iopoll.h>
37 #include <linux/iopoll.h>
38 #include <linux/sizes.h>
39 #include <linux/err.h>
42 DECLARE_GLOBAL_DATA_PTR;
45 * The driver only uses one single LUT entry, that is updated on
46 * each call of exec_op(). Index 0 is preset at boot with a basic
47 * read operation, so let's use the last entry (15).
50 #define SEQID_LUT_AHB 14
52 /* Registers used by the driver */
53 #define QUADSPI_MCR 0x00
54 #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
55 #define QUADSPI_MCR_MDIS_MASK BIT(14)
56 #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
57 #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
58 #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
59 #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
60 #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
61 #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
63 #define QUADSPI_IPCR 0x08
64 #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
65 #define QUADSPI_FLSHCR 0x0c
66 #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
67 #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
68 #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
70 #define QUADSPI_BUF3CR 0x1c
71 #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
72 #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
73 #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
75 #define QUADSPI_BFGENCR 0x20
76 #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
78 #define QUADSPI_BUF0IND 0x30
79 #define QUADSPI_BUF1IND 0x34
80 #define QUADSPI_BUF2IND 0x38
81 #define QUADSPI_SFAR 0x100
83 #define QUADSPI_SMPR 0x108
84 #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
85 #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
86 #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
87 #define QUADSPI_SMPR_HSENA_MASK BIT(0)
89 #define QUADSPI_RBCT 0x110
90 #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
91 #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
93 #define QUADSPI_TBDR 0x154
95 #define QUADSPI_SR 0x15c
96 #define QUADSPI_SR_IP_ACC_MASK BIT(1)
97 #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
99 #define QUADSPI_FR 0x160
100 #define QUADSPI_FR_TFF_MASK BIT(0)
102 #define QUADSPI_RSER 0x164
103 #define QUADSPI_RSER_TFIE BIT(0)
105 #define QUADSPI_SPTRCLR 0x16c
106 #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
107 #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
109 #define QUADSPI_SFA1AD 0x180
110 #define QUADSPI_SFA2AD 0x184
111 #define QUADSPI_SFB1AD 0x188
112 #define QUADSPI_SFB2AD 0x18c
113 #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
115 #define QUADSPI_LUTKEY 0x300
116 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
118 #define QUADSPI_LCKCR 0x304
119 #define QUADSPI_LCKER_LOCK BIT(0)
120 #define QUADSPI_LCKER_UNLOCK BIT(1)
122 #define QUADSPI_LUT_BASE 0x310
123 #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
124 #define QUADSPI_LUT_REG(idx) \
125 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
127 #define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4)
128 #define QUADSPI_AHB_LUT_REG(idx) \
129 (QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4)
131 /* Instruction set for the LUT register */
139 #define LUT_FSL_READ 7
140 #define LUT_FSL_WRITE 8
141 #define LUT_JMP_ON_CS 9
142 #define LUT_ADDR_DDR 10
143 #define LUT_MODE_DDR 11
144 #define LUT_MODE2_DDR 12
145 #define LUT_MODE4_DDR 13
146 #define LUT_FSL_READ_DDR 14
147 #define LUT_FSL_WRITE_DDR 15
148 #define LUT_DATA_LEARN 16
151 * The PAD definitions for LUT register.
153 * The pad stands for the number of IO lines [0:3].
154 * For example, the quad read needs four IO lines,
155 * so you should use LUT_PAD(4).
157 #define LUT_PAD(x) (fls(x) - 1)
160 * Macro for constructing the LUT entries with the following
163 * ---------------------------------------------------
164 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
165 * ---------------------------------------------------
167 #define LUT_DEF(idx, ins, pad, opr) \
168 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
170 /* Controller needs driver to swap endianness */
171 #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
173 /* Controller needs 4x internal clock */
174 #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
177 * TKT253890, the controller needs the driver to fill the txfifo with
178 * 16 bytes at least to trigger a data transfer, even though the extra
179 * data won't be transferred.
181 #define QUADSPI_QUIRK_TKT253890 BIT(2)
183 /* TKT245618, the controller cannot wake up from wait mode */
184 #define QUADSPI_QUIRK_TKT245618 BIT(3)
187 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
188 * internally. No need to add it when setting SFXXAD and SFAR registers
190 #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
193 * Controller uses TDH bits in register QUADSPI_FLSHCR.
194 * They need to be set in accordance with the DDR/SDR mode.
196 #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
199 * Controller only has Two CS on flash A, no flash B port
201 #define QUADSPI_QUIRK_SINGLE_BUS BIT(6)
203 struct fsl_qspi_devtype_data {
206 unsigned int ahb_buf_size;
211 static const struct fsl_qspi_devtype_data vybrid_data = {
214 .ahb_buf_size = SZ_1K,
215 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
216 .little_endian = true,
219 static const struct fsl_qspi_devtype_data imx6sx_data = {
222 .ahb_buf_size = SZ_1K,
223 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
224 .little_endian = true,
227 static const struct fsl_qspi_devtype_data imx7d_data = {
230 .ahb_buf_size = SZ_1K,
231 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
232 QUADSPI_QUIRK_USE_TDH_SETTING,
233 .little_endian = true,
236 static const struct fsl_qspi_devtype_data imx6ul_data = {
239 .ahb_buf_size = SZ_1K,
240 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
241 QUADSPI_QUIRK_USE_TDH_SETTING,
242 .little_endian = true,
245 static const struct fsl_qspi_devtype_data imx7ulp_data = {
248 .ahb_buf_size = SZ_128,
249 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
250 QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS,
251 .little_endian = true,
254 static const struct fsl_qspi_devtype_data ls1021a_data = {
257 .ahb_buf_size = SZ_1K,
259 .little_endian = false,
262 static const struct fsl_qspi_devtype_data ls1088a_data = {
265 .ahb_buf_size = SZ_1K,
266 .quirks = QUADSPI_QUIRK_TKT253890,
267 .little_endian = true,
270 static const struct fsl_qspi_devtype_data ls2080a_data = {
273 .ahb_buf_size = SZ_1K,
274 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
275 .little_endian = true,
280 void __iomem *iobase;
281 void __iomem *ahb_addr;
284 const struct fsl_qspi_devtype_data *devtype_data;
288 static inline int needs_swap_endian(struct fsl_qspi *q)
290 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
293 static inline int needs_4x_clock(struct fsl_qspi *q)
295 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
298 static inline int needs_fill_txfifo(struct fsl_qspi *q)
300 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
303 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
305 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
308 static inline int needs_amba_base_offset(struct fsl_qspi *q)
310 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
313 static inline int needs_tdh_setting(struct fsl_qspi *q)
315 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
318 static inline int needs_single_bus(struct fsl_qspi *q)
320 return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS;
324 * An IC bug makes it necessary to rearrange the 32-bit data.
325 * Later chips, such as IMX6SLX, have fixed this bug.
327 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
329 return needs_swap_endian(q) ? __swab32(a) : a;
333 * R/W functions for big- or little-endian registers:
334 * The QSPI controller's endianness is independent of
335 * the CPU core's endianness. So far, although the CPU
336 * core is little-endian the QSPI controller can use
337 * big-endian or little-endian.
339 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
341 if (q->devtype_data->little_endian)
347 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
349 if (q->devtype_data->little_endian)
350 return in_le32(addr);
352 return in_be32(addr);
355 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
367 static bool fsl_qspi_supports_op(struct spi_slave *slave,
368 const struct spi_mem_op *op)
370 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
373 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
376 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
378 if (op->dummy.nbytes)
379 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
382 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
388 * The number of instructions needed for the op, needs
389 * to fit into a single LUT entry.
391 if (op->addr.nbytes +
392 (op->dummy.nbytes ? 1 : 0) +
393 (op->data.nbytes ? 1 : 0) > 6)
396 /* Max 64 dummy clock cycles supported */
397 if (op->dummy.nbytes &&
398 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
401 /* Max data length, check controller limits and alignment */
402 if (op->data.dir == SPI_MEM_DATA_IN &&
403 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
404 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
405 !IS_ALIGNED(op->data.nbytes, 8))))
408 if (op->data.dir == SPI_MEM_DATA_OUT &&
409 op->data.nbytes > q->devtype_data->txfifo)
412 return spi_mem_default_supports_op(slave, op);
415 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
416 const struct spi_mem_op *op)
418 void __iomem *base = q->iobase;
422 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
425 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
426 if (op->addr.nbytes) {
427 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
428 LUT_PAD(op->addr.buswidth),
429 (op->addr.nbytes == 4) ? 0x20 : 0x18);
434 * For some unknown reason, using LUT_ADDR doesn't work in some
435 * cases (at least with only one byte long addresses), so
436 * let's use LUT_MODE to write the address bytes one by one
438 for (i = 0; i < op->addr.nbytes; i++) {
439 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
441 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
442 LUT_PAD(op->addr.buswidth),
448 if (op->dummy.nbytes) {
449 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
450 LUT_PAD(op->dummy.buswidth),
451 op->dummy.nbytes * 8 /
456 if (op->data.nbytes) {
457 lutval[lutidx / 2] |= LUT_DEF(lutidx,
458 op->data.dir == SPI_MEM_DATA_IN ?
459 LUT_FSL_READ : LUT_FSL_WRITE,
460 LUT_PAD(op->data.buswidth),
465 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
468 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
469 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
471 dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
472 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
475 for (i = 0; i < ARRAY_SIZE(lutval); i++)
476 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
478 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
479 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
481 for (i = 0; i < ARRAY_SIZE(lutval); i++)
482 qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
487 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
488 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
492 * If we have changed the content of the flash by writing or erasing, or if we
493 * read from flash with a different offset into the page buffer, we need to
494 * invalidate the AHB buffer. If we do not do so, we may read out the wrong
495 * data. The spec tells us reset the AHB domain and Serial Flash domain at
498 static void fsl_qspi_invalidate(struct fsl_qspi *q)
502 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
503 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
504 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
507 * The minimum delay : 1 AHB + 2 SFCK clocks.
508 * Delay 1 us is enough.
512 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
513 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
516 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
518 struct dm_spi_slave_plat *plat =
519 dev_get_parent_plat(slave->dev);
521 if (q->selected == plat->cs)
524 q->selected = plat->cs;
525 fsl_qspi_invalidate(q);
528 static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q)
530 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
531 if (needs_single_bus(q))
532 return q->memmap_size / 2;
534 return q->memmap_size / 4;
536 return ALIGN(q->devtype_data->ahb_buf_size, 0x400);
540 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
542 void __iomem *ahb_read_addr = q->ahb_addr;
544 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
546 ahb_read_addr += op->addr.val;
549 memcpy_fromio(op->data.buf.in,
550 ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q),
554 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
555 const struct spi_mem_op *op)
557 void __iomem *base = q->iobase;
561 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
562 memcpy(&val, op->data.buf.out + i, 4);
563 val = fsl_qspi_endian_xchg(q, val);
564 qspi_writel(q, val, base + QUADSPI_TBDR);
567 if (i < op->data.nbytes) {
568 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
569 val = fsl_qspi_endian_xchg(q, val);
570 qspi_writel(q, val, base + QUADSPI_TBDR);
573 if (needs_fill_txfifo(q)) {
574 for (i = op->data.nbytes; i < 16; i += 4)
575 qspi_writel(q, 0, base + QUADSPI_TBDR);
579 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
580 const struct spi_mem_op *op)
582 void __iomem *base = q->iobase;
584 u8 *buf = op->data.buf.in;
587 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
588 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
589 val = fsl_qspi_endian_xchg(q, val);
590 memcpy(buf + i, &val, 4);
593 if (i < op->data.nbytes) {
594 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
595 val = fsl_qspi_endian_xchg(q, val);
596 memcpy(buf + i, &val, op->data.nbytes - i);
600 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
601 u32 mask, u32 delay_us, u32 timeout_us)
605 if (!q->devtype_data->little_endian)
606 mask = (u32)cpu_to_be32(mask);
608 return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
611 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
613 void __iomem *base = q->iobase;
617 * Always start the sequence at the same index since we update
618 * the LUT at each exec_op() call. And also specify the DATA
619 * length, since it's has not been specified in the LUT.
621 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
622 base + QUADSPI_IPCR);
624 /* wait for the controller being ready */
625 err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
626 (QUADSPI_SR_IP_ACC_MASK |
627 QUADSPI_SR_AHB_ACC_MASK),
630 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
631 fsl_qspi_read_rxfifo(q, op);
636 static int fsl_qspi_exec_op(struct spi_slave *slave,
637 const struct spi_mem_op *op)
639 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
640 void __iomem *base = q->iobase;
644 /* wait for the controller being ready */
645 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
646 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
648 fsl_qspi_select_mem(q, slave);
650 if (needs_amba_base_offset(q))
651 addr_offset = q->memmap_phy;
653 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
655 addr_offset += op->addr.val;
659 q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset,
660 base + QUADSPI_SFAR);
662 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
663 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
666 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
667 base + QUADSPI_SPTRCLR);
669 fsl_qspi_prepare_lut(q, op);
672 * If we have large chunks of data, we read them through the AHB bus
673 * by accessing the mapped memory. In all other cases we use
674 * IP commands to access the flash.
676 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
677 op->data.dir == SPI_MEM_DATA_IN) {
678 fsl_qspi_read_ahb(q, op);
680 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
681 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
683 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
684 fsl_qspi_fill_txfifo(q, op);
686 err = fsl_qspi_do_op(q, op);
689 /* Invalidate the data in the AHB buffer. */
690 fsl_qspi_invalidate(q);
695 static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
696 struct spi_mem_op *op)
698 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
700 if (op->data.dir == SPI_MEM_DATA_OUT) {
701 if (op->data.nbytes > q->devtype_data->txfifo)
702 op->data.nbytes = q->devtype_data->txfifo;
704 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
705 op->data.nbytes = q->devtype_data->ahb_buf_size;
706 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
707 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
713 static int fsl_qspi_default_setup(struct fsl_qspi *q)
715 void __iomem *base = q->iobase;
716 u32 reg, addr_offset = 0, memsize_cs;
718 /* Reset the module */
719 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
723 /* Disable the module */
724 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
728 * Previous boot stages (BootROM, bootloader) might have used DDR
729 * mode and did not clear the TDH bits. As we currently use SDR mode
730 * only, clear the TDH bits if necessary.
732 if (needs_tdh_setting(q))
733 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
734 ~QUADSPI_FLSHCR_TDH_MASK,
735 base + QUADSPI_FLSHCR);
737 reg = qspi_readl(q, base + QUADSPI_SMPR);
738 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
739 | QUADSPI_SMPR_FSPHS_MASK
740 | QUADSPI_SMPR_HSENA_MASK
741 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
743 /* We only use the buffer3 for AHB read */
744 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
745 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
746 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
748 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
749 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
750 q->iobase + QUADSPI_BFGENCR);
752 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
753 q->iobase + QUADSPI_BFGENCR);
755 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
756 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
757 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
758 base + QUADSPI_BUF3CR);
760 if (needs_amba_base_offset(q))
761 addr_offset = q->memmap_phy;
764 * In HW there can be a maximum of four chips on two buses with
765 * two chip selects on each bus. We use four chip selects in SW
766 * to differentiate between the four chips.
767 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
768 * SFB2AD accordingly.
770 memsize_cs = fsl_qspi_memsize_per_cs(q);
771 qspi_writel(q, memsize_cs + addr_offset,
772 base + QUADSPI_SFA1AD);
773 qspi_writel(q, memsize_cs * 2 + addr_offset,
774 base + QUADSPI_SFA2AD);
775 if (!needs_single_bus(q)) {
776 qspi_writel(q, memsize_cs * 3 + addr_offset,
777 base + QUADSPI_SFB1AD);
778 qspi_writel(q, memsize_cs * 4 + addr_offset,
779 base + QUADSPI_SFB2AD);
784 /* Enable the module */
785 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
790 static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
791 .adjust_op_size = fsl_qspi_adjust_op_size,
792 .supports_op = fsl_qspi_supports_op,
793 .exec_op = fsl_qspi_exec_op,
796 static int fsl_qspi_probe(struct udevice *bus)
798 struct dm_spi_bus *dm_bus = dev_get_uclass_priv(bus);
799 struct fsl_qspi *q = dev_get_priv(bus);
800 const void *blob = gd->fdt_blob;
801 int node = dev_of_offset(bus);
802 struct fdt_resource res;
806 q->devtype_data = (struct fsl_qspi_devtype_data *)
807 dev_get_driver_data(bus);
809 /* find the resources */
810 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
813 dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
817 q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
819 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
820 "QuadSPI-memory", &res);
822 dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
826 q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
827 q->memmap_phy = res.start;
828 q->memmap_size = res.end - res.start;
830 dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
833 fsl_qspi_default_setup(q);
838 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
839 const void *dout, void *din, unsigned long flags)
844 static int fsl_qspi_claim_bus(struct udevice *dev)
849 static int fsl_qspi_release_bus(struct udevice *dev)
854 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
859 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
864 static const struct dm_spi_ops fsl_qspi_ops = {
865 .claim_bus = fsl_qspi_claim_bus,
866 .release_bus = fsl_qspi_release_bus,
867 .xfer = fsl_qspi_xfer,
868 .set_speed = fsl_qspi_set_speed,
869 .set_mode = fsl_qspi_set_mode,
870 .mem_ops = &fsl_qspi_mem_ops,
873 static const struct udevice_id fsl_qspi_ids[] = {
874 { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
875 { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
876 { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
877 { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
878 { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
879 { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
880 { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
881 { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
885 U_BOOT_DRIVER(fsl_qspi) = {
888 .of_match = fsl_qspi_ids,
889 .ops = &fsl_qspi_ops,
890 .priv_auto = sizeof(struct fsl_qspi),
891 .probe = fsl_qspi_probe,