spi: fsl_qspi: Add controller busy check before new spi operation
[platform/kernel/u-boot.git] / drivers / spi / fsl_qspi.c
1 /*
2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
3  *
4  * Freescale Quad Serial Peripheral Interface (QSPI) driver
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #include <common.h>
10 #include <malloc.h>
11 #include <spi.h>
12 #include <asm/io.h>
13 #include <linux/sizes.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <watchdog.h>
17 #include <wait_bit.h>
18 #include "fsl_qspi.h"
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #define RX_BUFFER_SIZE          0x80
23 #ifdef CONFIG_MX6SX
24 #define TX_BUFFER_SIZE          0x200
25 #else
26 #define TX_BUFFER_SIZE          0x40
27 #endif
28
29 #define OFFSET_BITS_MASK        GENMASK(23, 0)
30
31 #define FLASH_STATUS_WEL        0x02
32
33 /* SEQID */
34 #define SEQID_WREN              1
35 #define SEQID_FAST_READ         2
36 #define SEQID_RDSR              3
37 #define SEQID_SE                4
38 #define SEQID_CHIP_ERASE        5
39 #define SEQID_PP                6
40 #define SEQID_RDID              7
41 #define SEQID_BE_4K             8
42 #ifdef CONFIG_SPI_FLASH_BAR
43 #define SEQID_BRRD              9
44 #define SEQID_BRWR              10
45 #define SEQID_RDEAR             11
46 #define SEQID_WREAR             12
47 #endif
48 #define SEQID_WRAR              13
49 #define SEQID_RDAR              14
50
51 /* QSPI CMD */
52 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
53 #define QSPI_CMD_RDSR           0x05    /* Read status register */
54 #define QSPI_CMD_WREN           0x06    /* Write enable */
55 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
56 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
57 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
58 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
59 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
60
61 /* Used for Micron, winbond and Macronix flashes */
62 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
63 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
64
65 /* Used for Spansion flashes only. */
66 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
67 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
68
69 /* Used for Spansion S25FS-S family flash only. */
70 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
71 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
72
73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
74 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
75 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
76 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
77
78 /* fsl_qspi_platdata flags */
79 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
80
81 /* default SCK frequency, unit: HZ */
82 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
83
84 /* QSPI max chipselect signals number */
85 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
86
87 #ifdef CONFIG_DM_SPI
88 /**
89  * struct fsl_qspi_platdata - platform data for Freescale QSPI
90  *
91  * @flags: Flags for QSPI QSPI_FLAG_...
92  * @speed_hz: Default SCK frequency
93  * @reg_base: Base address of QSPI registers
94  * @amba_base: Base address of QSPI memory mapping
95  * @amba_total_size: size of QSPI memory mapping
96  * @flash_num: Number of active slave devices
97  * @num_chipselect: Number of QSPI chipselect signals
98  */
99 struct fsl_qspi_platdata {
100         u32 flags;
101         u32 speed_hz;
102         fdt_addr_t reg_base;
103         fdt_addr_t amba_base;
104         fdt_size_t amba_total_size;
105         u32 flash_num;
106         u32 num_chipselect;
107 };
108 #endif
109
110 /**
111  * struct fsl_qspi_priv - private data for Freescale QSPI
112  *
113  * @flags: Flags for QSPI QSPI_FLAG_...
114  * @bus_clk: QSPI input clk frequency
115  * @speed_hz: Default SCK frequency
116  * @cur_seqid: current LUT table sequence id
117  * @sf_addr: flash access offset
118  * @amba_base: Base address of QSPI memory mapping of every CS
119  * @amba_total_size: size of QSPI memory mapping
120  * @cur_amba_base: Base address of QSPI memory mapping of current CS
121  * @flash_num: Number of active slave devices
122  * @num_chipselect: Number of QSPI chipselect signals
123  * @regs: Point to QSPI register structure for I/O access
124  */
125 struct fsl_qspi_priv {
126         u32 flags;
127         u32 bus_clk;
128         u32 speed_hz;
129         u32 cur_seqid;
130         u32 sf_addr;
131         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
132         u32 amba_total_size;
133         u32 cur_amba_base;
134         u32 flash_num;
135         u32 num_chipselect;
136         struct fsl_qspi_regs *regs;
137 };
138
139 #ifndef CONFIG_DM_SPI
140 struct fsl_qspi {
141         struct spi_slave slave;
142         struct fsl_qspi_priv priv;
143 };
144 #endif
145
146 static u32 qspi_read32(u32 flags, u32 *addr)
147 {
148         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
149                 in_be32(addr) : in_le32(addr);
150 }
151
152 static void qspi_write32(u32 flags, u32 *addr, u32 val)
153 {
154         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
155                 out_be32(addr, val) : out_le32(addr, val);
156 }
157
158 /* QSPI support swapping the flash read/write data
159  * in hardware for LS102xA, but not for VF610 */
160 static inline u32 qspi_endian_xchg(u32 data)
161 {
162 #ifdef CONFIG_VF610
163         return swab32(data);
164 #else
165         return data;
166 #endif
167 }
168
169 static void qspi_set_lut(struct fsl_qspi_priv *priv)
170 {
171         struct fsl_qspi_regs *regs = priv->regs;
172         u32 lut_base;
173
174         /* Unlock the LUT */
175         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
176         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
177
178         /* Write Enable */
179         lut_base = SEQID_WREN * 4;
180         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
181                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
182         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
183         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
184         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
185
186         /* Fast Read */
187         lut_base = SEQID_FAST_READ * 4;
188 #ifdef CONFIG_SPI_FLASH_BAR
189         qspi_write32(priv->flags, &regs->lut[lut_base],
190                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
191                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
192                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
193 #else
194         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
195                 qspi_write32(priv->flags, &regs->lut[lut_base],
196                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
197                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
198                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
199         else
200                 qspi_write32(priv->flags, &regs->lut[lut_base],
201                              OPRND0(QSPI_CMD_FAST_READ_4B) |
202                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
203                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
204                              INSTR1(LUT_ADDR));
205 #endif
206         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
207                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
208                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
209                      INSTR1(LUT_READ));
210         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
211         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
212
213         /* Read Status */
214         lut_base = SEQID_RDSR * 4;
215         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
216                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
217                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
218         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
219         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
220         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
221
222         /* Erase a sector */
223         lut_base = SEQID_SE * 4;
224 #ifdef CONFIG_SPI_FLASH_BAR
225         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
226                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
227                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
228 #else
229         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
230                 qspi_write32(priv->flags, &regs->lut[lut_base],
231                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
232                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
233                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
234         else
235                 qspi_write32(priv->flags, &regs->lut[lut_base],
236                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
237                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
238                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
239 #endif
240         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
241         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
242         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
243
244         /* Erase the whole chip */
245         lut_base = SEQID_CHIP_ERASE * 4;
246         qspi_write32(priv->flags, &regs->lut[lut_base],
247                      OPRND0(QSPI_CMD_CHIP_ERASE) |
248                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
249         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
250         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
251         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
252
253         /* Page Program */
254         lut_base = SEQID_PP * 4;
255 #ifdef CONFIG_SPI_FLASH_BAR
256         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
257                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
258                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
259 #else
260         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
261                 qspi_write32(priv->flags, &regs->lut[lut_base],
262                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
263                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
264                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
265         else
266                 qspi_write32(priv->flags, &regs->lut[lut_base],
267                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
268                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
269                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
270 #endif
271 #ifdef CONFIG_MX6SX
272         /*
273          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
274          * So, Use IDATSZ in IPCR to determine the size and here set 0.
275          */
276         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
277                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
278 #else
279         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
280                      OPRND0(TX_BUFFER_SIZE) |
281                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
282 #endif
283         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
284         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
285
286         /* READ ID */
287         lut_base = SEQID_RDID * 4;
288         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
289                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
290                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
291         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
292         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
293         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
294
295         /* SUB SECTOR 4K ERASE */
296         lut_base = SEQID_BE_4K * 4;
297         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
298                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
299                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
300
301 #ifdef CONFIG_SPI_FLASH_BAR
302         /*
303          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
304          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
305          * initialization.
306          */
307         lut_base = SEQID_BRRD * 4;
308         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
309                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
310                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
311
312         lut_base = SEQID_BRWR * 4;
313         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
314                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
315                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
316
317         lut_base = SEQID_RDEAR * 4;
318         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
319                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
320                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
321
322         lut_base = SEQID_WREAR * 4;
323         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
324                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
325                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
326 #endif
327
328         /*
329          * Read any device register.
330          * Used for Spansion S25FS-S family flash only.
331          */
332         lut_base = SEQID_RDAR * 4;
333         qspi_write32(priv->flags, &regs->lut[lut_base],
334                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
335                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
336                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
337         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
338                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
339                      OPRND1(1) | PAD1(LUT_PAD1) |
340                      INSTR1(LUT_READ));
341
342         /*
343          * Write any device register.
344          * Used for Spansion S25FS-S family flash only.
345          */
346         lut_base = SEQID_WRAR * 4;
347         qspi_write32(priv->flags, &regs->lut[lut_base],
348                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
349                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
350                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
351         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
352                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
353
354         /* Lock the LUT */
355         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
356         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
357 }
358
359 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
360 /*
361  * If we have changed the content of the flash by writing or erasing,
362  * we need to invalidate the AHB buffer. If we do not do so, we may read out
363  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
364  * domain at the same time.
365  */
366 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
367 {
368         struct fsl_qspi_regs *regs = priv->regs;
369         u32 reg;
370
371         reg = qspi_read32(priv->flags, &regs->mcr);
372         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
373         qspi_write32(priv->flags, &regs->mcr, reg);
374
375         /*
376          * The minimum delay : 1 AHB + 2 SFCK clocks.
377          * Delay 1 us is enough.
378          */
379         udelay(1);
380
381         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
382         qspi_write32(priv->flags, &regs->mcr, reg);
383 }
384
385 /* Read out the data from the AHB buffer. */
386 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
387 {
388         struct fsl_qspi_regs *regs = priv->regs;
389         u32 mcr_reg;
390         void *rx_addr = NULL;
391
392         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
393
394         qspi_write32(priv->flags, &regs->mcr,
395                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
396                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
397
398         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
399         /* Read out the data directly from the AHB buffer. */
400         memcpy(rxbuf, rx_addr, len);
401
402         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
403 }
404
405 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
406 {
407         u32 reg, reg2;
408         struct fsl_qspi_regs *regs = priv->regs;
409
410         reg = qspi_read32(priv->flags, &regs->mcr);
411         /* Disable the module */
412         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
413
414         /* Set the Sampling Register for DDR */
415         reg2 = qspi_read32(priv->flags, &regs->smpr);
416         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
417         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
418         qspi_write32(priv->flags, &regs->smpr, reg2);
419
420         /* Enable the module again (enable the DDR too) */
421         reg |= QSPI_MCR_DDR_EN_MASK;
422         /* Enable bit 29 for imx6sx */
423         reg |= BIT(29);
424
425         qspi_write32(priv->flags, &regs->mcr, reg);
426 }
427
428 /*
429  * There are two different ways to read out the data from the flash:
430  *  the "IP Command Read" and the "AHB Command Read".
431  *
432  * The IC guy suggests we use the "AHB Command Read" which is faster
433  * then the "IP Command Read". (What's more is that there is a bug in
434  * the "IP Command Read" in the Vybrid.)
435  *
436  * After we set up the registers for the "AHB Command Read", we can use
437  * the memcpy to read the data directly. A "missed" access to the buffer
438  * causes the controller to clear the buffer, and use the sequence pointed
439  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
440  */
441 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
442 {
443         struct fsl_qspi_regs *regs = priv->regs;
444
445         /* AHB configuration for access buffer 0/1/2 .*/
446         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
447         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
448         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
449         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
450                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
451
452         /* We only use the buffer3 */
453         qspi_write32(priv->flags, &regs->buf0ind, 0);
454         qspi_write32(priv->flags, &regs->buf1ind, 0);
455         qspi_write32(priv->flags, &regs->buf2ind, 0);
456
457         /*
458          * Set the default lut sequence for AHB Read.
459          * Parallel mode is disabled.
460          */
461         qspi_write32(priv->flags, &regs->bfgencr,
462                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
463
464         /*Enable DDR Mode*/
465         qspi_enable_ddr_mode(priv);
466 }
467 #endif
468
469 #ifdef CONFIG_SPI_FLASH_BAR
470 /* Bank register read/write, EAR register read/write */
471 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
472 {
473         struct fsl_qspi_regs *regs = priv->regs;
474         u32 reg, mcr_reg, data, seqid;
475
476         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
477         qspi_write32(priv->flags, &regs->mcr,
478                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
479                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
480         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
481
482         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
483
484         if (priv->cur_seqid == QSPI_CMD_BRRD)
485                 seqid = SEQID_BRRD;
486         else
487                 seqid = SEQID_RDEAR;
488
489         qspi_write32(priv->flags, &regs->ipcr,
490                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
491
492         /* Wait previous command complete */
493         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
494                 ;
495
496         while (1) {
497                 WATCHDOG_RESET();
498
499                 reg = qspi_read32(priv->flags, &regs->rbsr);
500                 if (reg & QSPI_RBSR_RDBFL_MASK) {
501                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
502                         data = qspi_endian_xchg(data);
503                         memcpy(rxbuf, &data, len);
504                         qspi_write32(priv->flags, &regs->mcr,
505                                      qspi_read32(priv->flags, &regs->mcr) |
506                                      QSPI_MCR_CLR_RXF_MASK);
507                         break;
508                 }
509         }
510
511         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
512 }
513 #endif
514
515 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
516 {
517         struct fsl_qspi_regs *regs = priv->regs;
518         u32 mcr_reg, rbsr_reg, data, size;
519         int i;
520
521         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
522         qspi_write32(priv->flags, &regs->mcr,
523                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
524                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
525         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
526
527         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
528
529         qspi_write32(priv->flags, &regs->ipcr,
530                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
531         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
532                 ;
533
534         i = 0;
535         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
536                 WATCHDOG_RESET();
537
538                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
539                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
540                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
541                         data = qspi_endian_xchg(data);
542                         size = (len < 4) ? len : 4;
543                         memcpy(rxbuf, &data, size);
544                         len -= size;
545                         rxbuf++;
546                         i++;
547                 }
548         }
549
550         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
551 }
552
553 /* If not use AHB read, read data from ip interface */
554 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
555 {
556         struct fsl_qspi_regs *regs = priv->regs;
557         u32 mcr_reg, data;
558         int i, size;
559         u32 to_or_from;
560         u32 seqid;
561
562         if (priv->cur_seqid == QSPI_CMD_RDAR)
563                 seqid = SEQID_RDAR;
564         else
565                 seqid = SEQID_FAST_READ;
566
567         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
568         qspi_write32(priv->flags, &regs->mcr,
569                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
570                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
571         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
572
573         to_or_from = priv->sf_addr + priv->cur_amba_base;
574
575         while (len > 0) {
576                 WATCHDOG_RESET();
577
578                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
579
580                 size = (len > RX_BUFFER_SIZE) ?
581                         RX_BUFFER_SIZE : len;
582
583                 qspi_write32(priv->flags, &regs->ipcr,
584                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
585                              size);
586                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
587                         ;
588
589                 to_or_from += size;
590                 len -= size;
591
592                 i = 0;
593                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
594                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
595                         data = qspi_endian_xchg(data);
596                         if (size < 4)
597                                 memcpy(rxbuf, &data, size);
598                         else
599                                 memcpy(rxbuf, &data, 4);
600                         rxbuf++;
601                         size -= 4;
602                         i++;
603                 }
604                 qspi_write32(priv->flags, &regs->mcr,
605                              qspi_read32(priv->flags, &regs->mcr) |
606                              QSPI_MCR_CLR_RXF_MASK);
607         }
608
609         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
610 }
611
612 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
613 {
614         struct fsl_qspi_regs *regs = priv->regs;
615         u32 mcr_reg, data, reg, status_reg, seqid;
616         int i, size, tx_size;
617         u32 to_or_from = 0;
618
619         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
620         qspi_write32(priv->flags, &regs->mcr,
621                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
622                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
623         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
624
625         status_reg = 0;
626         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
627                 WATCHDOG_RESET();
628
629                 qspi_write32(priv->flags, &regs->ipcr,
630                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
631                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
632                         ;
633
634                 qspi_write32(priv->flags, &regs->ipcr,
635                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
636                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
637                         ;
638
639                 reg = qspi_read32(priv->flags, &regs->rbsr);
640                 if (reg & QSPI_RBSR_RDBFL_MASK) {
641                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
642                         status_reg = qspi_endian_xchg(status_reg);
643                 }
644                 qspi_write32(priv->flags, &regs->mcr,
645                              qspi_read32(priv->flags, &regs->mcr) |
646                              QSPI_MCR_CLR_RXF_MASK);
647         }
648
649         /* Default is page programming */
650         seqid = SEQID_PP;
651         if (priv->cur_seqid == QSPI_CMD_WRAR)
652                 seqid = SEQID_WRAR;
653 #ifdef CONFIG_SPI_FLASH_BAR
654         if (priv->cur_seqid == QSPI_CMD_BRWR)
655                 seqid = SEQID_BRWR;
656         else if (priv->cur_seqid == QSPI_CMD_WREAR)
657                 seqid = SEQID_WREAR;
658 #endif
659
660         to_or_from = priv->sf_addr + priv->cur_amba_base;
661
662         qspi_write32(priv->flags, &regs->sfar, to_or_from);
663
664         tx_size = (len > TX_BUFFER_SIZE) ?
665                 TX_BUFFER_SIZE : len;
666
667         size = tx_size / 4;
668         for (i = 0; i < size; i++) {
669                 memcpy(&data, txbuf, 4);
670                 data = qspi_endian_xchg(data);
671                 qspi_write32(priv->flags, &regs->tbdr, data);
672                 txbuf += 4;
673         }
674
675         size = tx_size % 4;
676         if (size) {
677                 data = 0;
678                 memcpy(&data, txbuf, size);
679                 data = qspi_endian_xchg(data);
680                 qspi_write32(priv->flags, &regs->tbdr, data);
681         }
682
683         qspi_write32(priv->flags, &regs->ipcr,
684                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
685         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
686                 ;
687
688         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
689 }
690
691 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
692 {
693         struct fsl_qspi_regs *regs = priv->regs;
694         u32 mcr_reg, reg, data;
695
696         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
697         qspi_write32(priv->flags, &regs->mcr,
698                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
699                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
700         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
701
702         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
703
704         qspi_write32(priv->flags, &regs->ipcr,
705                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
706         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
707                 ;
708
709         while (1) {
710                 WATCHDOG_RESET();
711
712                 reg = qspi_read32(priv->flags, &regs->rbsr);
713                 if (reg & QSPI_RBSR_RDBFL_MASK) {
714                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
715                         data = qspi_endian_xchg(data);
716                         memcpy(rxbuf, &data, len);
717                         qspi_write32(priv->flags, &regs->mcr,
718                                      qspi_read32(priv->flags, &regs->mcr) |
719                                      QSPI_MCR_CLR_RXF_MASK);
720                         break;
721                 }
722         }
723
724         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
725 }
726
727 static void qspi_op_erase(struct fsl_qspi_priv *priv)
728 {
729         struct fsl_qspi_regs *regs = priv->regs;
730         u32 mcr_reg;
731         u32 to_or_from = 0;
732
733         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
734         qspi_write32(priv->flags, &regs->mcr,
735                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
736                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
737         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
738
739         to_or_from = priv->sf_addr + priv->cur_amba_base;
740         qspi_write32(priv->flags, &regs->sfar, to_or_from);
741
742         qspi_write32(priv->flags, &regs->ipcr,
743                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
744         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
745                 ;
746
747         if (priv->cur_seqid == QSPI_CMD_SE) {
748                 qspi_write32(priv->flags, &regs->ipcr,
749                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
750         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
751                 qspi_write32(priv->flags, &regs->ipcr,
752                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
753         }
754         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
755                 ;
756
757         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
758 }
759
760 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
761                 const void *dout, void *din, unsigned long flags)
762 {
763         u32 bytes = DIV_ROUND_UP(bitlen, 8);
764         static u32 wr_sfaddr;
765         u32 txbuf;
766
767         WATCHDOG_RESET();
768
769         if (dout) {
770                 if (flags & SPI_XFER_BEGIN) {
771                         priv->cur_seqid = *(u8 *)dout;
772                         memcpy(&txbuf, dout, 4);
773                 }
774
775                 if (flags == SPI_XFER_END) {
776                         priv->sf_addr = wr_sfaddr;
777                         qspi_op_write(priv, (u8 *)dout, bytes);
778                         return 0;
779                 }
780
781                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
782                     priv->cur_seqid == QSPI_CMD_RDAR) {
783                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
784                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
785                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
786                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
787                         qspi_op_erase(priv);
788                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
789                            priv->cur_seqid == QSPI_CMD_WRAR) {
790                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
791                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
792                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
793 #ifdef CONFIG_SPI_FLASH_BAR
794                         wr_sfaddr = 0;
795 #endif
796                 }
797         }
798
799         if (din) {
800                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
801 #ifdef CONFIG_SYS_FSL_QSPI_AHB
802                         qspi_ahb_read(priv, din, bytes);
803 #else
804                         qspi_op_read(priv, din, bytes);
805 #endif
806                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
807                         qspi_op_read(priv, din, bytes);
808                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
809                         qspi_op_rdid(priv, din, bytes);
810                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
811                         qspi_op_rdsr(priv, din, bytes);
812 #ifdef CONFIG_SPI_FLASH_BAR
813                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
814                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
815                         priv->sf_addr = 0;
816                         qspi_op_rdbank(priv, din, bytes);
817                 }
818 #endif
819         }
820
821 #ifdef CONFIG_SYS_FSL_QSPI_AHB
822         if ((priv->cur_seqid == QSPI_CMD_SE) ||
823             (priv->cur_seqid == QSPI_CMD_PP) ||
824             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
825             (priv->cur_seqid == QSPI_CMD_WREAR) ||
826             (priv->cur_seqid == QSPI_CMD_BRWR))
827                 qspi_ahb_invalid(priv);
828 #endif
829
830         return 0;
831 }
832
833 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
834 {
835         u32 mcr_val;
836
837         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
838         if (disable)
839                 mcr_val |= QSPI_MCR_MDIS_MASK;
840         else
841                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
842         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
843 }
844
845 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
846 {
847         u32 smpr_val;
848
849         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
850         smpr_val &= ~clear_bits;
851         smpr_val |= set_bits;
852         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
853 }
854 #ifndef CONFIG_DM_SPI
855 static unsigned long spi_bases[] = {
856         QSPI0_BASE_ADDR,
857 #ifdef CONFIG_MX6SX
858         QSPI1_BASE_ADDR,
859 #endif
860 };
861
862 static unsigned long amba_bases[] = {
863         QSPI0_AMBA_BASE,
864 #ifdef CONFIG_MX6SX
865         QSPI1_AMBA_BASE,
866 #endif
867 };
868
869 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
870 {
871         return container_of(slave, struct fsl_qspi, slave);
872 }
873
874 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
875                 unsigned int max_hz, unsigned int mode)
876 {
877         u32 mcr_val;
878         struct fsl_qspi *qspi;
879         struct fsl_qspi_regs *regs;
880         u32 total_size;
881
882         if (bus >= ARRAY_SIZE(spi_bases))
883                 return NULL;
884
885         if (cs >= FSL_QSPI_FLASH_NUM)
886                 return NULL;
887
888         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
889         if (!qspi)
890                 return NULL;
891
892 #ifdef CONFIG_SYS_FSL_QSPI_BE
893         qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
894 #endif
895
896         regs = (struct fsl_qspi_regs *)spi_bases[bus];
897         qspi->priv.regs = regs;
898         /*
899          * According cs, use different amba_base to choose the
900          * corresponding flash devices.
901          *
902          * If not, only one flash device is used even if passing
903          * different cs using `sf probe`
904          */
905         qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
906
907         qspi->slave.max_write_size = TX_BUFFER_SIZE;
908
909         mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
910         qspi_write32(qspi->priv.flags, &regs->mcr,
911                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
912                      (mcr_val & QSPI_MCR_END_CFD_MASK));
913
914         qspi_cfg_smpr(&qspi->priv,
915                       ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
916                       QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
917
918         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
919         /*
920          * Any read access to non-implemented addresses will provide
921          * undefined results.
922          *
923          * In case single die flash devices, TOP_ADDR_MEMA2 and
924          * TOP_ADDR_MEMB2 should be initialized/programmed to
925          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
926          * setting the size of these devices to 0.  This would ensure
927          * that the complete memory map is assigned to only one flash device.
928          */
929         qspi_write32(qspi->priv.flags, &regs->sfa1ad,
930                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
931         qspi_write32(qspi->priv.flags, &regs->sfa2ad,
932                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
933         qspi_write32(qspi->priv.flags, &regs->sfb1ad,
934                      total_size | amba_bases[bus]);
935         qspi_write32(qspi->priv.flags, &regs->sfb2ad,
936                      total_size | amba_bases[bus]);
937
938         qspi_set_lut(&qspi->priv);
939
940 #ifdef CONFIG_SYS_FSL_QSPI_AHB
941         qspi_init_ahb_read(&qspi->priv);
942 #endif
943
944         qspi_module_disable(&qspi->priv, 0);
945
946         return &qspi->slave;
947 }
948
949 void spi_free_slave(struct spi_slave *slave)
950 {
951         struct fsl_qspi *qspi = to_qspi_spi(slave);
952
953         free(qspi);
954 }
955
956 int spi_claim_bus(struct spi_slave *slave)
957 {
958         return 0;
959 }
960
961 void spi_release_bus(struct spi_slave *slave)
962 {
963         /* Nothing to do */
964 }
965
966 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
967                 const void *dout, void *din, unsigned long flags)
968 {
969         struct fsl_qspi *qspi = to_qspi_spi(slave);
970
971         return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
972 }
973
974 void spi_init(void)
975 {
976         /* Nothing to do */
977 }
978 #else
979 static int fsl_qspi_child_pre_probe(struct udevice *dev)
980 {
981         struct spi_slave *slave = dev_get_parent_priv(dev);
982
983         slave->max_write_size = TX_BUFFER_SIZE;
984
985         return 0;
986 }
987
988 static int fsl_qspi_probe(struct udevice *bus)
989 {
990         u32 mcr_val;
991         u32 amba_size_per_chip;
992         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
993         struct fsl_qspi_priv *priv = dev_get_priv(bus);
994         struct dm_spi_bus *dm_spi_bus;
995         int i, ret;
996
997         dm_spi_bus = bus->uclass_priv;
998
999         dm_spi_bus->max_hz = plat->speed_hz;
1000
1001         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
1002         priv->flags = plat->flags;
1003
1004         priv->speed_hz = plat->speed_hz;
1005         /*
1006          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
1007          * AMBA memory zone should be located on the 0~4GB space
1008          * even on a 64bits cpu.
1009          */
1010         priv->amba_base[0] = (u32)plat->amba_base;
1011         priv->amba_total_size = (u32)plat->amba_total_size;
1012         priv->flash_num = plat->flash_num;
1013         priv->num_chipselect = plat->num_chipselect;
1014
1015         /* make sure controller is not busy anywhere */
1016         ret = wait_for_bit(__func__, &priv->regs->sr,
1017                            QSPI_SR_BUSY_MASK |
1018                            QSPI_SR_AHB_ACC_MASK |
1019                            QSPI_SR_IP_ACC_MASK,
1020                            false, 100, false);
1021
1022         if (ret) {
1023                 debug("ERROR : The controller is busy\n");
1024                 return ret;
1025         }
1026
1027         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
1028         qspi_write32(priv->flags, &priv->regs->mcr,
1029                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
1030                      (mcr_val & QSPI_MCR_END_CFD_MASK));
1031
1032         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1033                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1034
1035         /*
1036          * Assign AMBA memory zone for every chipselect
1037          * QuadSPI has two channels, every channel has two chipselects.
1038          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1039          * into two parts and assign to every channel. This indicate that every
1040          * channel only has one valid chipselect.
1041          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1042          * into four parts and assign to every chipselect.
1043          * Every channel will has two valid chipselects.
1044          */
1045         amba_size_per_chip = priv->amba_total_size >>
1046                              (priv->num_chipselect >> 1);
1047         for (i = 1 ; i < priv->num_chipselect ; i++)
1048                 priv->amba_base[i] =
1049                         amba_size_per_chip + priv->amba_base[i - 1];
1050
1051         /*
1052          * Any read access to non-implemented addresses will provide
1053          * undefined results.
1054          *
1055          * In case single die flash devices, TOP_ADDR_MEMA2 and
1056          * TOP_ADDR_MEMB2 should be initialized/programmed to
1057          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1058          * setting the size of these devices to 0.  This would ensure
1059          * that the complete memory map is assigned to only one flash device.
1060          */
1061         qspi_write32(priv->flags, &priv->regs->sfa1ad,
1062                      priv->amba_base[0] + amba_size_per_chip);
1063         switch (priv->num_chipselect) {
1064         case 1:
1065                 break;
1066         case 2:
1067                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1068                              priv->amba_base[1]);
1069                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1070                              priv->amba_base[1] + amba_size_per_chip);
1071                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1072                              priv->amba_base[1] + amba_size_per_chip);
1073                 break;
1074         case 4:
1075                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1076                              priv->amba_base[2]);
1077                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1078                              priv->amba_base[3]);
1079                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1080                              priv->amba_base[3] + amba_size_per_chip);
1081                 break;
1082         default:
1083                 debug("Error: Unsupported chipselect number %u!\n",
1084                       priv->num_chipselect);
1085                 qspi_module_disable(priv, 1);
1086                 return -EINVAL;
1087         }
1088
1089         qspi_set_lut(priv);
1090
1091 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1092         qspi_init_ahb_read(priv);
1093 #endif
1094
1095         qspi_module_disable(priv, 0);
1096
1097         return 0;
1098 }
1099
1100 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1101 {
1102         struct fdt_resource res_regs, res_mem;
1103         struct fsl_qspi_platdata *plat = bus->platdata;
1104         const void *blob = gd->fdt_blob;
1105         int node = dev_of_offset(bus);
1106         int ret, flash_num = 0, subnode;
1107
1108         if (fdtdec_get_bool(blob, node, "big-endian"))
1109                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1110
1111         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1112                                      "QuadSPI", &res_regs);
1113         if (ret) {
1114                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1115                 return -ENOMEM;
1116         }
1117         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1118                                      "QuadSPI-memory", &res_mem);
1119         if (ret) {
1120                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1121                 return -ENOMEM;
1122         }
1123
1124         /* Count flash numbers */
1125         fdt_for_each_subnode(subnode, blob, node)
1126                 ++flash_num;
1127
1128         if (flash_num == 0) {
1129                 debug("Error: Missing flashes!\n");
1130                 return -ENODEV;
1131         }
1132
1133         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1134                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1135         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1136                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1137
1138         plat->reg_base = res_regs.start;
1139         plat->amba_base = res_mem.start;
1140         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1141         plat->flash_num = flash_num;
1142
1143         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1144               __func__,
1145               (u64)plat->reg_base,
1146               (u64)plat->amba_base,
1147               (u64)plat->amba_total_size,
1148               plat->speed_hz,
1149               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1150               );
1151
1152         return 0;
1153 }
1154
1155 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1156                 const void *dout, void *din, unsigned long flags)
1157 {
1158         struct fsl_qspi_priv *priv;
1159         struct udevice *bus;
1160
1161         bus = dev->parent;
1162         priv = dev_get_priv(bus);
1163
1164         return qspi_xfer(priv, bitlen, dout, din, flags);
1165 }
1166
1167 static int fsl_qspi_claim_bus(struct udevice *dev)
1168 {
1169         struct fsl_qspi_priv *priv;
1170         struct udevice *bus;
1171         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1172         int ret;
1173
1174         bus = dev->parent;
1175         priv = dev_get_priv(bus);
1176
1177         /* make sure controller is not busy anywhere */
1178         ret = wait_for_bit(__func__, &priv->regs->sr,
1179                            QSPI_SR_BUSY_MASK |
1180                            QSPI_SR_AHB_ACC_MASK |
1181                            QSPI_SR_IP_ACC_MASK,
1182                            false, 100, false);
1183
1184         if (ret) {
1185                 debug("ERROR : The controller is busy\n");
1186                 return ret;
1187         }
1188
1189         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1190
1191         qspi_module_disable(priv, 0);
1192
1193         return 0;
1194 }
1195
1196 static int fsl_qspi_release_bus(struct udevice *dev)
1197 {
1198         struct fsl_qspi_priv *priv;
1199         struct udevice *bus;
1200
1201         bus = dev->parent;
1202         priv = dev_get_priv(bus);
1203
1204         qspi_module_disable(priv, 1);
1205
1206         return 0;
1207 }
1208
1209 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1210 {
1211         /* Nothing to do */
1212         return 0;
1213 }
1214
1215 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1216 {
1217         /* Nothing to do */
1218         return 0;
1219 }
1220
1221 static const struct dm_spi_ops fsl_qspi_ops = {
1222         .claim_bus      = fsl_qspi_claim_bus,
1223         .release_bus    = fsl_qspi_release_bus,
1224         .xfer           = fsl_qspi_xfer,
1225         .set_speed      = fsl_qspi_set_speed,
1226         .set_mode       = fsl_qspi_set_mode,
1227 };
1228
1229 static const struct udevice_id fsl_qspi_ids[] = {
1230         { .compatible = "fsl,vf610-qspi" },
1231         { .compatible = "fsl,imx6sx-qspi" },
1232         { }
1233 };
1234
1235 U_BOOT_DRIVER(fsl_qspi) = {
1236         .name   = "fsl_qspi",
1237         .id     = UCLASS_SPI,
1238         .of_match = fsl_qspi_ids,
1239         .ops    = &fsl_qspi_ops,
1240         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1241         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1242         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1243         .probe  = fsl_qspi_probe,
1244         .child_pre_probe = fsl_qspi_child_pre_probe,
1245 };
1246 #endif