drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <linux/iopoll.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include <wait_bit.h>
  18 #include "fsl_qspi.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  23
  24 #define FLASH_STATUS_WEL        0x02
  25
  26 /* SEQID */
  27 #define SEQID_WREN              1
  28 #define SEQID_FAST_READ         2
  29 #define SEQID_RDSR              3
  30 #define SEQID_SE                4
  31 #define SEQID_CHIP_ERASE        5
  32 #define SEQID_PP                6
  33 #define SEQID_RDID              7
  34 #define SEQID_BE_4K             8
  35 #ifdef CONFIG_SPI_FLASH_BAR
  36 #define SEQID_BRRD              9
  37 #define SEQID_BRWR              10
  38 #define SEQID_RDEAR             11
  39 #define SEQID_WREAR             12
  40 #endif
  41 #define SEQID_WRAR              13
  42 #define SEQID_RDAR              14
  43
  44 /* QSPI CMD */
  45 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  46 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  47 #define QSPI_CMD_WREN           0x06    /* Write enable */
  48 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  49 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  50 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  51 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  52 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  53
  54 /* Used for Micron, winbond and Macronix flashes */
  55 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  56 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  57
  58 /* Used for Spansion flashes only. */
  59 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  60 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  61
  62 /* Used for Spansion S25FS-S family flash only. */
  63 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  64 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  65
  66 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  67 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  68 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  69 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  70
  71 /* fsl_qspi_platdata flags */
  72 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  73
  74 /* default SCK frequency, unit: HZ */
  75 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  76
  77 /* QSPI max chipselect signals number */
  78 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  79
  80 /* Controller needs driver to swap endian */
  81 #define QUADSPI_QUIRK_SWAP_ENDIAN       BIT(0)
  82
  83 enum fsl_qspi_devtype {
  84         FSL_QUADSPI_VYBRID,
  85         FSL_QUADSPI_IMX6SX,
  86         FSL_QUADSPI_IMX6UL_7D,
  87         FSL_QUADSPI_IMX7ULP,
  88 };
  89
  90 struct fsl_qspi_devtype_data {
  91         enum fsl_qspi_devtype devtype;
  92         u32 rxfifo;
  93         u32 txfifo;
  94         u32 ahb_buf_size;
  95         u32 driver_data;
  96 };
  97
  98 /**
  99  * struct fsl_qspi_platdata - platform data for Freescale QSPI
 100  *
 101  * @flags: Flags for QSPI QSPI_FLAG_...
 102  * @speed_hz: Default SCK frequency
 103  * @reg_base: Base address of QSPI registers
 104  * @amba_base: Base address of QSPI memory mapping
 105  * @amba_total_size: size of QSPI memory mapping
 106  * @flash_num: Number of active slave devices
 107  * @num_chipselect: Number of QSPI chipselect signals
 108  */
 109 struct fsl_qspi_platdata {
 110         u32 flags;
 111         u32 speed_hz;
 112         fdt_addr_t reg_base;
 113         fdt_addr_t amba_base;
 114         fdt_size_t amba_total_size;
 115         u32 flash_num;
 116         u32 num_chipselect;
 117 };
 118
 119 /**
 120  * struct fsl_qspi_priv - private data for Freescale QSPI
 121  *
 122  * @flags: Flags for QSPI QSPI_FLAG_...
 123  * @bus_clk: QSPI input clk frequency
 124  * @speed_hz: Default SCK frequency
 125  * @cur_seqid: current LUT table sequence id
 126  * @sf_addr: flash access offset
 127  * @amba_base: Base address of QSPI memory mapping of every CS
 128  * @amba_total_size: size of QSPI memory mapping
 129  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 130  * @flash_num: Number of active slave devices
 131  * @num_chipselect: Number of QSPI chipselect signals
 132  * @regs: Point to QSPI register structure for I/O access
 133  */
 134 struct fsl_qspi_priv {
 135         u32 flags;
 136         u32 bus_clk;
 137         u32 speed_hz;
 138         u32 cur_seqid;
 139         u32 sf_addr;
 140         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 141         u32 amba_total_size;
 142         u32 cur_amba_base;
 143         u32 flash_num;
 144         u32 num_chipselect;
 145         struct fsl_qspi_regs *regs;
 146         struct fsl_qspi_devtype_data *devtype_data;
 147 };
 148
 149 static const struct fsl_qspi_devtype_data vybrid_data = {
 150         .devtype = FSL_QUADSPI_VYBRID,
 151         .rxfifo = 128,
 152         .txfifo = 64,
 153         .ahb_buf_size = 1024,
 154         .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
 155 };
 156
 157 static const struct fsl_qspi_devtype_data imx6sx_data = {
 158         .devtype = FSL_QUADSPI_IMX6SX,
 159         .rxfifo = 128,
 160         .txfifo = 512,
 161         .ahb_buf_size = 1024,
 162         .driver_data = 0,
 163 };
 164
 165 static const struct fsl_qspi_devtype_data imx6ul_7d_data = {
 166         .devtype = FSL_QUADSPI_IMX6UL_7D,
 167         .rxfifo = 128,
 168         .txfifo = 512,
 169         .ahb_buf_size = 1024,
 170         .driver_data = 0,
 171 };
 172
 173 static const struct fsl_qspi_devtype_data imx7ulp_data = {
 174         .devtype = FSL_QUADSPI_IMX7ULP,
 175         .rxfifo = 64,
 176         .txfifo = 64,
 177         .ahb_buf_size = 128,
 178         .driver_data = 0,
 179 };
 180
 181 static u32 qspi_read32(u32 flags, u32 *addr)
 182 {
 183         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 184                 in_be32(addr) : in_le32(addr);
 185 }
 186
 187 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 188 {
 189         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 190                 out_be32(addr, val) : out_le32(addr, val);
 191 }
 192
 193 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
 194 {
 195         u32 val;
 196         u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
 197                    QSPI_SR_IP_ACC_MASK;
 198
 199         if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
 200                 mask = (u32)cpu_to_be32(mask);
 201
 202         return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
 203 }
 204
 205 /* QSPI support swapping the flash read/write data
 206  * in hardware for LS102xA, but not for VF610 */
 207 static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data)
 208 {
 209         if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN)
 210                 return swab32(data);
 211         else
 212                 return data;
 213 }
 214
 215 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 216 {
 217         struct fsl_qspi_regs *regs = priv->regs;
 218         u32 lut_base;
 219
 220         /* Unlock the LUT */
 221         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 222         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 223
 224         /* Write Enable */
 225         lut_base = SEQID_WREN * 4;
 226         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 227                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 228         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 229         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 230         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 231
 232         /* Fast Read */
 233         lut_base = SEQID_FAST_READ * 4;
 234 #ifdef CONFIG_SPI_FLASH_BAR
 235         qspi_write32(priv->flags, &regs->lut[lut_base],
 236                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 237                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 238                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 239 #else
 240         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 241                 qspi_write32(priv->flags, &regs->lut[lut_base],
 242                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 243                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 244                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 245         else
 246                 qspi_write32(priv->flags, &regs->lut[lut_base],
 247                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 248                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 249                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 250                              INSTR1(LUT_ADDR));
 251 #endif
 252         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 253                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 254                      OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) |
 255                      INSTR1(LUT_READ));
 256         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 257         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 258
 259         /* Read Status */
 260         lut_base = SEQID_RDSR * 4;
 261         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 262                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 263                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 264         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 265         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 266         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 267
 268         /* Erase a sector */
 269         lut_base = SEQID_SE * 4;
 270 #ifdef CONFIG_SPI_FLASH_BAR
 271         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 272                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 273                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 274 #else
 275         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 276                 qspi_write32(priv->flags, &regs->lut[lut_base],
 277                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 278                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 279                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 280         else
 281                 qspi_write32(priv->flags, &regs->lut[lut_base],
 282                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 283                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 284                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 285 #endif
 286         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 287         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 288         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 289
 290         /* Erase the whole chip */
 291         lut_base = SEQID_CHIP_ERASE * 4;
 292         qspi_write32(priv->flags, &regs->lut[lut_base],
 293                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 294                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 295         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 296         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 297         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 298
 299         /* Page Program */
 300         lut_base = SEQID_PP * 4;
 301 #ifdef CONFIG_SPI_FLASH_BAR
 302         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 303                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 304                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 305 #else
 306         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 307                 qspi_write32(priv->flags, &regs->lut[lut_base],
 308                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 309                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 310                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 311         else
 312                 qspi_write32(priv->flags, &regs->lut[lut_base],
 313                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 314                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 315                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 316 #endif
 317         /* Use IDATSZ in IPCR to determine the size and here set 0. */
 318         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 319                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 320         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 321         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 322
 323         /* READ ID */
 324         lut_base = SEQID_RDID * 4;
 325         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 326                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 327                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 328         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 329         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 330         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 331
 332         /* SUB SECTOR 4K ERASE */
 333         lut_base = SEQID_BE_4K * 4;
 334         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 335                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 336                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 337
 338 #ifdef CONFIG_SPI_FLASH_BAR
 339         /*
 340          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 341          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 342          * initialization.
 343          */
 344         lut_base = SEQID_BRRD * 4;
 345         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 346                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 347                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 348
 349         lut_base = SEQID_BRWR * 4;
 350         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 351                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 352                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 353
 354         lut_base = SEQID_RDEAR * 4;
 355         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 356                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 357                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 358
 359         lut_base = SEQID_WREAR * 4;
 360         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 361                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 362                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 363 #endif
 364
 365         /*
 366          * Read any device register.
 367          * Used for Spansion S25FS-S family flash only.
 368          */
 369         lut_base = SEQID_RDAR * 4;
 370         qspi_write32(priv->flags, &regs->lut[lut_base],
 371                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 372                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 373                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 374         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 375                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 376                      OPRND1(1) | PAD1(LUT_PAD1) |
 377                      INSTR1(LUT_READ));
 378
 379         /*
 380          * Write any device register.
 381          * Used for Spansion S25FS-S family flash only.
 382          */
 383         lut_base = SEQID_WRAR * 4;
 384         qspi_write32(priv->flags, &regs->lut[lut_base],
 385                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 386                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 387                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 388         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 389                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 390
 391         /* Lock the LUT */
 392         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 393         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 394 }
 395
 396 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 397 /*
 398  * If we have changed the content of the flash by writing or erasing,
 399  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 400  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 401  * domain at the same time.
 402  */
 403 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 404 {
 405         struct fsl_qspi_regs *regs = priv->regs;
 406         u32 reg;
 407
 408         reg = qspi_read32(priv->flags, &regs->mcr);
 409         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 410         qspi_write32(priv->flags, &regs->mcr, reg);
 411
 412         /*
 413          * The minimum delay : 1 AHB + 2 SFCK clocks.
 414          * Delay 1 us is enough.
 415          */
 416         udelay(1);
 417
 418         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 419         qspi_write32(priv->flags, &regs->mcr, reg);
 420 }
 421
 422 /* Read out the data from the AHB buffer. */
 423 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 424 {
 425         struct fsl_qspi_regs *regs = priv->regs;
 426         u32 mcr_reg;
 427         void *rx_addr;
 428
 429         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 430
 431         qspi_write32(priv->flags, &regs->mcr,
 432                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 433                      mcr_reg);
 434
 435         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 436         /* Read out the data directly from the AHB buffer. */
 437         memcpy(rxbuf, rx_addr, len);
 438
 439         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 440 }
 441
 442 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 443 {
 444         u32 reg, reg2;
 445         struct fsl_qspi_regs *regs = priv->regs;
 446
 447         reg = qspi_read32(priv->flags, &regs->mcr);
 448         /* Disable the module */
 449         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 450
 451         /* Set the Sampling Register for DDR */
 452         reg2 = qspi_read32(priv->flags, &regs->smpr);
 453         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 454         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 455         qspi_write32(priv->flags, &regs->smpr, reg2);
 456
 457         /* Enable the module again (enable the DDR too) */
 458         reg |= QSPI_MCR_DDR_EN_MASK;
 459         /* Enable bit 29 for imx6sx */
 460         reg |= BIT(29);
 461         qspi_write32(priv->flags, &regs->mcr, reg);
 462
 463         /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc
 464          * These two bits are reserved on other platforms
 465          */
 466         reg = qspi_read32(priv->flags, &regs->flshcr);
 467         reg &= ~(BIT(17));
 468         reg |= BIT(16);
 469         qspi_write32(priv->flags, &regs->flshcr, reg);
 470 }
 471
 472 /*
 473  * There are two different ways to read out the data from the flash:
 474  *  the "IP Command Read" and the "AHB Command Read".
 475  *
 476  * The IC guy suggests we use the "AHB Command Read" which is faster
 477  * then the "IP Command Read". (What's more is that there is a bug in
 478  * the "IP Command Read" in the Vybrid.)
 479  *
 480  * After we set up the registers for the "AHB Command Read", we can use
 481  * the memcpy to read the data directly. A "missed" access to the buffer
 482  * causes the controller to clear the buffer, and use the sequence pointed
 483  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 484  */
 485 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 486 {
 487         struct fsl_qspi_regs *regs = priv->regs;
 488
 489         /* AHB configuration for access buffer 0/1/2 .*/
 490         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 491         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 492         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 493         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 494                      ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT));
 495
 496         /* We only use the buffer3 */
 497         qspi_write32(priv->flags, &regs->buf0ind, 0);
 498         qspi_write32(priv->flags, &regs->buf1ind, 0);
 499         qspi_write32(priv->flags, &regs->buf2ind, 0);
 500
 501         /*
 502          * Set the default lut sequence for AHB Read.
 503          * Parallel mode is disabled.
 504          */
 505         qspi_write32(priv->flags, &regs->bfgencr,
 506                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 507
 508         /*Enable DDR Mode*/
 509         qspi_enable_ddr_mode(priv);
 510 }
 511 #endif
 512
 513 #ifdef CONFIG_SPI_FLASH_BAR
 514 /* Bank register read/write, EAR register read/write */
 515 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 516 {
 517         struct fsl_qspi_regs *regs = priv->regs;
 518         u32 reg, mcr_reg, data, seqid;
 519
 520         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 521         qspi_write32(priv->flags, &regs->mcr,
 522                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 523                      mcr_reg);
 524         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 525
 526         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 527
 528         if (priv->cur_seqid == QSPI_CMD_BRRD)
 529                 seqid = SEQID_BRRD;
 530         else
 531                 seqid = SEQID_RDEAR;
 532
 533         qspi_write32(priv->flags, &regs->ipcr,
 534                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 535
 536         /* Wait previous command complete */
 537         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 538                 ;
 539
 540         while (1) {
 541                 WATCHDOG_RESET();
 542
 543                 reg = qspi_read32(priv->flags, &regs->rbsr);
 544                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 545                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 546                         data = qspi_endian_xchg(priv, data);
 547                         memcpy(rxbuf, &data, len);
 548                         qspi_write32(priv->flags, &regs->mcr,
 549                                      qspi_read32(priv->flags, &regs->mcr) |
 550                                      QSPI_MCR_CLR_RXF_MASK);
 551                         break;
 552                 }
 553         }
 554
 555         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 556 }
 557 #endif
 558
 559 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 560 {
 561         struct fsl_qspi_regs *regs = priv->regs;
 562         u32 mcr_reg, rbsr_reg, data, size;
 563         int i;
 564
 565         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 566         qspi_write32(priv->flags, &regs->mcr,
 567                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 568                      mcr_reg);
 569         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 570
 571         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 572
 573         qspi_write32(priv->flags, &regs->ipcr,
 574                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 575         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 576                 ;
 577
 578         i = 0;
 579         while ((priv->devtype_data->rxfifo >= len) && (len > 0)) {
 580                 WATCHDOG_RESET();
 581
 582                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 583                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 584                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 585                         data = qspi_endian_xchg(priv, data);
 586                         size = (len < 4) ? len : 4;
 587                         memcpy(rxbuf, &data, size);
 588                         len -= size;
 589                         rxbuf++;
 590                         i++;
 591                 }
 592         }
 593
 594         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 595 }
 596
 597 /* If not use AHB read, read data from ip interface */
 598 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 599 {
 600         struct fsl_qspi_regs *regs = priv->regs;
 601         u32 mcr_reg, data;
 602         int i, size;
 603         u32 to_or_from;
 604         u32 seqid;
 605
 606         if (priv->cur_seqid == QSPI_CMD_RDAR)
 607                 seqid = SEQID_RDAR;
 608         else
 609                 seqid = SEQID_FAST_READ;
 610
 611         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 612         qspi_write32(priv->flags, &regs->mcr,
 613                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 614                      mcr_reg);
 615         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 616
 617         to_or_from = priv->sf_addr + priv->cur_amba_base;
 618
 619         while (len > 0) {
 620                 WATCHDOG_RESET();
 621
 622                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 623
 624                 size = (len > priv->devtype_data->rxfifo) ?
 625                         priv->devtype_data->rxfifo : len;
 626
 627                 qspi_write32(priv->flags, &regs->ipcr,
 628                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 629                              size);
 630                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 631                         ;
 632
 633                 to_or_from += size;
 634                 len -= size;
 635
 636                 i = 0;
 637                 while ((priv->devtype_data->rxfifo >= size) && (size > 0)) {
 638                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 639                         data = qspi_endian_xchg(priv, data);
 640                         if (size < 4)
 641                                 memcpy(rxbuf, &data, size);
 642                         else
 643                                 memcpy(rxbuf, &data, 4);
 644                         rxbuf++;
 645                         size -= 4;
 646                         i++;
 647                 }
 648                 qspi_write32(priv->flags, &regs->mcr,
 649                              qspi_read32(priv->flags, &regs->mcr) |
 650                              QSPI_MCR_CLR_RXF_MASK);
 651         }
 652
 653         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 654 }
 655
 656 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 657 {
 658         struct fsl_qspi_regs *regs = priv->regs;
 659         u32 mcr_reg, data, reg, status_reg, seqid;
 660         int i, size, tx_size;
 661         u32 to_or_from = 0;
 662
 663         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 664         qspi_write32(priv->flags, &regs->mcr,
 665                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 666                      mcr_reg);
 667         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 668
 669         status_reg = 0;
 670         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 671                 WATCHDOG_RESET();
 672
 673                 qspi_write32(priv->flags, &regs->ipcr,
 674                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 675                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 676                         ;
 677
 678                 qspi_write32(priv->flags, &regs->ipcr,
 679                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 680                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 681                         ;
 682
 683                 reg = qspi_read32(priv->flags, &regs->rbsr);
 684                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 685                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 686                         status_reg = qspi_endian_xchg(priv, status_reg);
 687                 }
 688                 qspi_write32(priv->flags, &regs->mcr,
 689                              qspi_read32(priv->flags, &regs->mcr) |
 690                              QSPI_MCR_CLR_RXF_MASK);
 691         }
 692
 693         /* Default is page programming */
 694         seqid = SEQID_PP;
 695         if (priv->cur_seqid == QSPI_CMD_WRAR)
 696                 seqid = SEQID_WRAR;
 697 #ifdef CONFIG_SPI_FLASH_BAR
 698         if (priv->cur_seqid == QSPI_CMD_BRWR)
 699                 seqid = SEQID_BRWR;
 700         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 701                 seqid = SEQID_WREAR;
 702 #endif
 703
 704         to_or_from = priv->sf_addr + priv->cur_amba_base;
 705
 706         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 707
 708         tx_size = (len > priv->devtype_data->txfifo) ?
 709                 priv->devtype_data->txfifo : len;
 710
 711         size = tx_size / 16;
 712         /*
 713          * There must be atleast 128bit data
 714          * available in TX FIFO for any pop operation
 715          */
 716         if (tx_size % 16)
 717                 size++;
 718         for (i = 0; i < size * 4; i++) {
 719                 memcpy(&data, txbuf, 4);
 720                 data = qspi_endian_xchg(priv, data);
 721                 qspi_write32(priv->flags, &regs->tbdr, data);
 722                 txbuf += 4;
 723         }
 724
 725         qspi_write32(priv->flags, &regs->ipcr,
 726                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 727         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 728                 ;
 729
 730         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 731 }
 732
 733 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 734 {
 735         struct fsl_qspi_regs *regs = priv->regs;
 736         u32 mcr_reg, reg, data;
 737
 738         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 739         qspi_write32(priv->flags, &regs->mcr,
 740                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 741                      mcr_reg);
 742         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 743
 744         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 745
 746         qspi_write32(priv->flags, &regs->ipcr,
 747                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 748         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 749                 ;
 750
 751         while (1) {
 752                 WATCHDOG_RESET();
 753
 754                 reg = qspi_read32(priv->flags, &regs->rbsr);
 755                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 756                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 757                         data = qspi_endian_xchg(priv, data);
 758                         memcpy(rxbuf, &data, len);
 759                         qspi_write32(priv->flags, &regs->mcr,
 760                                      qspi_read32(priv->flags, &regs->mcr) |
 761                                      QSPI_MCR_CLR_RXF_MASK);
 762                         break;
 763                 }
 764         }
 765
 766         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 767 }
 768
 769 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 770 {
 771         struct fsl_qspi_regs *regs = priv->regs;
 772         u32 mcr_reg;
 773         u32 to_or_from = 0;
 774
 775         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 776         qspi_write32(priv->flags, &regs->mcr,
 777                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 778                      mcr_reg);
 779         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 780
 781         to_or_from = priv->sf_addr + priv->cur_amba_base;
 782         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 783
 784         qspi_write32(priv->flags, &regs->ipcr,
 785                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 786         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 787                 ;
 788
 789         if (priv->cur_seqid == QSPI_CMD_SE) {
 790                 qspi_write32(priv->flags, &regs->ipcr,
 791                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 792         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 793                 qspi_write32(priv->flags, &regs->ipcr,
 794                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 795         }
 796         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 797                 ;
 798
 799         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 800 }
 801
 802 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 803                 const void *dout, void *din, unsigned long flags)
 804 {
 805         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 806         static u32 wr_sfaddr;
 807         u32 txbuf;
 808
 809         WATCHDOG_RESET();
 810
 811         if (dout) {
 812                 if (flags & SPI_XFER_BEGIN) {
 813                         priv->cur_seqid = *(u8 *)dout;
 814                         memcpy(&txbuf, dout, 4);
 815                 }
 816
 817                 if (flags == SPI_XFER_END) {
 818                         priv->sf_addr = wr_sfaddr;
 819                         qspi_op_write(priv, (u8 *)dout, bytes);
 820                         return 0;
 821                 }
 822
 823                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 824                     priv->cur_seqid == QSPI_CMD_RDAR) {
 825                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 826                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 827                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 828                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 829                         qspi_op_erase(priv);
 830                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 831                            priv->cur_seqid == QSPI_CMD_WRAR) {
 832                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 833                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 834                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 835 #ifdef CONFIG_SPI_FLASH_BAR
 836                         wr_sfaddr = 0;
 837 #endif
 838                 }
 839         }
 840
 841         if (din) {
 842                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 843 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 844                         qspi_ahb_read(priv, din, bytes);
 845 #else
 846                         qspi_op_read(priv, din, bytes);
 847 #endif
 848                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 849                         qspi_op_read(priv, din, bytes);
 850                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 851                         qspi_op_rdid(priv, din, bytes);
 852                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 853                         qspi_op_rdsr(priv, din, bytes);
 854 #ifdef CONFIG_SPI_FLASH_BAR
 855                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 856                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 857                         priv->sf_addr = 0;
 858                         qspi_op_rdbank(priv, din, bytes);
 859                 }
 860 #endif
 861         }
 862
 863 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 864         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 865             (priv->cur_seqid == QSPI_CMD_PP) ||
 866             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 867             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 868             (priv->cur_seqid == QSPI_CMD_BRWR))
 869                 qspi_ahb_invalid(priv);
 870 #endif
 871
 872         return 0;
 873 }
 874
 875 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 876 {
 877         u32 mcr_val;
 878
 879         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 880         if (disable)
 881                 mcr_val |= QSPI_MCR_MDIS_MASK;
 882         else
 883                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 884         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 885 }
 886
 887 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 888 {
 889         u32 smpr_val;
 890
 891         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 892         smpr_val &= ~clear_bits;
 893         smpr_val |= set_bits;
 894         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 895 }
 896
 897 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 898 {
 899         struct spi_slave *slave = dev_get_parent_priv(dev);
 900         struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev));
 901
 902         slave->max_write_size = priv->devtype_data->txfifo;
 903
 904         return 0;
 905 }
 906
 907 static int fsl_qspi_probe(struct udevice *bus)
 908 {
 909         u32 amba_size_per_chip;
 910         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 911         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 912         struct dm_spi_bus *dm_spi_bus;
 913         int i, ret;
 914
 915         dm_spi_bus = bus->uclass_priv;
 916
 917         dm_spi_bus->max_hz = plat->speed_hz;
 918
 919         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 920         priv->flags = plat->flags;
 921
 922         priv->speed_hz = plat->speed_hz;
 923         /*
 924          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 925          * AMBA memory zone should be located on the 0~4GB space
 926          * even on a 64bits cpu.
 927          */
 928         priv->amba_base[0] = (u32)plat->amba_base;
 929         priv->amba_total_size = (u32)plat->amba_total_size;
 930         priv->flash_num = plat->flash_num;
 931         priv->num_chipselect = plat->num_chipselect;
 932
 933         priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus);
 934         if (!priv->devtype_data) {
 935                 printf("ERROR : No devtype_data found\n");
 936                 return -ENODEV;
 937         }
 938
 939         debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n",
 940                 priv->devtype_data->devtype,
 941                 priv->devtype_data->txfifo,
 942                 priv->devtype_data->rxfifo,
 943                 priv->devtype_data->ahb_buf_size,
 944                 priv->devtype_data->driver_data);
 945
 946         /* make sure controller is not busy anywhere */
 947         ret = is_controller_busy(priv);
 948
 949         if (ret) {
 950                 debug("ERROR : The controller is busy\n");
 951                 return ret;
 952         }
 953
 954         qspi_write32(priv->flags, &priv->regs->mcr,
 955                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 956                      QSPI_MCR_END_CFD_LE);
 957
 958         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 959                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 960
 961         /*
 962          * Assign AMBA memory zone for every chipselect
 963          * QuadSPI has two channels, every channel has two chipselects.
 964          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
 965          * into two parts and assign to every channel. This indicate that every
 966          * channel only has one valid chipselect.
 967          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
 968          * into four parts and assign to every chipselect.
 969          * Every channel will has two valid chipselects.
 970          */
 971         amba_size_per_chip = priv->amba_total_size >>
 972                              (priv->num_chipselect >> 1);
 973         for (i = 1 ; i < priv->num_chipselect ; i++)
 974                 priv->amba_base[i] =
 975                         amba_size_per_chip + priv->amba_base[i - 1];
 976
 977         /*
 978          * Any read access to non-implemented addresses will provide
 979          * undefined results.
 980          *
 981          * In case single die flash devices, TOP_ADDR_MEMA2 and
 982          * TOP_ADDR_MEMB2 should be initialized/programmed to
 983          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 984          * setting the size of these devices to 0.  This would ensure
 985          * that the complete memory map is assigned to only one flash device.
 986          */
 987         qspi_write32(priv->flags, &priv->regs->sfa1ad,
 988                      priv->amba_base[0] + amba_size_per_chip);
 989         switch (priv->num_chipselect) {
 990         case 1:
 991                 break;
 992         case 2:
 993                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
 994                              priv->amba_base[1]);
 995                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
 996                              priv->amba_base[1] + amba_size_per_chip);
 997                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
 998                              priv->amba_base[1] + amba_size_per_chip);
 999                 break;
1000         case 4:
1001                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1002                              priv->amba_base[2]);
1003                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1004                              priv->amba_base[3]);
1005                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1006                              priv->amba_base[3] + amba_size_per_chip);
1007                 break;
1008         default:
1009                 debug("Error: Unsupported chipselect number %u!\n",
1010                       priv->num_chipselect);
1011                 qspi_module_disable(priv, 1);
1012                 return -EINVAL;
1013         }
1014
1015         qspi_set_lut(priv);
1016
1017 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1018         qspi_init_ahb_read(priv);
1019 #endif
1020
1021         qspi_module_disable(priv, 0);
1022
1023         return 0;
1024 }
1025
1026 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1027 {
1028         struct fdt_resource res_regs, res_mem;
1029         struct fsl_qspi_platdata *plat = bus->platdata;
1030         const void *blob = gd->fdt_blob;
1031         int node = dev_of_offset(bus);
1032         int ret, flash_num = 0, subnode;
1033
1034         if (fdtdec_get_bool(blob, node, "big-endian"))
1035                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1036
1037         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1038                                      "QuadSPI", &res_regs);
1039         if (ret) {
1040                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1041                 return -ENOMEM;
1042         }
1043         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1044                                      "QuadSPI-memory", &res_mem);
1045         if (ret) {
1046                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1047                 return -ENOMEM;
1048         }
1049
1050         /* Count flash numbers */
1051         fdt_for_each_subnode(subnode, blob, node)
1052                 ++flash_num;
1053
1054         if (flash_num == 0) {
1055                 debug("Error: Missing flashes!\n");
1056                 return -ENODEV;
1057         }
1058
1059         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1060                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1061         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1062                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1063
1064         plat->reg_base = res_regs.start;
1065         plat->amba_base = res_mem.start;
1066         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1067         plat->flash_num = flash_num;
1068
1069         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1070               __func__,
1071               (u64)plat->reg_base,
1072               (u64)plat->amba_base,
1073               (u64)plat->amba_total_size,
1074               plat->speed_hz,
1075               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1076               );
1077
1078         return 0;
1079 }
1080
1081 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1082                 const void *dout, void *din, unsigned long flags)
1083 {
1084         struct fsl_qspi_priv *priv;
1085         struct udevice *bus;
1086
1087         bus = dev->parent;
1088         priv = dev_get_priv(bus);
1089
1090         return qspi_xfer(priv, bitlen, dout, din, flags);
1091 }
1092
1093 static int fsl_qspi_claim_bus(struct udevice *dev)
1094 {
1095         struct fsl_qspi_priv *priv;
1096         struct udevice *bus;
1097         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1098         int ret;
1099
1100         bus = dev->parent;
1101         priv = dev_get_priv(bus);
1102
1103         /* make sure controller is not busy anywhere */
1104         ret = is_controller_busy(priv);
1105
1106         if (ret) {
1107                 debug("ERROR : The controller is busy\n");
1108                 return ret;
1109         }
1110
1111         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1112
1113         qspi_module_disable(priv, 0);
1114
1115         return 0;
1116 }
1117
1118 static int fsl_qspi_release_bus(struct udevice *dev)
1119 {
1120         struct fsl_qspi_priv *priv;
1121         struct udevice *bus;
1122
1123         bus = dev->parent;
1124         priv = dev_get_priv(bus);
1125
1126         qspi_module_disable(priv, 1);
1127
1128         return 0;
1129 }
1130
1131 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1132 {
1133         /* Nothing to do */
1134         return 0;
1135 }
1136
1137 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1138 {
1139         /* Nothing to do */
1140         return 0;
1141 }
1142
1143 static const struct dm_spi_ops fsl_qspi_ops = {
1144         .claim_bus      = fsl_qspi_claim_bus,
1145         .release_bus    = fsl_qspi_release_bus,
1146         .xfer           = fsl_qspi_xfer,
1147         .set_speed      = fsl_qspi_set_speed,
1148         .set_mode       = fsl_qspi_set_mode,
1149 };
1150
1151 static const struct udevice_id fsl_qspi_ids[] = {
1152         { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data },
1153         { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data },
1154         { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data },
1155         { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data },
1156         { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data },
1157         { }
1158 };
1159
1160 U_BOOT_DRIVER(fsl_qspi) = {
1161         .name   = "fsl_qspi",
1162         .id     = UCLASS_SPI,
1163         .of_match = fsl_qspi_ids,
1164         .ops    = &fsl_qspi_ops,
1165         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1166         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1167         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1168         .probe  = fsl_qspi_probe,
1169         .child_pre_probe = fsl_qspi_child_pre_probe,
1170 };