drivers/spi/fsl_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   4  *
   5  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <asm/io.h>
  12 #include <linux/sizes.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15 #include <watchdog.h>
  16 #include <wait_bit.h>
  17 #include "fsl_qspi.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define RX_BUFFER_SIZE          0x80
  22 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
  23         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
  24 #define TX_BUFFER_SIZE          0x200
  25 #else
  26 #define TX_BUFFER_SIZE          0x40
  27 #endif
  28
  29 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  30
  31 #define FLASH_STATUS_WEL        0x02
  32
  33 /* SEQID */
  34 #define SEQID_WREN              1
  35 #define SEQID_FAST_READ         2
  36 #define SEQID_RDSR              3
  37 #define SEQID_SE                4
  38 #define SEQID_CHIP_ERASE        5
  39 #define SEQID_PP                6
  40 #define SEQID_RDID              7
  41 #define SEQID_BE_4K             8
  42 #ifdef CONFIG_SPI_FLASH_BAR
  43 #define SEQID_BRRD              9
  44 #define SEQID_BRWR              10
  45 #define SEQID_RDEAR             11
  46 #define SEQID_WREAR             12
  47 #endif
  48 #define SEQID_WRAR              13
  49 #define SEQID_RDAR              14
  50
  51 /* QSPI CMD */
  52 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  53 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  54 #define QSPI_CMD_WREN           0x06    /* Write enable */
  55 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  56 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  57 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  58 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  59 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  60
  61 /* Used for Micron, winbond and Macronix flashes */
  62 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  63 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  64
  65 /* Used for Spansion flashes only. */
  66 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  67 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  68
  69 /* Used for Spansion S25FS-S family flash only. */
  70 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  71 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  72
  73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  74 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  75 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  76 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  77
  78 /* fsl_qspi_platdata flags */
  79 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  80
  81 /* default SCK frequency, unit: HZ */
  82 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  83
  84 /* QSPI max chipselect signals number */
  85 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  86
  87 #ifdef CONFIG_DM_SPI
  88 /**
  89  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  90  *
  91  * @flags: Flags for QSPI QSPI_FLAG_...
  92  * @speed_hz: Default SCK frequency
  93  * @reg_base: Base address of QSPI registers
  94  * @amba_base: Base address of QSPI memory mapping
  95  * @amba_total_size: size of QSPI memory mapping
  96  * @flash_num: Number of active slave devices
  97  * @num_chipselect: Number of QSPI chipselect signals
  98  */
  99 struct fsl_qspi_platdata {
 100         u32 flags;
 101         u32 speed_hz;
 102         fdt_addr_t reg_base;
 103         fdt_addr_t amba_base;
 104         fdt_size_t amba_total_size;
 105         u32 flash_num;
 106         u32 num_chipselect;
 107 };
 108 #endif
 109
 110 /**
 111  * struct fsl_qspi_priv - private data for Freescale QSPI
 112  *
 113  * @flags: Flags for QSPI QSPI_FLAG_...
 114  * @bus_clk: QSPI input clk frequency
 115  * @speed_hz: Default SCK frequency
 116  * @cur_seqid: current LUT table sequence id
 117  * @sf_addr: flash access offset
 118  * @amba_base: Base address of QSPI memory mapping of every CS
 119  * @amba_total_size: size of QSPI memory mapping
 120  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 121  * @flash_num: Number of active slave devices
 122  * @num_chipselect: Number of QSPI chipselect signals
 123  * @regs: Point to QSPI register structure for I/O access
 124  */
 125 struct fsl_qspi_priv {
 126         u32 flags;
 127         u32 bus_clk;
 128         u32 speed_hz;
 129         u32 cur_seqid;
 130         u32 sf_addr;
 131         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 132         u32 amba_total_size;
 133         u32 cur_amba_base;
 134         u32 flash_num;
 135         u32 num_chipselect;
 136         struct fsl_qspi_regs *regs;
 137 };
 138
 139 #ifndef CONFIG_DM_SPI
 140 struct fsl_qspi {
 141         struct spi_slave slave;
 142         struct fsl_qspi_priv priv;
 143 };
 144 #endif
 145
 146 static u32 qspi_read32(u32 flags, u32 *addr)
 147 {
 148         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 149                 in_be32(addr) : in_le32(addr);
 150 }
 151
 152 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 153 {
 154         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 155                 out_be32(addr, val) : out_le32(addr, val);
 156 }
 157
 158 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
 159 {
 160         u32 val;
 161         const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
 162                          QSPI_SR_IP_ACC_MASK;
 163         unsigned int retry = 5;
 164
 165         do {
 166                 val = qspi_read32(priv->flags, &priv->regs->sr);
 167
 168                 if ((~val & mask) == mask)
 169                         return 0;
 170
 171                 udelay(1);
 172         } while (--retry);
 173
 174         return -ETIMEDOUT;
 175 }
 176
 177 /* QSPI support swapping the flash read/write data
 178  * in hardware for LS102xA, but not for VF610 */
 179 static inline u32 qspi_endian_xchg(u32 data)
 180 {
 181 #ifdef CONFIG_VF610
 182         return swab32(data);
 183 #else
 184         return data;
 185 #endif
 186 }
 187
 188 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 189 {
 190         struct fsl_qspi_regs *regs = priv->regs;
 191         u32 lut_base;
 192
 193         /* Unlock the LUT */
 194         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 195         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 196
 197         /* Write Enable */
 198         lut_base = SEQID_WREN * 4;
 199         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 200                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 201         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 202         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 203         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 204
 205         /* Fast Read */
 206         lut_base = SEQID_FAST_READ * 4;
 207 #ifdef CONFIG_SPI_FLASH_BAR
 208         qspi_write32(priv->flags, &regs->lut[lut_base],
 209                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 210                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 211                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 212 #else
 213         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 214                 qspi_write32(priv->flags, &regs->lut[lut_base],
 215                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 216                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 217                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 218         else
 219                 qspi_write32(priv->flags, &regs->lut[lut_base],
 220                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 221                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 222                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 223                              INSTR1(LUT_ADDR));
 224 #endif
 225         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 226                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 227                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 228                      INSTR1(LUT_READ));
 229         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 230         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 231
 232         /* Read Status */
 233         lut_base = SEQID_RDSR * 4;
 234         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 235                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 236                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 237         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 238         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 239         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 240
 241         /* Erase a sector */
 242         lut_base = SEQID_SE * 4;
 243 #ifdef CONFIG_SPI_FLASH_BAR
 244         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 245                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 246                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 247 #else
 248         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 249                 qspi_write32(priv->flags, &regs->lut[lut_base],
 250                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 251                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 252                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 253         else
 254                 qspi_write32(priv->flags, &regs->lut[lut_base],
 255                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 256                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 257                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 258 #endif
 259         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 260         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 261         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 262
 263         /* Erase the whole chip */
 264         lut_base = SEQID_CHIP_ERASE * 4;
 265         qspi_write32(priv->flags, &regs->lut[lut_base],
 266                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 267                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 268         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 269         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 270         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 271
 272         /* Page Program */
 273         lut_base = SEQID_PP * 4;
 274 #ifdef CONFIG_SPI_FLASH_BAR
 275         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 276                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 277                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 278 #else
 279         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 280                 qspi_write32(priv->flags, &regs->lut[lut_base],
 281                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 282                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 283                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 284         else
 285                 qspi_write32(priv->flags, &regs->lut[lut_base],
 286                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 287                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 288                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 289 #endif
 290 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
 291         defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
 292         /*
 293          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 294          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 295          */
 296         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 297                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 298 #else
 299         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 300                      OPRND0(TX_BUFFER_SIZE) |
 301                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 302 #endif
 303         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 304         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 305
 306         /* READ ID */
 307         lut_base = SEQID_RDID * 4;
 308         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 309                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 310                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 311         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 312         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 313         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 314
 315         /* SUB SECTOR 4K ERASE */
 316         lut_base = SEQID_BE_4K * 4;
 317         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 318                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 319                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 320
 321 #ifdef CONFIG_SPI_FLASH_BAR
 322         /*
 323          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 324          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 325          * initialization.
 326          */
 327         lut_base = SEQID_BRRD * 4;
 328         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 329                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 330                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 331
 332         lut_base = SEQID_BRWR * 4;
 333         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 334                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 335                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 336
 337         lut_base = SEQID_RDEAR * 4;
 338         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 339                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 340                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 341
 342         lut_base = SEQID_WREAR * 4;
 343         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 344                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 345                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 346 #endif
 347
 348         /*
 349          * Read any device register.
 350          * Used for Spansion S25FS-S family flash only.
 351          */
 352         lut_base = SEQID_RDAR * 4;
 353         qspi_write32(priv->flags, &regs->lut[lut_base],
 354                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 355                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 356                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 357         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 358                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 359                      OPRND1(1) | PAD1(LUT_PAD1) |
 360                      INSTR1(LUT_READ));
 361
 362         /*
 363          * Write any device register.
 364          * Used for Spansion S25FS-S family flash only.
 365          */
 366         lut_base = SEQID_WRAR * 4;
 367         qspi_write32(priv->flags, &regs->lut[lut_base],
 368                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 369                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 370                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 371         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 372                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 373
 374         /* Lock the LUT */
 375         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 376         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 377 }
 378
 379 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 380 /*
 381  * If we have changed the content of the flash by writing or erasing,
 382  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 383  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 384  * domain at the same time.
 385  */
 386 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 387 {
 388         struct fsl_qspi_regs *regs = priv->regs;
 389         u32 reg;
 390
 391         reg = qspi_read32(priv->flags, &regs->mcr);
 392         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 393         qspi_write32(priv->flags, &regs->mcr, reg);
 394
 395         /*
 396          * The minimum delay : 1 AHB + 2 SFCK clocks.
 397          * Delay 1 us is enough.
 398          */
 399         udelay(1);
 400
 401         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 402         qspi_write32(priv->flags, &regs->mcr, reg);
 403 }
 404
 405 /* Read out the data from the AHB buffer. */
 406 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 407 {
 408         struct fsl_qspi_regs *regs = priv->regs;
 409         u32 mcr_reg;
 410         void *rx_addr;
 411
 412         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 413
 414         qspi_write32(priv->flags, &regs->mcr,
 415                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 416                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 417
 418         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 419         /* Read out the data directly from the AHB buffer. */
 420         memcpy(rxbuf, rx_addr, len);
 421
 422         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 423 }
 424
 425 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 426 {
 427         u32 reg, reg2;
 428         struct fsl_qspi_regs *regs = priv->regs;
 429
 430         reg = qspi_read32(priv->flags, &regs->mcr);
 431         /* Disable the module */
 432         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 433
 434         /* Set the Sampling Register for DDR */
 435         reg2 = qspi_read32(priv->flags, &regs->smpr);
 436         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 437         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 438         qspi_write32(priv->flags, &regs->smpr, reg2);
 439
 440         /* Enable the module again (enable the DDR too) */
 441         reg |= QSPI_MCR_DDR_EN_MASK;
 442         /* Enable bit 29 for imx6sx */
 443         reg |= BIT(29);
 444
 445         qspi_write32(priv->flags, &regs->mcr, reg);
 446 }
 447
 448 /*
 449  * There are two different ways to read out the data from the flash:
 450  *  the "IP Command Read" and the "AHB Command Read".
 451  *
 452  * The IC guy suggests we use the "AHB Command Read" which is faster
 453  * then the "IP Command Read". (What's more is that there is a bug in
 454  * the "IP Command Read" in the Vybrid.)
 455  *
 456  * After we set up the registers for the "AHB Command Read", we can use
 457  * the memcpy to read the data directly. A "missed" access to the buffer
 458  * causes the controller to clear the buffer, and use the sequence pointed
 459  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 460  */
 461 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 462 {
 463         struct fsl_qspi_regs *regs = priv->regs;
 464
 465         /* AHB configuration for access buffer 0/1/2 .*/
 466         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 467         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 468         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 469         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 470                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 471
 472         /* We only use the buffer3 */
 473         qspi_write32(priv->flags, &regs->buf0ind, 0);
 474         qspi_write32(priv->flags, &regs->buf1ind, 0);
 475         qspi_write32(priv->flags, &regs->buf2ind, 0);
 476
 477         /*
 478          * Set the default lut sequence for AHB Read.
 479          * Parallel mode is disabled.
 480          */
 481         qspi_write32(priv->flags, &regs->bfgencr,
 482                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 483
 484         /*Enable DDR Mode*/
 485         qspi_enable_ddr_mode(priv);
 486 }
 487 #endif
 488
 489 #ifdef CONFIG_SPI_FLASH_BAR
 490 /* Bank register read/write, EAR register read/write */
 491 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 492 {
 493         struct fsl_qspi_regs *regs = priv->regs;
 494         u32 reg, mcr_reg, data, seqid;
 495
 496         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 497         qspi_write32(priv->flags, &regs->mcr,
 498                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 499                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 500         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 501
 502         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 503
 504         if (priv->cur_seqid == QSPI_CMD_BRRD)
 505                 seqid = SEQID_BRRD;
 506         else
 507                 seqid = SEQID_RDEAR;
 508
 509         qspi_write32(priv->flags, &regs->ipcr,
 510                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 511
 512         /* Wait previous command complete */
 513         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 514                 ;
 515
 516         while (1) {
 517                 WATCHDOG_RESET();
 518
 519                 reg = qspi_read32(priv->flags, &regs->rbsr);
 520                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 521                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 522                         data = qspi_endian_xchg(data);
 523                         memcpy(rxbuf, &data, len);
 524                         qspi_write32(priv->flags, &regs->mcr,
 525                                      qspi_read32(priv->flags, &regs->mcr) |
 526                                      QSPI_MCR_CLR_RXF_MASK);
 527                         break;
 528                 }
 529         }
 530
 531         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 532 }
 533 #endif
 534
 535 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 536 {
 537         struct fsl_qspi_regs *regs = priv->regs;
 538         u32 mcr_reg, rbsr_reg, data, size;
 539         int i;
 540
 541         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 542         qspi_write32(priv->flags, &regs->mcr,
 543                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 544                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 545         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 546
 547         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 548
 549         qspi_write32(priv->flags, &regs->ipcr,
 550                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 551         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 552                 ;
 553
 554         i = 0;
 555         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 556                 WATCHDOG_RESET();
 557
 558                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 559                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 560                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 561                         data = qspi_endian_xchg(data);
 562                         size = (len < 4) ? len : 4;
 563                         memcpy(rxbuf, &data, size);
 564                         len -= size;
 565                         rxbuf++;
 566                         i++;
 567                 }
 568         }
 569
 570         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 571 }
 572
 573 /* If not use AHB read, read data from ip interface */
 574 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 575 {
 576         struct fsl_qspi_regs *regs = priv->regs;
 577         u32 mcr_reg, data;
 578         int i, size;
 579         u32 to_or_from;
 580         u32 seqid;
 581
 582         if (priv->cur_seqid == QSPI_CMD_RDAR)
 583                 seqid = SEQID_RDAR;
 584         else
 585                 seqid = SEQID_FAST_READ;
 586
 587         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 588         qspi_write32(priv->flags, &regs->mcr,
 589                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 590                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 591         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 592
 593         to_or_from = priv->sf_addr + priv->cur_amba_base;
 594
 595         while (len > 0) {
 596                 WATCHDOG_RESET();
 597
 598                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 599
 600                 size = (len > RX_BUFFER_SIZE) ?
 601                         RX_BUFFER_SIZE : len;
 602
 603                 qspi_write32(priv->flags, &regs->ipcr,
 604                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 605                              size);
 606                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 607                         ;
 608
 609                 to_or_from += size;
 610                 len -= size;
 611
 612                 i = 0;
 613                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 614                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 615                         data = qspi_endian_xchg(data);
 616                         if (size < 4)
 617                                 memcpy(rxbuf, &data, size);
 618                         else
 619                                 memcpy(rxbuf, &data, 4);
 620                         rxbuf++;
 621                         size -= 4;
 622                         i++;
 623                 }
 624                 qspi_write32(priv->flags, &regs->mcr,
 625                              qspi_read32(priv->flags, &regs->mcr) |
 626                              QSPI_MCR_CLR_RXF_MASK);
 627         }
 628
 629         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 630 }
 631
 632 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 633 {
 634         struct fsl_qspi_regs *regs = priv->regs;
 635         u32 mcr_reg, data, reg, status_reg, seqid;
 636         int i, size, tx_size;
 637         u32 to_or_from = 0;
 638
 639         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 640         qspi_write32(priv->flags, &regs->mcr,
 641                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 642                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 643         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 644
 645         status_reg = 0;
 646         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 647                 WATCHDOG_RESET();
 648
 649                 qspi_write32(priv->flags, &regs->ipcr,
 650                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 651                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 652                         ;
 653
 654                 qspi_write32(priv->flags, &regs->ipcr,
 655                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 656                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 657                         ;
 658
 659                 reg = qspi_read32(priv->flags, &regs->rbsr);
 660                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 661                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 662                         status_reg = qspi_endian_xchg(status_reg);
 663                 }
 664                 qspi_write32(priv->flags, &regs->mcr,
 665                              qspi_read32(priv->flags, &regs->mcr) |
 666                              QSPI_MCR_CLR_RXF_MASK);
 667         }
 668
 669         /* Default is page programming */
 670         seqid = SEQID_PP;
 671         if (priv->cur_seqid == QSPI_CMD_WRAR)
 672                 seqid = SEQID_WRAR;
 673 #ifdef CONFIG_SPI_FLASH_BAR
 674         if (priv->cur_seqid == QSPI_CMD_BRWR)
 675                 seqid = SEQID_BRWR;
 676         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 677                 seqid = SEQID_WREAR;
 678 #endif
 679
 680         to_or_from = priv->sf_addr + priv->cur_amba_base;
 681
 682         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 683
 684         tx_size = (len > TX_BUFFER_SIZE) ?
 685                 TX_BUFFER_SIZE : len;
 686
 687         size = tx_size / 16;
 688         /*
 689          * There must be atleast 128bit data
 690          * available in TX FIFO for any pop operation
 691          */
 692         if (tx_size % 16)
 693                 size++;
 694         for (i = 0; i < size * 4; i++) {
 695                 memcpy(&data, txbuf, 4);
 696                 data = qspi_endian_xchg(data);
 697                 qspi_write32(priv->flags, &regs->tbdr, data);
 698                 txbuf += 4;
 699         }
 700
 701         qspi_write32(priv->flags, &regs->ipcr,
 702                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 703         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 704                 ;
 705
 706         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 707 }
 708
 709 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 710 {
 711         struct fsl_qspi_regs *regs = priv->regs;
 712         u32 mcr_reg, reg, data;
 713
 714         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 715         qspi_write32(priv->flags, &regs->mcr,
 716                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 717                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 718         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 719
 720         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 721
 722         qspi_write32(priv->flags, &regs->ipcr,
 723                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 724         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 725                 ;
 726
 727         while (1) {
 728                 WATCHDOG_RESET();
 729
 730                 reg = qspi_read32(priv->flags, &regs->rbsr);
 731                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 732                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 733                         data = qspi_endian_xchg(data);
 734                         memcpy(rxbuf, &data, len);
 735                         qspi_write32(priv->flags, &regs->mcr,
 736                                      qspi_read32(priv->flags, &regs->mcr) |
 737                                      QSPI_MCR_CLR_RXF_MASK);
 738                         break;
 739                 }
 740         }
 741
 742         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 743 }
 744
 745 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 746 {
 747         struct fsl_qspi_regs *regs = priv->regs;
 748         u32 mcr_reg;
 749         u32 to_or_from = 0;
 750
 751         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 752         qspi_write32(priv->flags, &regs->mcr,
 753                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 754                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 755         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 756
 757         to_or_from = priv->sf_addr + priv->cur_amba_base;
 758         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 759
 760         qspi_write32(priv->flags, &regs->ipcr,
 761                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 762         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 763                 ;
 764
 765         if (priv->cur_seqid == QSPI_CMD_SE) {
 766                 qspi_write32(priv->flags, &regs->ipcr,
 767                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 768         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 769                 qspi_write32(priv->flags, &regs->ipcr,
 770                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 771         }
 772         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 773                 ;
 774
 775         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 776 }
 777
 778 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 779                 const void *dout, void *din, unsigned long flags)
 780 {
 781         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 782         static u32 wr_sfaddr;
 783         u32 txbuf;
 784
 785         WATCHDOG_RESET();
 786
 787         if (dout) {
 788                 if (flags & SPI_XFER_BEGIN) {
 789                         priv->cur_seqid = *(u8 *)dout;
 790                         memcpy(&txbuf, dout, 4);
 791                 }
 792
 793                 if (flags == SPI_XFER_END) {
 794                         priv->sf_addr = wr_sfaddr;
 795                         qspi_op_write(priv, (u8 *)dout, bytes);
 796                         return 0;
 797                 }
 798
 799                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 800                     priv->cur_seqid == QSPI_CMD_RDAR) {
 801                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 802                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 803                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 804                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 805                         qspi_op_erase(priv);
 806                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 807                            priv->cur_seqid == QSPI_CMD_WRAR) {
 808                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 809                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 810                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 811 #ifdef CONFIG_SPI_FLASH_BAR
 812                         wr_sfaddr = 0;
 813 #endif
 814                 }
 815         }
 816
 817         if (din) {
 818                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 819 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 820                         qspi_ahb_read(priv, din, bytes);
 821 #else
 822                         qspi_op_read(priv, din, bytes);
 823 #endif
 824                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 825                         qspi_op_read(priv, din, bytes);
 826                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 827                         qspi_op_rdid(priv, din, bytes);
 828                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 829                         qspi_op_rdsr(priv, din, bytes);
 830 #ifdef CONFIG_SPI_FLASH_BAR
 831                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 832                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 833                         priv->sf_addr = 0;
 834                         qspi_op_rdbank(priv, din, bytes);
 835                 }
 836 #endif
 837         }
 838
 839 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 840         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 841             (priv->cur_seqid == QSPI_CMD_PP) ||
 842             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 843             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 844             (priv->cur_seqid == QSPI_CMD_BRWR))
 845                 qspi_ahb_invalid(priv);
 846 #endif
 847
 848         return 0;
 849 }
 850
 851 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 852 {
 853         u32 mcr_val;
 854
 855         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 856         if (disable)
 857                 mcr_val |= QSPI_MCR_MDIS_MASK;
 858         else
 859                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 860         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 861 }
 862
 863 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 864 {
 865         u32 smpr_val;
 866
 867         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 868         smpr_val &= ~clear_bits;
 869         smpr_val |= set_bits;
 870         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 871 }
 872 #ifndef CONFIG_DM_SPI
 873 static unsigned long spi_bases[] = {
 874         QSPI0_BASE_ADDR,
 875 #ifdef CONFIG_MX6SX
 876         QSPI1_BASE_ADDR,
 877 #endif
 878 };
 879
 880 static unsigned long amba_bases[] = {
 881         QSPI0_AMBA_BASE,
 882 #ifdef CONFIG_MX6SX
 883         QSPI1_AMBA_BASE,
 884 #endif
 885 };
 886
 887 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
 888 {
 889         return container_of(slave, struct fsl_qspi, slave);
 890 }
 891
 892 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 893                 unsigned int max_hz, unsigned int mode)
 894 {
 895         u32 mcr_val;
 896         struct fsl_qspi *qspi;
 897         struct fsl_qspi_regs *regs;
 898         u32 total_size;
 899
 900         if (bus >= ARRAY_SIZE(spi_bases))
 901                 return NULL;
 902
 903         if (cs >= FSL_QSPI_FLASH_NUM)
 904                 return NULL;
 905
 906         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
 907         if (!qspi)
 908                 return NULL;
 909
 910 #ifdef CONFIG_SYS_FSL_QSPI_BE
 911         qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 912 #endif
 913
 914         regs = (struct fsl_qspi_regs *)spi_bases[bus];
 915         qspi->priv.regs = regs;
 916         /*
 917          * According cs, use different amba_base to choose the
 918          * corresponding flash devices.
 919          *
 920          * If not, only one flash device is used even if passing
 921          * different cs using `sf probe`
 922          */
 923         qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 924
 925         qspi->slave.max_write_size = TX_BUFFER_SIZE;
 926
 927         mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
 928
 929         /* Set endianness to LE for i.mx */
 930         if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
 931                 mcr_val = QSPI_MCR_END_CFD_LE;
 932
 933         qspi_write32(qspi->priv.flags, &regs->mcr,
 934                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 935                      (mcr_val & QSPI_MCR_END_CFD_MASK));
 936
 937         qspi_cfg_smpr(&qspi->priv,
 938                       ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 939                       QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 940
 941         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 942         /*
 943          * Any read access to non-implemented addresses will provide
 944          * undefined results.
 945          *
 946          * In case single die flash devices, TOP_ADDR_MEMA2 and
 947          * TOP_ADDR_MEMB2 should be initialized/programmed to
 948          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 949          * setting the size of these devices to 0.  This would ensure
 950          * that the complete memory map is assigned to only one flash device.
 951          */
 952         qspi_write32(qspi->priv.flags, &regs->sfa1ad,
 953                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 954         qspi_write32(qspi->priv.flags, &regs->sfa2ad,
 955                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 956         qspi_write32(qspi->priv.flags, &regs->sfb1ad,
 957                      total_size | amba_bases[bus]);
 958         qspi_write32(qspi->priv.flags, &regs->sfb2ad,
 959                      total_size | amba_bases[bus]);
 960
 961         qspi_set_lut(&qspi->priv);
 962
 963 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 964         qspi_init_ahb_read(&qspi->priv);
 965 #endif
 966
 967         qspi_module_disable(&qspi->priv, 0);
 968
 969         return &qspi->slave;
 970 }
 971
 972 void spi_free_slave(struct spi_slave *slave)
 973 {
 974         struct fsl_qspi *qspi = to_qspi_spi(slave);
 975
 976         free(qspi);
 977 }
 978
 979 int spi_claim_bus(struct spi_slave *slave)
 980 {
 981         return 0;
 982 }
 983
 984 void spi_release_bus(struct spi_slave *slave)
 985 {
 986         /* Nothing to do */
 987 }
 988
 989 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 990                 const void *dout, void *din, unsigned long flags)
 991 {
 992         struct fsl_qspi *qspi = to_qspi_spi(slave);
 993
 994         return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
 995 }
 996
 997 void spi_init(void)
 998 {
 999         /* Nothing to do */
1000 }
1001 #else
1002 static int fsl_qspi_child_pre_probe(struct udevice *dev)
1003 {
1004         struct spi_slave *slave = dev_get_parent_priv(dev);
1005
1006         slave->max_write_size = TX_BUFFER_SIZE;
1007
1008         return 0;
1009 }
1010
1011 static int fsl_qspi_probe(struct udevice *bus)
1012 {
1013         u32 mcr_val;
1014         u32 amba_size_per_chip;
1015         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
1016         struct fsl_qspi_priv *priv = dev_get_priv(bus);
1017         struct dm_spi_bus *dm_spi_bus;
1018         int i, ret;
1019
1020         dm_spi_bus = bus->uclass_priv;
1021
1022         dm_spi_bus->max_hz = plat->speed_hz;
1023
1024         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
1025         priv->flags = plat->flags;
1026
1027         priv->speed_hz = plat->speed_hz;
1028         /*
1029          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
1030          * AMBA memory zone should be located on the 0~4GB space
1031          * even on a 64bits cpu.
1032          */
1033         priv->amba_base[0] = (u32)plat->amba_base;
1034         priv->amba_total_size = (u32)plat->amba_total_size;
1035         priv->flash_num = plat->flash_num;
1036         priv->num_chipselect = plat->num_chipselect;
1037
1038         /* make sure controller is not busy anywhere */
1039         ret = is_controller_busy(priv);
1040
1041         if (ret) {
1042                 debug("ERROR : The controller is busy\n");
1043                 return ret;
1044         }
1045
1046         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
1047
1048         /* Set endianness to LE for i.mx */
1049         if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
1050                 mcr_val = QSPI_MCR_END_CFD_LE;
1051
1052         qspi_write32(priv->flags, &priv->regs->mcr,
1053                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
1054                      (mcr_val & QSPI_MCR_END_CFD_MASK));
1055
1056         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1057                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1058
1059         /*
1060          * Assign AMBA memory zone for every chipselect
1061          * QuadSPI has two channels, every channel has two chipselects.
1062          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1063          * into two parts and assign to every channel. This indicate that every
1064          * channel only has one valid chipselect.
1065          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1066          * into four parts and assign to every chipselect.
1067          * Every channel will has two valid chipselects.
1068          */
1069         amba_size_per_chip = priv->amba_total_size >>
1070                              (priv->num_chipselect >> 1);
1071         for (i = 1 ; i < priv->num_chipselect ; i++)
1072                 priv->amba_base[i] =
1073                         amba_size_per_chip + priv->amba_base[i - 1];
1074
1075         /*
1076          * Any read access to non-implemented addresses will provide
1077          * undefined results.
1078          *
1079          * In case single die flash devices, TOP_ADDR_MEMA2 and
1080          * TOP_ADDR_MEMB2 should be initialized/programmed to
1081          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1082          * setting the size of these devices to 0.  This would ensure
1083          * that the complete memory map is assigned to only one flash device.
1084          */
1085         qspi_write32(priv->flags, &priv->regs->sfa1ad,
1086                      priv->amba_base[0] + amba_size_per_chip);
1087         switch (priv->num_chipselect) {
1088         case 1:
1089                 break;
1090         case 2:
1091                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1092                              priv->amba_base[1]);
1093                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1094                              priv->amba_base[1] + amba_size_per_chip);
1095                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1096                              priv->amba_base[1] + amba_size_per_chip);
1097                 break;
1098         case 4:
1099                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1100                              priv->amba_base[2]);
1101                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1102                              priv->amba_base[3]);
1103                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1104                              priv->amba_base[3] + amba_size_per_chip);
1105                 break;
1106         default:
1107                 debug("Error: Unsupported chipselect number %u!\n",
1108                       priv->num_chipselect);
1109                 qspi_module_disable(priv, 1);
1110                 return -EINVAL;
1111         }
1112
1113         qspi_set_lut(priv);
1114
1115 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1116         qspi_init_ahb_read(priv);
1117 #endif
1118
1119         qspi_module_disable(priv, 0);
1120
1121         return 0;
1122 }
1123
1124 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1125 {
1126         struct fdt_resource res_regs, res_mem;
1127         struct fsl_qspi_platdata *plat = bus->platdata;
1128         const void *blob = gd->fdt_blob;
1129         int node = dev_of_offset(bus);
1130         int ret, flash_num = 0, subnode;
1131
1132         if (fdtdec_get_bool(blob, node, "big-endian"))
1133                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1134
1135         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1136                                      "QuadSPI", &res_regs);
1137         if (ret) {
1138                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1139                 return -ENOMEM;
1140         }
1141         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1142                                      "QuadSPI-memory", &res_mem);
1143         if (ret) {
1144                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1145                 return -ENOMEM;
1146         }
1147
1148         /* Count flash numbers */
1149         fdt_for_each_subnode(subnode, blob, node)
1150                 ++flash_num;
1151
1152         if (flash_num == 0) {
1153                 debug("Error: Missing flashes!\n");
1154                 return -ENODEV;
1155         }
1156
1157         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1158                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1159         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1160                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1161
1162         plat->reg_base = res_regs.start;
1163         plat->amba_base = res_mem.start;
1164         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1165         plat->flash_num = flash_num;
1166
1167         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1168               __func__,
1169               (u64)plat->reg_base,
1170               (u64)plat->amba_base,
1171               (u64)plat->amba_total_size,
1172               plat->speed_hz,
1173               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1174               );
1175
1176         return 0;
1177 }
1178
1179 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1180                 const void *dout, void *din, unsigned long flags)
1181 {
1182         struct fsl_qspi_priv *priv;
1183         struct udevice *bus;
1184
1185         bus = dev->parent;
1186         priv = dev_get_priv(bus);
1187
1188         return qspi_xfer(priv, bitlen, dout, din, flags);
1189 }
1190
1191 static int fsl_qspi_claim_bus(struct udevice *dev)
1192 {
1193         struct fsl_qspi_priv *priv;
1194         struct udevice *bus;
1195         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1196         int ret;
1197
1198         bus = dev->parent;
1199         priv = dev_get_priv(bus);
1200
1201         /* make sure controller is not busy anywhere */
1202         ret = is_controller_busy(priv);
1203
1204         if (ret) {
1205                 debug("ERROR : The controller is busy\n");
1206                 return ret;
1207         }
1208
1209         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1210
1211         qspi_module_disable(priv, 0);
1212
1213         return 0;
1214 }
1215
1216 static int fsl_qspi_release_bus(struct udevice *dev)
1217 {
1218         struct fsl_qspi_priv *priv;
1219         struct udevice *bus;
1220
1221         bus = dev->parent;
1222         priv = dev_get_priv(bus);
1223
1224         qspi_module_disable(priv, 1);
1225
1226         return 0;
1227 }
1228
1229 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1230 {
1231         /* Nothing to do */
1232         return 0;
1233 }
1234
1235 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1236 {
1237         /* Nothing to do */
1238         return 0;
1239 }
1240
1241 static const struct dm_spi_ops fsl_qspi_ops = {
1242         .claim_bus      = fsl_qspi_claim_bus,
1243         .release_bus    = fsl_qspi_release_bus,
1244         .xfer           = fsl_qspi_xfer,
1245         .set_speed      = fsl_qspi_set_speed,
1246         .set_mode       = fsl_qspi_set_mode,
1247 };
1248
1249 static const struct udevice_id fsl_qspi_ids[] = {
1250         { .compatible = "fsl,vf610-qspi" },
1251         { .compatible = "fsl,imx6sx-qspi" },
1252         { .compatible = "fsl,imx6ul-qspi" },
1253         { .compatible = "fsl,imx7d-qspi" },
1254         { }
1255 };
1256
1257 U_BOOT_DRIVER(fsl_qspi) = {
1258         .name   = "fsl_qspi",
1259         .id     = UCLASS_SPI,
1260         .of_match = fsl_qspi_ids,
1261         .ops    = &fsl_qspi_ops,
1262         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1263         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1264         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1265         .probe  = fsl_qspi_probe,
1266         .child_pre_probe = fsl_qspi_child_pre_probe,
1267 };
1268 #endif