1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * Chao Fu (B44548@freescale.com)
9 * Haikun Wang (B53464@freescale.com)
12 #include <asm/global_data.h>
13 #include <linux/math64.h>
24 #include <asm/arch/clock.h>
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
30 /* linux/include/time.h */
31 #define NSEC_PER_SEC 1000000000L
33 DECLARE_GLOBAL_DATA_PTR;
35 /* fsl_dspi_plat flags */
36 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
39 #define DSPI_IDLE_VAL 0x0
41 /* max chipselect signals number */
42 #define FSL_DSPI_MAX_CHIPSELECT 6
44 /* default SCK frequency, unit: HZ */
45 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
47 /* tx/rx data wait timeout value, unit: us */
48 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
50 /* CTAR register pre-configure value */
51 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
52 DSPI_CTAR_PCSSCK_1CLK | \
55 DSPI_CTAR_CSSCK(0) | \
59 /* CTAR register pre-configure mask */
60 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
61 DSPI_CTAR_PCSSCK(3) | \
64 DSPI_CTAR_CSSCK(15) | \
69 * struct fsl_dspi_plat - platform data for Freescale DSPI
71 * @flags: Flags for DSPI DSPI_FLAG_...
72 * @speed_hz: Default SCK frequency
73 * @num_chipselect: Number of DSPI chipselect signals
74 * @regs_addr: Base address of DSPI registers
76 struct fsl_dspi_plat {
84 * struct fsl_dspi_priv - private data for Freescale DSPI
86 * @flags: Flags for DSPI DSPI_FLAG_...
87 * @mode: SPI mode to use for slave device (see SPI mode flags)
88 * @mcr_val: MCR register configure value
89 * @bus_clk: DSPI input clk frequency
90 * @speed_hz: Default SCK frequency
91 * @charbit: How many bits in every transfer
92 * @num_chipselect: Number of DSPI chipselect signals
93 * @ctar_val: CTAR register configure value of per chipselect slave device
94 * @regs: Point to DSPI register structure for I/O access
96 struct fsl_dspi_priv {
104 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
108 __weak void cpu_dspi_port_conf(void)
112 __weak int cpu_dspi_claim_bus(uint bus, uint cs)
117 __weak void cpu_dspi_release_bus(uint bus, uint cs)
121 static uint dspi_read32(uint flags, uint *addr)
123 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
124 in_be32(addr) : in_le32(addr);
127 static void dspi_write32(uint flags, uint *addr, uint val)
129 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
130 out_be32(addr, val) : out_le32(addr, val);
133 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
137 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
140 mcr_val |= DSPI_MCR_HALT;
142 mcr_val &= ~DSPI_MCR_HALT;
144 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
147 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
149 /* halt DSPI module */
152 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
157 priv->mcr_val = cfg_val;
160 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
167 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
168 if (state & SPI_CS_HIGH)
169 /* CSx inactive state is low */
170 mcr_val &= ~DSPI_MCR_PCSIS(cs);
172 /* CSx inactive state is high */
173 mcr_val |= DSPI_MCR_PCSIS(cs);
174 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
179 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
184 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
186 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
187 bus_setup |= priv->ctar_val[cs];
188 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
191 bus_setup |= DSPI_CTAR_CPOL;
193 bus_setup |= DSPI_CTAR_CPHA;
194 if (mode & SPI_LSB_FIRST)
195 bus_setup |= DSPI_CTAR_LSBFE;
197 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
200 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
201 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
206 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
211 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
212 /* flush RX and TX FIFO */
213 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
214 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
218 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
220 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
222 /* wait for empty entries in TXFIFO or timeout */
223 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
228 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
230 debug("dspi_tx: waiting timeout!\n");
233 static u16 dspi_rx(struct fsl_dspi_priv *priv)
235 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
237 /* wait for valid entries in RXFIFO or timeout */
238 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
243 return (u16)DSPI_RFR_RXDATA(
244 dspi_read32(priv->flags, &priv->regs->rfr));
246 debug("dspi_rx: waiting timeout!\n");
251 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
252 const void *dout, void *din, unsigned long flags)
254 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
255 u8 *spi_rd = NULL, *spi_wr = NULL;
257 uint len = bitlen >> 3;
259 if (priv->charbit == 16) {
261 spi_wr16 = (u16 *)dout;
262 spi_rd16 = (u16 *)din;
268 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
269 ctrl |= DSPI_TFR_CONT;
271 ctrl = ctrl & DSPI_TFR_CONT;
272 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
275 int tmp_len = len - 1;
277 if ((dout != NULL) && (din != NULL)) {
278 if (priv->charbit == 16) {
279 dspi_tx(priv, ctrl, *spi_wr16++);
280 *spi_rd16++ = dspi_rx(priv);
283 dspi_tx(priv, ctrl, *spi_wr++);
284 *spi_rd++ = dspi_rx(priv);
288 else if (dout != NULL) {
289 if (priv->charbit == 16)
290 dspi_tx(priv, ctrl, *spi_wr16++);
292 dspi_tx(priv, ctrl, *spi_wr++);
296 else if (din != NULL) {
297 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
298 if (priv->charbit == 16)
299 *spi_rd16++ = dspi_rx(priv);
301 *spi_rd++ = dspi_rx(priv);
305 len = 1; /* remaining byte */
308 if ((flags & SPI_XFER_END) == SPI_XFER_END)
309 ctrl &= ~DSPI_TFR_CONT;
312 if ((dout != NULL) && (din != NULL)) {
313 if (priv->charbit == 16) {
314 dspi_tx(priv, ctrl, *spi_wr16++);
315 *spi_rd16++ = dspi_rx(priv);
318 dspi_tx(priv, ctrl, *spi_wr++);
319 *spi_rd++ = dspi_rx(priv);
323 else if (dout != NULL) {
324 if (priv->charbit == 16)
325 dspi_tx(priv, ctrl, *spi_wr16);
327 dspi_tx(priv, ctrl, *spi_wr);
331 else if (din != NULL) {
332 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
333 if (priv->charbit == 16)
334 *spi_rd16 = dspi_rx(priv);
336 *spi_rd = dspi_rx(priv);
340 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
348 * Calculate the divide value between input clk frequency and expected SCK frequency
349 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
350 * Dbr: use default value 0
352 * @pbr: return Baud Rate Prescaler value
353 * @br: return Baud Rate Scaler value
354 * @speed_hz: expected SCK frequency
355 * @clkrate: input clk frequency
357 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
358 int speed_hz, uint clkrate)
360 /* Valid baud rate pre-scaler values */
361 int pbr_tbl[4] = {2, 3, 5, 7};
362 int brs[16] = {2, 4, 6, 8,
364 256, 512, 1024, 2048,
365 4096, 8192, 16384, 32768};
366 int temp, i = 0, j = 0;
368 temp = clkrate / speed_hz;
370 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
371 for (j = 0; j < ARRAY_SIZE(brs); j++) {
372 if (pbr_tbl[i] * brs[j] >= temp) {
379 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
380 debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
382 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
383 *br = ARRAY_SIZE(brs) - 1;
387 static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
388 unsigned long clkrate)
390 int scale_needed, scale, minscale = INT_MAX;
391 int pscale_tbl[4] = {1, 3, 5, 7};
395 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
400 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
401 for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
402 scale = pscale_tbl[i] * (2 << j);
403 if (scale >= scale_needed) {
404 if (scale < minscale) {
413 if (minscale == INT_MAX) {
414 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
416 *psc = ARRAY_SIZE(pscale_tbl) - 1;
417 *sc = DSPI_CTAR_SCALE_BITS;
421 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
425 int best_i, best_j, bus_clk;
427 bus_clk = priv->bus_clk;
429 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
432 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
433 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
435 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
437 speed = priv->speed_hz;
438 debug("DSPI set_speed use default SCK rate %u.\n", speed);
439 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
442 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
443 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
445 priv->speed_hz = speed;
450 static int fsl_dspi_child_pre_probe(struct udevice *dev)
452 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
453 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
454 u32 cs_sck_delay = 0, sck_cs_delay = 0;
455 unsigned char pcssck = 0, cssck = 0;
456 unsigned char pasc = 0, asc = 0;
458 if (slave_plat->cs >= priv->num_chipselect) {
459 debug("DSPI invalid chipselect number %d(max %d)!\n",
460 slave_plat->cs, priv->num_chipselect - 1);
464 ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
466 ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
469 /* Set PCS to SCK delay scale values */
470 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
472 /* Set After SCK delay scale values */
473 ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
475 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
476 DSPI_CTAR_PCSSCK(pcssck) |
477 DSPI_CTAR_PASC(pasc);
479 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
480 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
485 static int fsl_dspi_probe(struct udevice *bus)
487 struct fsl_dspi_plat *plat = dev_get_plat(bus);
488 struct fsl_dspi_priv *priv = dev_get_priv(bus);
489 struct dm_spi_bus *dm_spi_bus;
492 dm_spi_bus = dev_get_uclass_priv(bus);
494 /* cpu speical pin muxing configure */
495 cpu_dspi_port_conf();
497 /* get input clk frequency */
498 priv->regs = (struct dspi *)plat->regs_addr;
499 priv->flags = plat->flags;
501 priv->bus_clk = gd->bus_clk;
503 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
505 priv->num_chipselect = plat->num_chipselect;
506 priv->speed_hz = plat->speed_hz;
507 /* frame data length in bits, default 8bits */
510 dm_spi_bus->max_hz = plat->speed_hz;
512 /* default: all CS signals inactive state is high */
513 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
514 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
515 fsl_dspi_init_mcr(priv, mcr_cfg_val);
517 debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
522 static int fsl_dspi_claim_bus(struct udevice *dev)
525 struct fsl_dspi_priv *priv;
526 struct udevice *bus = dev->parent;
527 struct dm_spi_slave_plat *slave_plat =
528 dev_get_parent_plat(dev);
530 priv = dev_get_priv(bus);
532 /* processor special preparation work */
533 cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);
535 /* configure transfer mode */
536 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
538 /* configure active state of CSX */
539 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
542 fsl_dspi_clr_fifo(priv);
544 /* check module TX and RX status */
545 sr_val = dspi_read32(priv->flags, &priv->regs->sr);
546 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
547 debug("DSPI RX/TX not ready!\n");
554 static int fsl_dspi_release_bus(struct udevice *dev)
556 struct udevice *bus = dev->parent;
557 struct fsl_dspi_priv *priv = dev_get_priv(bus);
558 struct dm_spi_slave_plat *slave_plat =
559 dev_get_parent_plat(dev);
564 /* processor special release work */
565 cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);
571 * This function doesn't do anything except help with debugging
573 static int fsl_dspi_bind(struct udevice *bus)
575 debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
579 static int fsl_dspi_of_to_plat(struct udevice *bus)
582 struct fsl_dspi_plat *plat = dev_get_plat(bus);
583 const void *blob = gd->fdt_blob;
584 int node = dev_of_offset(bus);
586 if (fdtdec_get_bool(blob, node, "big-endian"))
587 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
589 plat->num_chipselect = fdtdec_get_int(blob, node,
590 "spi-num-chipselects",
591 FSL_DSPI_MAX_CHIPSELECT);
593 addr = dev_read_addr(bus);
594 if (addr == FDT_ADDR_T_NONE) {
595 debug("DSPI: Can't get base address or size\n");
598 plat->regs_addr = addr;
600 plat->speed_hz = fdtdec_get_int(blob,
601 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
603 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
604 &plat->regs_addr, plat->speed_hz,
605 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
606 plat->num_chipselect);
611 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
612 const void *dout, void *din, unsigned long flags)
614 struct fsl_dspi_priv *priv;
615 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
619 priv = dev_get_priv(bus);
621 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
624 static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
626 struct fsl_dspi_priv *priv = dev_get_priv(bus);
628 return fsl_dspi_cfg_speed(priv, speed);
631 static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
633 struct fsl_dspi_priv *priv = dev_get_priv(bus);
635 debug("DSPI set_mode: mode 0x%x.\n", mode);
638 * We store some chipselect special configure value in priv->ctar_val,
639 * and we can't get the correct chipselect number here,
640 * so just store mode value.
641 * Do really configuration when claim_bus.
648 static const struct dm_spi_ops fsl_dspi_ops = {
649 .claim_bus = fsl_dspi_claim_bus,
650 .release_bus = fsl_dspi_release_bus,
651 .xfer = fsl_dspi_xfer,
652 .set_speed = fsl_dspi_set_speed,
653 .set_mode = fsl_dspi_set_mode,
656 static const struct udevice_id fsl_dspi_ids[] = {
657 { .compatible = "fsl,vf610-dspi" },
658 { .compatible = "fsl,ls1021a-v1.0-dspi" },
662 U_BOOT_DRIVER(fsl_dspi) = {
665 .of_match = fsl_dspi_ids,
666 .ops = &fsl_dspi_ops,
667 .of_to_plat = fsl_dspi_of_to_plat,
668 .plat_auto = sizeof(struct fsl_dspi_plat),
669 .priv_auto = sizeof(struct fsl_dspi_priv),
670 .probe = fsl_dspi_probe,
671 .child_pre_probe = fsl_dspi_child_pre_probe,
672 .bind = fsl_dspi_bind,