2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Padmavathi Venna <padma.v@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <asm/arch/clk.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/pinmux.h>
28 #include <asm/arch-exynos/spi.h>
31 /* Information about each SPI controller */
33 enum periph_id periph_id;
34 s32 frequency; /* Default clock frequency, -1 for none */
35 struct exynos_spi *regs;
36 int inited; /* 1 if this bus is ready for use */
39 /* A list of spi buses that we know about */
40 static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
42 struct exynos_spi_slave {
43 struct spi_slave slave;
44 struct exynos_spi *regs;
45 unsigned int freq; /* Default frequency */
47 enum periph_id periph_id; /* Peripheral ID for this device */
48 unsigned int fifo_size;
51 static struct spi_bus *spi_get_bus(unsigned dev_index)
53 if (dev_index < EXYNOS5_SPI_NUM_CONTROLLERS)
54 return &spi_bus[dev_index];
55 debug("%s: invalid bus %d", __func__, dev_index);
60 static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
62 return container_of(slave, struct exynos_spi_slave, slave);
66 * Setup the driver private data
68 * @param bus ID of the bus that the slave is attached to
69 * @param cs ID of the chip select connected to the slave
70 * @param max_hz Required spi frequency
71 * @param mode Required spi mode (clk polarity, clk phase and
73 * @return new device or NULL
75 struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
76 unsigned int max_hz, unsigned int mode)
78 struct exynos_spi_slave *spi_slave;
81 if (!spi_cs_is_valid(busnum, cs)) {
82 debug("%s: Invalid bus/chip select %d, %d\n", __func__,
87 spi_slave = malloc(sizeof(*spi_slave));
89 debug("%s: Could not allocate spi_slave\n", __func__);
93 bus = &spi_bus[busnum];
94 spi_slave->slave.bus = busnum;
95 spi_slave->slave.cs = cs;
96 spi_slave->regs = bus->regs;
97 spi_slave->mode = mode;
98 spi_slave->periph_id = bus->periph_id;
99 if (bus->periph_id == PERIPH_ID_SPI1 ||
100 bus->periph_id == PERIPH_ID_SPI2)
101 spi_slave->fifo_size = 64;
103 spi_slave->fifo_size = 256;
105 spi_slave->freq = bus->frequency;
107 spi_slave->freq = min(max_hz, spi_slave->freq);
109 return &spi_slave->slave;
113 * Free spi controller
115 * @param slave Pointer to spi_slave to which controller has to
118 void spi_free_slave(struct spi_slave *slave)
120 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
126 * Flush spi tx, rx fifos and reset the SPI controller
128 * @param slave Pointer to spi_slave to which controller has to
131 static void spi_flush_fifo(struct spi_slave *slave)
133 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
134 struct exynos_spi *regs = spi_slave->regs;
136 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
137 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
138 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
142 * Initialize the spi base registers, set the required clock frequency and
143 * initialize the gpios
145 * @param slave Pointer to spi_slave to which controller has to
147 * @return zero on success else a negative value
149 int spi_claim_bus(struct spi_slave *slave)
151 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
152 struct exynos_spi *regs = spi_slave->regs;
156 ret = set_spi_clk(spi_slave->periph_id,
159 debug("%s: Failed to setup spi clock\n", __func__);
163 exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
165 spi_flush_fifo(slave);
167 reg = readl(®s->ch_cfg);
168 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
170 if (spi_slave->mode & SPI_CPHA)
171 reg |= SPI_CH_CPHA_B;
173 if (spi_slave->mode & SPI_CPOL)
174 reg |= SPI_CH_CPOL_L;
176 writel(reg, ®s->ch_cfg);
177 writel(SPI_FB_DELAY_180, ®s->fb_clk);
183 * Reset the spi H/W and flush the tx and rx fifos
185 * @param slave Pointer to spi_slave to which controller has to
188 void spi_release_bus(struct spi_slave *slave)
190 spi_flush_fifo(slave);
193 static void spi_get_fifo_levels(struct exynos_spi *regs,
194 int *rx_lvl, int *tx_lvl)
196 uint32_t spi_sts = readl(®s->spi_sts);
198 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
199 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
203 * If there's something to transfer, do a software reset and set a
206 * @param regs SPI peripheral registers
207 * @param count Number of bytes to transfer
209 static void spi_request_bytes(struct exynos_spi *regs, int count)
211 assert(count && count < (1 << 16));
212 setbits_le32(®s->ch_cfg, SPI_CH_RST);
213 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
214 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
217 static void spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
218 void **dinp, void const **doutp)
220 struct exynos_spi *regs = spi_slave->regs;
222 const uchar *txp = *doutp;
224 uint out_bytes, in_bytes;
226 out_bytes = in_bytes = todo;
229 * If there's something to send, do a software reset and set a
232 spi_request_bytes(regs, todo);
235 * Bytes are transmitted/received in pairs. Wait to receive all the
236 * data because then transmission will be done as well.
241 /* Keep the fifos full/empty. */
242 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
243 if (tx_lvl < spi_slave->fifo_size && out_bytes) {
244 temp = txp ? *txp++ : 0xff;
245 writel(temp, ®s->tx_data);
248 if (rx_lvl > 0 && in_bytes) {
249 temp = readl(®s->rx_data);
260 * Transfer and receive data
262 * @param slave Pointer to spi_slave to which controller has to
264 * @param bitlen No of bits to tranfer or receive
265 * @param dout Pointer to transfer buffer
266 * @param din Pointer to receive buffer
267 * @param flags Flags for transfer begin and end
268 * @return zero on success else a negative value
270 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
271 void *din, unsigned long flags)
273 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
277 /* spi core configured to do 8 bit transfers */
279 debug("Non byte aligned SPI transfer.\n");
283 /* Start the transaction, if necessary. */
284 if ((flags & SPI_XFER_BEGIN))
285 spi_cs_activate(slave);
287 /* Exynos SPI limits each transfer to 65535 bytes */
288 bytelen = bitlen / 8;
289 for (upto = 0; upto < bytelen; upto += todo) {
290 todo = min(bytelen - upto, (1 << 16) - 1);
291 spi_rx_tx(spi_slave, todo, &din, &dout);
294 /* Stop the transaction, if necessary. */
295 if ((flags & SPI_XFER_END))
296 spi_cs_deactivate(slave);
302 * Validates the bus and chip select numbers
304 * @param bus ID of the bus that the slave is attached to
305 * @param cs ID of the chip select connected to the slave
306 * @return one on success else zero
308 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
310 return spi_get_bus(bus) && cs == 0;
314 * Activate the CS by driving it LOW
316 * @param slave Pointer to spi_slave to which controller has to
319 void spi_cs_activate(struct spi_slave *slave)
321 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
323 clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
324 debug("Activate CS, bus %d\n", spi_slave->slave.bus);
328 * Deactivate the CS by driving it HIGH
330 * @param slave Pointer to spi_slave to which controller has to
333 void spi_cs_deactivate(struct spi_slave *slave)
335 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
337 setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
338 debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
341 static inline struct exynos_spi *get_spi_base(int dev_index)
344 return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
346 return (struct exynos_spi *)samsung_get_base_spi_isp() +
350 /* Sadly there is no error return from this function */
356 for (i = 0; i < EXYNOS5_SPI_NUM_CONTROLLERS; i++) {
358 bus->regs = get_spi_base(i);
359 bus->periph_id = PERIPH_ID_SPI0 + i;
361 /* Although Exynos5 supports upto 50Mhz speed,
362 * we are setting it to 10Mhz for safe side
364 bus->frequency = 10000000;