1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Padmavathi Venna <padma.v@samsung.com>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/spi.h>
22 #include <linux/delay.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 struct exynos_spi_platdata {
27 enum periph_id periph_id;
28 s32 frequency; /* Default clock frequency, -1 for none */
29 struct exynos_spi *regs;
30 uint deactivate_delay_us; /* Delay to wait after deactivate */
33 struct exynos_spi_priv {
34 struct exynos_spi *regs;
35 unsigned int freq; /* Default frequency */
37 enum periph_id periph_id; /* Peripheral ID for this device */
38 unsigned int fifo_size;
40 ulong last_transaction_us; /* Time of last transaction end */
44 * Flush spi tx, rx fifos and reset the SPI controller
46 * @param regs Pointer to SPI registers
48 static void spi_flush_fifo(struct exynos_spi *regs)
50 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
51 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
52 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
55 static void spi_get_fifo_levels(struct exynos_spi *regs,
56 int *rx_lvl, int *tx_lvl)
58 uint32_t spi_sts = readl(®s->spi_sts);
60 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
61 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
65 * If there's something to transfer, do a software reset and set a
68 * @param regs SPI peripheral registers
69 * @param count Number of bytes to transfer
70 * @param step Number of bytes to transfer in each packet (1 or 4)
72 static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
74 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
76 /* For word address we need to swap bytes */
78 setbits_le32(®s->mode_cfg,
79 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
81 setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
82 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
83 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
85 /* Select byte access and clear the swap configuration */
86 clrbits_le32(®s->mode_cfg,
87 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
88 writel(0, ®s->swap_cfg);
91 assert(count && count < (1 << 16));
92 setbits_le32(®s->ch_cfg, SPI_CH_RST);
93 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
95 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
98 static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
99 void **dinp, void const **doutp, unsigned long flags)
101 struct exynos_spi *regs = priv->regs;
103 const uchar *txp = *doutp;
105 uint out_bytes, in_bytes;
107 unsigned start = get_timer(0);
111 out_bytes = in_bytes = todo;
113 stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
114 !(priv->mode & SPI_SLAVE);
117 * Try to transfer words if we can. This helps read performance at
118 * SPI clock speeds above about 20MHz.
121 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
122 !priv->skip_preamble)
126 * If there's something to send, do a software reset and set a
129 spi_request_bytes(regs, todo, step);
132 * Bytes are transmitted/received in pairs. Wait to receive all the
133 * data because then transmission will be done as well.
140 /* Keep the fifos full/empty. */
141 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
144 * Don't completely fill the txfifo, since we don't want our
145 * rxfifo to overflow, and it may already contain data.
147 while (tx_lvl < priv->fifo_size/2 && out_bytes) {
151 temp = *(uint32_t *)txp;
154 writel(temp, ®s->tx_data);
160 if (rx_lvl >= step) {
161 while (rx_lvl >= step) {
162 temp = readl(®s->rx_data);
163 if (priv->skip_preamble) {
164 if (temp == SPI_PREAMBLE_END_BYTE) {
165 priv->skip_preamble = 0;
169 if (rxp || stopping) {
171 *(uint32_t *)rxp = temp;
181 } else if (!toread) {
183 * We have run out of input data, but haven't read
184 * enough bytes after the preamble yet. Read some more,
185 * and make sure that we transmit dummy bytes too, to
189 out_bytes = in_bytes;
192 spi_request_bytes(regs, toread, step);
194 if (priv->skip_preamble && get_timer(start) > 100) {
195 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
196 in_bytes, out_bytes);
208 * Activate the CS by driving it LOW
210 * @param slave Pointer to spi_slave to which controller has to
213 static void spi_cs_activate(struct udevice *dev)
215 struct udevice *bus = dev->parent;
216 struct exynos_spi_platdata *pdata = dev_get_plat(bus);
217 struct exynos_spi_priv *priv = dev_get_priv(bus);
219 /* If it's too soon to do another transaction, wait */
220 if (pdata->deactivate_delay_us &&
221 priv->last_transaction_us) {
222 ulong delay_us; /* The delay completed so far */
223 delay_us = timer_get_us() - priv->last_transaction_us;
224 if (delay_us < pdata->deactivate_delay_us)
225 udelay(pdata->deactivate_delay_us - delay_us);
228 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
229 debug("Activate CS, bus '%s'\n", bus->name);
230 priv->skip_preamble = priv->mode & SPI_PREAMBLE;
234 * Deactivate the CS by driving it HIGH
236 * @param slave Pointer to spi_slave to which controller has to
239 static void spi_cs_deactivate(struct udevice *dev)
241 struct udevice *bus = dev->parent;
242 struct exynos_spi_platdata *pdata = dev_get_plat(bus);
243 struct exynos_spi_priv *priv = dev_get_priv(bus);
245 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
247 /* Remember time of this transaction so we can honour the bus delay */
248 if (pdata->deactivate_delay_us)
249 priv->last_transaction_us = timer_get_us();
251 debug("Deactivate CS, bus '%s'\n", bus->name);
254 static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
256 struct exynos_spi_platdata *plat = bus->plat;
257 const void *blob = gd->fdt_blob;
258 int node = dev_of_offset(bus);
260 plat->regs = dev_read_addr_ptr(bus);
261 plat->periph_id = pinmux_decode_periph_id(blob, node);
263 if (plat->periph_id == PERIPH_ID_NONE) {
264 debug("%s: Invalid peripheral ID %d\n", __func__,
266 return -FDT_ERR_NOTFOUND;
269 /* Use 500KHz as a suitable default */
270 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
272 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
273 "spi-deactivate-delay", 0);
274 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
275 __func__, plat->regs, plat->periph_id, plat->frequency,
276 plat->deactivate_delay_us);
281 static int exynos_spi_probe(struct udevice *bus)
283 struct exynos_spi_platdata *plat = dev_get_plat(bus);
284 struct exynos_spi_priv *priv = dev_get_priv(bus);
286 priv->regs = plat->regs;
287 if (plat->periph_id == PERIPH_ID_SPI1 ||
288 plat->periph_id == PERIPH_ID_SPI2)
289 priv->fifo_size = 64;
291 priv->fifo_size = 256;
293 priv->skip_preamble = 0;
294 priv->last_transaction_us = timer_get_us();
295 priv->freq = plat->frequency;
296 priv->periph_id = plat->periph_id;
301 static int exynos_spi_claim_bus(struct udevice *dev)
303 struct udevice *bus = dev->parent;
304 struct exynos_spi_priv *priv = dev_get_priv(bus);
306 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
307 spi_flush_fifo(priv->regs);
309 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
314 static int exynos_spi_release_bus(struct udevice *dev)
316 struct udevice *bus = dev->parent;
317 struct exynos_spi_priv *priv = dev_get_priv(bus);
319 spi_flush_fifo(priv->regs);
324 static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
325 const void *dout, void *din, unsigned long flags)
327 struct udevice *bus = dev->parent;
328 struct exynos_spi_priv *priv = dev_get_priv(bus);
333 /* spi core configured to do 8 bit transfers */
335 debug("Non byte aligned SPI transfer.\n");
339 /* Start the transaction, if necessary. */
340 if ((flags & SPI_XFER_BEGIN))
341 spi_cs_activate(dev);
344 * Exynos SPI limits each transfer to 65535 transfers. To keep
345 * things simple, allow a maximum of 65532 bytes. We could allow
346 * more in word mode, but the performance difference is small.
348 bytelen = bitlen / 8;
349 for (upto = 0; !ret && upto < bytelen; upto += todo) {
350 todo = min(bytelen - upto, (1 << 16) - 4);
351 ret = spi_rx_tx(priv, todo, &din, &dout, flags);
356 /* Stop the transaction, if necessary. */
357 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
358 spi_cs_deactivate(dev);
359 if (priv->skip_preamble) {
360 assert(!priv->skip_preamble);
361 debug("Failed to complete premable transaction\n");
369 static int exynos_spi_set_speed(struct udevice *bus, uint speed)
371 struct exynos_spi_platdata *plat = bus->plat;
372 struct exynos_spi_priv *priv = dev_get_priv(bus);
375 if (speed > plat->frequency)
376 speed = plat->frequency;
377 ret = set_spi_clk(priv->periph_id, speed);
381 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
386 static int exynos_spi_set_mode(struct udevice *bus, uint mode)
388 struct exynos_spi_priv *priv = dev_get_priv(bus);
391 reg = readl(&priv->regs->ch_cfg);
392 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
395 reg |= SPI_CH_CPHA_B;
398 reg |= SPI_CH_CPOL_L;
400 writel(reg, &priv->regs->ch_cfg);
402 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
407 static const struct dm_spi_ops exynos_spi_ops = {
408 .claim_bus = exynos_spi_claim_bus,
409 .release_bus = exynos_spi_release_bus,
410 .xfer = exynos_spi_xfer,
411 .set_speed = exynos_spi_set_speed,
412 .set_mode = exynos_spi_set_mode,
414 * cs_info is not needed, since we require all chip selects to be
415 * in the device tree explicitly
419 static const struct udevice_id exynos_spi_ids[] = {
420 { .compatible = "samsung,exynos-spi" },
424 U_BOOT_DRIVER(exynos_spi) = {
425 .name = "exynos_spi",
427 .of_match = exynos_spi_ids,
428 .ops = &exynos_spi_ops,
429 .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
430 .plat_auto = sizeof(struct exynos_spi_platdata),
431 .priv_auto = sizeof(struct exynos_spi_priv),
432 .probe = exynos_spi_probe,