1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Padmavathi Venna <padma.v@samsung.com>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/spi.h>
21 #include <asm/global_data.h>
23 #include <linux/delay.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 struct exynos_spi_plat {
28 enum periph_id periph_id;
29 s32 frequency; /* Default clock frequency, -1 for none */
30 struct exynos_spi *regs;
31 uint deactivate_delay_us; /* Delay to wait after deactivate */
34 struct exynos_spi_priv {
35 struct exynos_spi *regs;
36 unsigned int freq; /* Default frequency */
38 enum periph_id periph_id; /* Peripheral ID for this device */
39 unsigned int fifo_size;
41 ulong last_transaction_us; /* Time of last transaction end */
45 * Flush spi tx, rx fifos and reset the SPI controller
47 * @param regs Pointer to SPI registers
49 static void spi_flush_fifo(struct exynos_spi *regs)
51 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
52 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
53 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
56 static void spi_get_fifo_levels(struct exynos_spi *regs,
57 int *rx_lvl, int *tx_lvl)
59 uint32_t spi_sts = readl(®s->spi_sts);
61 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
62 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
66 * If there's something to transfer, do a software reset and set a
69 * @param regs SPI peripheral registers
70 * @param count Number of bytes to transfer
71 * @param step Number of bytes to transfer in each packet (1 or 4)
73 static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
75 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
77 /* For word address we need to swap bytes */
79 setbits_le32(®s->mode_cfg,
80 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
82 setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
83 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
84 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
86 /* Select byte access and clear the swap configuration */
87 clrbits_le32(®s->mode_cfg,
88 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
89 writel(0, ®s->swap_cfg);
92 assert(count && count < (1 << 16));
93 setbits_le32(®s->ch_cfg, SPI_CH_RST);
94 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
96 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
99 static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
100 void **dinp, void const **doutp, unsigned long flags)
102 struct exynos_spi *regs = priv->regs;
104 const uchar *txp = *doutp;
106 uint out_bytes, in_bytes;
108 unsigned start = get_timer(0);
112 out_bytes = in_bytes = todo;
114 stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
115 !(priv->mode & SPI_SLAVE);
118 * Try to transfer words if we can. This helps read performance at
119 * SPI clock speeds above about 20MHz.
122 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
123 !priv->skip_preamble)
127 * If there's something to send, do a software reset and set a
130 spi_request_bytes(regs, todo, step);
133 * Bytes are transmitted/received in pairs. Wait to receive all the
134 * data because then transmission will be done as well.
141 /* Keep the fifos full/empty. */
142 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
145 * Don't completely fill the txfifo, since we don't want our
146 * rxfifo to overflow, and it may already contain data.
148 while (tx_lvl < priv->fifo_size/2 && out_bytes) {
152 temp = *(uint32_t *)txp;
155 writel(temp, ®s->tx_data);
161 if (rx_lvl >= step) {
162 while (rx_lvl >= step) {
163 temp = readl(®s->rx_data);
164 if (priv->skip_preamble) {
165 if (temp == SPI_PREAMBLE_END_BYTE) {
166 priv->skip_preamble = 0;
170 if (rxp || stopping) {
172 *(uint32_t *)rxp = temp;
182 } else if (!toread) {
184 * We have run out of input data, but haven't read
185 * enough bytes after the preamble yet. Read some more,
186 * and make sure that we transmit dummy bytes too, to
190 out_bytes = in_bytes;
193 spi_request_bytes(regs, toread, step);
195 if (priv->skip_preamble && get_timer(start) > 100) {
196 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
197 in_bytes, out_bytes);
209 * Activate the CS by driving it LOW
211 * @param slave Pointer to spi_slave to which controller has to
214 static void spi_cs_activate(struct udevice *dev)
216 struct udevice *bus = dev->parent;
217 struct exynos_spi_plat *pdata = dev_get_plat(bus);
218 struct exynos_spi_priv *priv = dev_get_priv(bus);
220 /* If it's too soon to do another transaction, wait */
221 if (pdata->deactivate_delay_us &&
222 priv->last_transaction_us) {
223 ulong delay_us; /* The delay completed so far */
224 delay_us = timer_get_us() - priv->last_transaction_us;
225 if (delay_us < pdata->deactivate_delay_us)
226 udelay(pdata->deactivate_delay_us - delay_us);
229 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
230 debug("Activate CS, bus '%s'\n", bus->name);
231 priv->skip_preamble = priv->mode & SPI_PREAMBLE;
235 * Deactivate the CS by driving it HIGH
237 * @param slave Pointer to spi_slave to which controller has to
240 static void spi_cs_deactivate(struct udevice *dev)
242 struct udevice *bus = dev->parent;
243 struct exynos_spi_plat *pdata = dev_get_plat(bus);
244 struct exynos_spi_priv *priv = dev_get_priv(bus);
246 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
248 /* Remember time of this transaction so we can honour the bus delay */
249 if (pdata->deactivate_delay_us)
250 priv->last_transaction_us = timer_get_us();
252 debug("Deactivate CS, bus '%s'\n", bus->name);
255 static int exynos_spi_of_to_plat(struct udevice *bus)
257 struct exynos_spi_plat *plat = dev_get_plat(bus);
258 const void *blob = gd->fdt_blob;
259 int node = dev_of_offset(bus);
261 plat->regs = dev_read_addr_ptr(bus);
262 plat->periph_id = pinmux_decode_periph_id(blob, node);
264 if (plat->periph_id == PERIPH_ID_NONE) {
265 debug("%s: Invalid peripheral ID %d\n", __func__,
267 return -FDT_ERR_NOTFOUND;
270 /* Use 500KHz as a suitable default */
271 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
273 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
274 "spi-deactivate-delay", 0);
275 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
276 __func__, plat->regs, plat->periph_id, plat->frequency,
277 plat->deactivate_delay_us);
282 static int exynos_spi_probe(struct udevice *bus)
284 struct exynos_spi_plat *plat = dev_get_plat(bus);
285 struct exynos_spi_priv *priv = dev_get_priv(bus);
287 priv->regs = plat->regs;
288 if (plat->periph_id == PERIPH_ID_SPI1 ||
289 plat->periph_id == PERIPH_ID_SPI2)
290 priv->fifo_size = 64;
292 priv->fifo_size = 256;
294 priv->skip_preamble = 0;
295 priv->last_transaction_us = timer_get_us();
296 priv->freq = plat->frequency;
297 priv->periph_id = plat->periph_id;
302 static int exynos_spi_claim_bus(struct udevice *dev)
304 struct udevice *bus = dev->parent;
305 struct exynos_spi_priv *priv = dev_get_priv(bus);
307 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
308 spi_flush_fifo(priv->regs);
310 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
315 static int exynos_spi_release_bus(struct udevice *dev)
317 struct udevice *bus = dev->parent;
318 struct exynos_spi_priv *priv = dev_get_priv(bus);
320 spi_flush_fifo(priv->regs);
325 static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
326 const void *dout, void *din, unsigned long flags)
328 struct udevice *bus = dev->parent;
329 struct exynos_spi_priv *priv = dev_get_priv(bus);
334 /* spi core configured to do 8 bit transfers */
336 debug("Non byte aligned SPI transfer.\n");
340 /* Start the transaction, if necessary. */
341 if ((flags & SPI_XFER_BEGIN))
342 spi_cs_activate(dev);
345 * Exynos SPI limits each transfer to 65535 transfers. To keep
346 * things simple, allow a maximum of 65532 bytes. We could allow
347 * more in word mode, but the performance difference is small.
349 bytelen = bitlen / 8;
350 for (upto = 0; !ret && upto < bytelen; upto += todo) {
351 todo = min(bytelen - upto, (1 << 16) - 4);
352 ret = spi_rx_tx(priv, todo, &din, &dout, flags);
357 /* Stop the transaction, if necessary. */
358 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
359 spi_cs_deactivate(dev);
360 if (priv->skip_preamble) {
361 assert(!priv->skip_preamble);
362 debug("Failed to complete premable transaction\n");
370 static int exynos_spi_set_speed(struct udevice *bus, uint speed)
372 struct exynos_spi_plat *plat = dev_get_plat(bus);
373 struct exynos_spi_priv *priv = dev_get_priv(bus);
376 if (speed > plat->frequency)
377 speed = plat->frequency;
378 ret = set_spi_clk(priv->periph_id, speed);
382 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
387 static int exynos_spi_set_mode(struct udevice *bus, uint mode)
389 struct exynos_spi_priv *priv = dev_get_priv(bus);
392 reg = readl(&priv->regs->ch_cfg);
393 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
396 reg |= SPI_CH_CPHA_B;
399 reg |= SPI_CH_CPOL_L;
401 writel(reg, &priv->regs->ch_cfg);
403 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
408 static const struct dm_spi_ops exynos_spi_ops = {
409 .claim_bus = exynos_spi_claim_bus,
410 .release_bus = exynos_spi_release_bus,
411 .xfer = exynos_spi_xfer,
412 .set_speed = exynos_spi_set_speed,
413 .set_mode = exynos_spi_set_mode,
415 * cs_info is not needed, since we require all chip selects to be
416 * in the device tree explicitly
420 static const struct udevice_id exynos_spi_ids[] = {
421 { .compatible = "samsung,exynos-spi" },
425 U_BOOT_DRIVER(exynos_spi) = {
426 .name = "exynos_spi",
428 .of_match = exynos_spi_ids,
429 .ops = &exynos_spi_ops,
430 .of_to_plat = exynos_spi_of_to_plat,
431 .plat_auto = sizeof(struct exynos_spi_plat),
432 .priv_auto = sizeof(struct exynos_spi_priv),
433 .probe = exynos_spi_probe,