2 * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/highmem.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
26 #include <linux/spi/dw_spi.h>
27 #include <linux/spi/spi.h>
29 #ifdef CONFIG_DEBUG_FS
30 #include <linux/debugfs.h>
33 #define START_STATE ((void *)0)
34 #define RUNNING_STATE ((void *)1)
35 #define DONE_STATE ((void *)2)
36 #define ERROR_STATE ((void *)-1)
38 #define QUEUE_RUNNING 0
39 #define QUEUE_STOPPED 1
41 #define MRST_SPI_DEASSERT 0
42 #define MRST_SPI_ASSERT 1
44 /* Slave spi_dev related */
47 u8 cs; /* chip select pin */
48 u8 n_bytes; /* current is a 1/2/4 byte op */
49 u8 tmode; /* TR/TO/RO/EEPROM */
50 u8 type; /* SPI/SSP/MicroWire */
52 u8 poll_mode; /* 1 means use poll mode */
59 u16 clk_div; /* baud rate divider */
60 u32 speed_hz; /* baud rate */
61 int (*write)(struct dw_spi *dws);
62 int (*read)(struct dw_spi *dws);
63 void (*cs_control)(u32 command);
66 #ifdef CONFIG_DEBUG_FS
67 static int spi_show_regs_open(struct inode *inode, struct file *file)
69 file->private_data = inode->i_private;
73 #define SPI_REGS_BUFSIZE 1024
74 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
75 size_t count, loff_t *ppos)
82 dws = file->private_data;
84 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
88 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
89 "MRST SPI0 registers:\n");
90 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
91 "=================================\n");
92 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
93 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
94 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
95 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
96 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
97 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
98 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
99 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
100 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
101 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
102 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
103 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
104 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
105 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
106 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
107 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
108 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
109 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
110 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
111 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
112 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
113 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
114 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
115 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
116 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
117 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
118 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
119 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
120 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
121 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
122 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
123 "=================================\n");
125 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
130 static const struct file_operations mrst_spi_regs_ops = {
131 .owner = THIS_MODULE,
132 .open = spi_show_regs_open,
133 .read = spi_show_regs,
134 .llseek = default_llseek,
137 static int mrst_spi_debugfs_init(struct dw_spi *dws)
139 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
143 debugfs_create_file("registers", S_IFREG | S_IRUGO,
144 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
148 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
151 debugfs_remove_recursive(dws->debugfs);
155 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
160 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
163 #endif /* CONFIG_DEBUG_FS */
165 static void wait_till_not_busy(struct dw_spi *dws)
167 unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
169 while (time_before(jiffies, end)) {
170 if (!(dw_readw(dws, sr) & SR_BUSY))
174 dev_err(&dws->master->dev,
175 "DW SPI: Status keeps busy for 5000us after a read/write!\n");
178 static void flush(struct dw_spi *dws)
180 while (dw_readw(dws, sr) & SR_RF_NOT_EMPT) {
185 wait_till_not_busy(dws);
188 static int null_writer(struct dw_spi *dws)
190 u8 n_bytes = dws->n_bytes;
192 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
193 || (dws->tx == dws->tx_end))
195 dw_writew(dws, dr, 0);
198 wait_till_not_busy(dws);
202 static int null_reader(struct dw_spi *dws)
204 u8 n_bytes = dws->n_bytes;
206 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
207 && (dws->rx < dws->rx_end)) {
211 wait_till_not_busy(dws);
212 return dws->rx == dws->rx_end;
215 static int u8_writer(struct dw_spi *dws)
217 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
218 || (dws->tx == dws->tx_end))
221 dw_writew(dws, dr, *(u8 *)(dws->tx));
224 wait_till_not_busy(dws);
228 static int u8_reader(struct dw_spi *dws)
230 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
231 && (dws->rx < dws->rx_end)) {
232 *(u8 *)(dws->rx) = dw_readw(dws, dr);
236 wait_till_not_busy(dws);
237 return dws->rx == dws->rx_end;
240 static int u16_writer(struct dw_spi *dws)
242 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
243 || (dws->tx == dws->tx_end))
246 dw_writew(dws, dr, *(u16 *)(dws->tx));
249 wait_till_not_busy(dws);
253 static int u16_reader(struct dw_spi *dws)
257 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
258 && (dws->rx < dws->rx_end)) {
259 temp = dw_readw(dws, dr);
260 *(u16 *)(dws->rx) = temp;
264 wait_till_not_busy(dws);
265 return dws->rx == dws->rx_end;
268 static void *next_transfer(struct dw_spi *dws)
270 struct spi_message *msg = dws->cur_msg;
271 struct spi_transfer *trans = dws->cur_transfer;
273 /* Move to next transfer */
274 if (trans->transfer_list.next != &msg->transfers) {
276 list_entry(trans->transfer_list.next,
279 return RUNNING_STATE;
285 * Note: first step is the protocol driver prepares
286 * a dma-capable memory, and this func just need translate
287 * the virt addr to physical
289 static int map_dma_buffers(struct dw_spi *dws)
291 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
292 || !dws->cur_chip->enable_dma)
295 if (dws->cur_transfer->tx_dma)
296 dws->tx_dma = dws->cur_transfer->tx_dma;
298 if (dws->cur_transfer->rx_dma)
299 dws->rx_dma = dws->cur_transfer->rx_dma;
304 /* Caller already set message->status; dma and pio irqs are blocked */
305 static void giveback(struct dw_spi *dws)
307 struct spi_transfer *last_transfer;
309 struct spi_message *msg;
311 spin_lock_irqsave(&dws->lock, flags);
314 dws->cur_transfer = NULL;
315 dws->prev_chip = dws->cur_chip;
316 dws->cur_chip = NULL;
318 queue_work(dws->workqueue, &dws->pump_messages);
319 spin_unlock_irqrestore(&dws->lock, flags);
321 last_transfer = list_entry(msg->transfers.prev,
325 if (!last_transfer->cs_change && dws->cs_control)
326 dws->cs_control(MRST_SPI_DEASSERT);
330 msg->complete(msg->context);
333 static void int_error_stop(struct dw_spi *dws, const char *msg)
335 /* Stop and reset hw */
337 spi_enable_chip(dws, 0);
339 dev_err(&dws->master->dev, "%s\n", msg);
340 dws->cur_msg->state = ERROR_STATE;
341 tasklet_schedule(&dws->pump_transfers);
344 static void transfer_complete(struct dw_spi *dws)
346 /* Update total byte transfered return count actual bytes read */
347 dws->cur_msg->actual_length += dws->len;
349 /* Move to next transfer */
350 dws->cur_msg->state = next_transfer(dws);
352 /* Handle end of message */
353 if (dws->cur_msg->state == DONE_STATE) {
354 dws->cur_msg->status = 0;
357 tasklet_schedule(&dws->pump_transfers);
360 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
362 u16 irq_status, irq_mask = 0x3f;
363 u32 int_level = dws->fifo_len / 2;
366 irq_status = dw_readw(dws, isr) & irq_mask;
368 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
369 dw_readw(dws, txoicr);
370 dw_readw(dws, rxoicr);
371 dw_readw(dws, rxuicr);
372 int_error_stop(dws, "interrupt_transfer: fifo overrun");
376 if (irq_status & SPI_INT_TXEI) {
377 spi_mask_intr(dws, SPI_INT_TXEI);
379 left = (dws->tx_end - dws->tx) / dws->n_bytes;
380 left = (left > int_level) ? int_level : left;
386 /* Re-enable the IRQ if there is still data left to tx */
387 if (dws->tx_end > dws->tx)
388 spi_umask_intr(dws, SPI_INT_TXEI);
390 transfer_complete(dws);
396 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
398 struct dw_spi *dws = dev_id;
399 u16 irq_status, irq_mask = 0x3f;
401 irq_status = dw_readw(dws, isr) & irq_mask;
406 spi_mask_intr(dws, SPI_INT_TXEI);
411 return dws->transfer_handler(dws);
414 /* Must be called inside pump_transfers() */
415 static void poll_transfer(struct dw_spi *dws)
417 while (dws->write(dws))
420 * There is a possibility that the last word of a transaction
421 * will be lost if data is not ready. Re-read to solve this issue.
425 transfer_complete(dws);
428 static void dma_transfer(struct dw_spi *dws, int cs_change)
432 static void pump_transfers(unsigned long data)
434 struct dw_spi *dws = (struct dw_spi *)data;
435 struct spi_message *message = NULL;
436 struct spi_transfer *transfer = NULL;
437 struct spi_transfer *previous = NULL;
438 struct spi_device *spi = NULL;
439 struct chip_data *chip = NULL;
448 /* Get current state information */
449 message = dws->cur_msg;
450 transfer = dws->cur_transfer;
451 chip = dws->cur_chip;
454 if (unlikely(!chip->clk_div))
455 chip->clk_div = dws->max_freq / chip->speed_hz;
457 if (message->state == ERROR_STATE) {
458 message->status = -EIO;
462 /* Handle end of message */
463 if (message->state == DONE_STATE) {
468 /* Delay if requested at end of transfer*/
469 if (message->state == RUNNING_STATE) {
470 previous = list_entry(transfer->transfer_list.prev,
473 if (previous->delay_usecs)
474 udelay(previous->delay_usecs);
477 dws->n_bytes = chip->n_bytes;
478 dws->dma_width = chip->dma_width;
479 dws->cs_control = chip->cs_control;
481 dws->rx_dma = transfer->rx_dma;
482 dws->tx_dma = transfer->tx_dma;
483 dws->tx = (void *)transfer->tx_buf;
484 dws->tx_end = dws->tx + transfer->len;
485 dws->rx = transfer->rx_buf;
486 dws->rx_end = dws->rx + transfer->len;
487 dws->write = dws->tx ? chip->write : null_writer;
488 dws->read = dws->rx ? chip->read : null_reader;
489 dws->cs_change = transfer->cs_change;
490 dws->len = dws->cur_transfer->len;
491 if (chip != dws->prev_chip)
496 /* Handle per transfer options for bpw and speed */
497 if (transfer->speed_hz) {
498 speed = chip->speed_hz;
500 if (transfer->speed_hz != speed) {
501 speed = transfer->speed_hz;
502 if (speed > dws->max_freq) {
503 printk(KERN_ERR "MRST SPI0: unsupported"
504 "freq: %dHz\n", speed);
505 message->status = -EIO;
509 /* clk_div doesn't support odd number */
510 clk_div = dws->max_freq / speed;
511 clk_div = (clk_div + 1) & 0xfffe;
513 chip->speed_hz = speed;
514 chip->clk_div = clk_div;
517 if (transfer->bits_per_word) {
518 bits = transfer->bits_per_word;
524 dws->read = (dws->read != null_reader) ?
525 u8_reader : null_reader;
526 dws->write = (dws->write != null_writer) ?
527 u8_writer : null_writer;
532 dws->read = (dws->read != null_reader) ?
533 u16_reader : null_reader;
534 dws->write = (dws->write != null_writer) ?
535 u16_writer : null_writer;
538 printk(KERN_ERR "MRST SPI0: unsupported bits:"
540 message->status = -EIO;
545 | (chip->type << SPI_FRF_OFFSET)
546 | (spi->mode << SPI_MODE_OFFSET)
547 | (chip->tmode << SPI_TMOD_OFFSET);
549 message->state = RUNNING_STATE;
552 * Adjust transfer mode if necessary. Requires platform dependent
553 * chipselect mechanism.
555 if (dws->cs_control) {
556 if (dws->rx && dws->tx)
557 chip->tmode = SPI_TMOD_TR;
559 chip->tmode = SPI_TMOD_RO;
561 chip->tmode = SPI_TMOD_TO;
563 cr0 &= ~SPI_TMOD_MASK;
564 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
567 /* Check if current transfer is a DMA transaction */
568 dws->dma_mapped = map_dma_buffers(dws);
572 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
574 if (!dws->dma_mapped && !chip->poll_mode) {
575 int templen = dws->len / dws->n_bytes;
576 txint_level = dws->fifo_len / 2;
577 txint_level = (templen > txint_level) ? txint_level : templen;
579 imask |= SPI_INT_TXEI;
580 dws->transfer_handler = interrupt_transfer;
584 * Reprogram registers only if
585 * 1. chip select changes
586 * 2. clk_div is changed
587 * 3. control value changes
589 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
590 spi_enable_chip(dws, 0);
592 if (dw_readw(dws, ctrl0) != cr0)
593 dw_writew(dws, ctrl0, cr0);
595 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
596 spi_chip_sel(dws, spi->chip_select);
598 /* Set the interrupt mask, for poll mode just diable all int */
599 spi_mask_intr(dws, 0xff);
601 spi_umask_intr(dws, imask);
603 dw_writew(dws, txfltr, txint_level);
605 spi_enable_chip(dws, 1);
607 dws->prev_chip = chip;
611 dma_transfer(dws, cs_change);
623 static void pump_messages(struct work_struct *work)
626 container_of(work, struct dw_spi, pump_messages);
629 /* Lock queue and check for queue work */
630 spin_lock_irqsave(&dws->lock, flags);
631 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
633 spin_unlock_irqrestore(&dws->lock, flags);
637 /* Make sure we are not already running a message */
639 spin_unlock_irqrestore(&dws->lock, flags);
643 /* Extract head of queue */
644 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
645 list_del_init(&dws->cur_msg->queue);
647 /* Initial message state*/
648 dws->cur_msg->state = START_STATE;
649 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
652 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
654 /* Mark as busy and launch transfers */
655 tasklet_schedule(&dws->pump_transfers);
658 spin_unlock_irqrestore(&dws->lock, flags);
661 /* spi_device use this to queue in their spi_msg */
662 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
664 struct dw_spi *dws = spi_master_get_devdata(spi->master);
667 spin_lock_irqsave(&dws->lock, flags);
669 if (dws->run == QUEUE_STOPPED) {
670 spin_unlock_irqrestore(&dws->lock, flags);
674 msg->actual_length = 0;
675 msg->status = -EINPROGRESS;
676 msg->state = START_STATE;
678 list_add_tail(&msg->queue, &dws->queue);
680 if (dws->run == QUEUE_RUNNING && !dws->busy) {
682 if (dws->cur_transfer || dws->cur_msg)
683 queue_work(dws->workqueue,
684 &dws->pump_messages);
686 /* If no other data transaction in air, just go */
687 spin_unlock_irqrestore(&dws->lock, flags);
688 pump_messages(&dws->pump_messages);
693 spin_unlock_irqrestore(&dws->lock, flags);
697 /* This may be called twice for each spi dev */
698 static int dw_spi_setup(struct spi_device *spi)
700 struct dw_spi_chip *chip_info = NULL;
701 struct chip_data *chip;
703 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
706 /* Only alloc on first setup */
707 chip = spi_get_ctldata(spi);
709 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
715 * Protocol drivers may change the chip settings, so...
716 * if chip_info exists, use it
718 chip_info = spi->controller_data;
720 /* chip_info doesn't always exist */
722 if (chip_info->cs_control)
723 chip->cs_control = chip_info->cs_control;
725 chip->poll_mode = chip_info->poll_mode;
726 chip->type = chip_info->type;
728 chip->rx_threshold = 0;
729 chip->tx_threshold = 0;
731 chip->enable_dma = chip_info->enable_dma;
734 if (spi->bits_per_word <= 8) {
737 chip->read = u8_reader;
738 chip->write = u8_writer;
739 } else if (spi->bits_per_word <= 16) {
742 chip->read = u16_reader;
743 chip->write = u16_writer;
745 /* Never take >16b case for MRST SPIC */
746 dev_err(&spi->dev, "invalid wordsize\n");
749 chip->bits_per_word = spi->bits_per_word;
751 if (!spi->max_speed_hz) {
752 dev_err(&spi->dev, "No max speed HZ parameter\n");
755 chip->speed_hz = spi->max_speed_hz;
757 chip->tmode = 0; /* Tx & Rx */
758 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
759 chip->cr0 = (chip->bits_per_word - 1)
760 | (chip->type << SPI_FRF_OFFSET)
761 | (spi->mode << SPI_MODE_OFFSET)
762 | (chip->tmode << SPI_TMOD_OFFSET);
764 spi_set_ctldata(spi, chip);
768 static void dw_spi_cleanup(struct spi_device *spi)
770 struct chip_data *chip = spi_get_ctldata(spi);
774 static int __devinit init_queue(struct dw_spi *dws)
776 INIT_LIST_HEAD(&dws->queue);
777 spin_lock_init(&dws->lock);
779 dws->run = QUEUE_STOPPED;
782 tasklet_init(&dws->pump_transfers,
783 pump_transfers, (unsigned long)dws);
785 INIT_WORK(&dws->pump_messages, pump_messages);
786 dws->workqueue = create_singlethread_workqueue(
787 dev_name(dws->master->dev.parent));
788 if (dws->workqueue == NULL)
794 static int start_queue(struct dw_spi *dws)
798 spin_lock_irqsave(&dws->lock, flags);
800 if (dws->run == QUEUE_RUNNING || dws->busy) {
801 spin_unlock_irqrestore(&dws->lock, flags);
805 dws->run = QUEUE_RUNNING;
807 dws->cur_transfer = NULL;
808 dws->cur_chip = NULL;
809 dws->prev_chip = NULL;
810 spin_unlock_irqrestore(&dws->lock, flags);
812 queue_work(dws->workqueue, &dws->pump_messages);
817 static int stop_queue(struct dw_spi *dws)
823 spin_lock_irqsave(&dws->lock, flags);
824 dws->run = QUEUE_STOPPED;
825 while (!list_empty(&dws->queue) && dws->busy && limit--) {
826 spin_unlock_irqrestore(&dws->lock, flags);
828 spin_lock_irqsave(&dws->lock, flags);
831 if (!list_empty(&dws->queue) || dws->busy)
833 spin_unlock_irqrestore(&dws->lock, flags);
838 static int destroy_queue(struct dw_spi *dws)
842 status = stop_queue(dws);
845 destroy_workqueue(dws->workqueue);
849 /* Restart the controller, disable all interrupts, clean rx fifo */
850 static void spi_hw_init(struct dw_spi *dws)
852 spi_enable_chip(dws, 0);
853 spi_mask_intr(dws, 0xff);
854 spi_enable_chip(dws, 1);
858 * Try to detect the FIFO depth if not set by interface driver,
859 * the depth could be from 2 to 256 from HW spec
861 if (!dws->fifo_len) {
863 for (fifo = 2; fifo <= 257; fifo++) {
864 dw_writew(dws, txfltr, fifo);
865 if (fifo != dw_readw(dws, txfltr))
869 dws->fifo_len = (fifo == 257) ? 0 : fifo;
870 dw_writew(dws, txfltr, 0);
874 int __devinit dw_spi_add_host(struct dw_spi *dws)
876 struct spi_master *master;
881 master = spi_alloc_master(dws->parent_dev, 0);
887 dws->master = master;
888 dws->type = SSI_MOTO_SPI;
889 dws->prev_chip = NULL;
891 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
893 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
896 dev_err(&master->dev, "can not get IRQ\n");
897 goto err_free_master;
900 master->mode_bits = SPI_CPOL | SPI_CPHA;
901 master->bus_num = dws->bus_num;
902 master->num_chipselect = dws->num_cs;
903 master->cleanup = dw_spi_cleanup;
904 master->setup = dw_spi_setup;
905 master->transfer = dw_spi_transfer;
912 /* Initial and start queue */
913 ret = init_queue(dws);
915 dev_err(&master->dev, "problem initializing queue\n");
918 ret = start_queue(dws);
920 dev_err(&master->dev, "problem starting queue\n");
924 spi_master_set_devdata(master, dws);
925 ret = spi_register_master(master);
927 dev_err(&master->dev, "problem registering spi master\n");
928 goto err_queue_alloc;
931 mrst_spi_debugfs_init(dws);
937 spi_enable_chip(dws, 0);
938 free_irq(dws->irq, dws);
940 spi_master_put(master);
944 EXPORT_SYMBOL(dw_spi_add_host);
946 void __devexit dw_spi_remove_host(struct dw_spi *dws)
952 mrst_spi_debugfs_remove(dws);
954 /* Remove the queue */
955 status = destroy_queue(dws);
957 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
958 "complete, message memory not freed\n");
960 spi_enable_chip(dws, 0);
963 free_irq(dws->irq, dws);
965 /* Disconnect from the SPI framework */
966 spi_unregister_master(dws->master);
968 EXPORT_SYMBOL(dw_spi_remove_host);
970 int dw_spi_suspend_host(struct dw_spi *dws)
974 ret = stop_queue(dws);
977 spi_enable_chip(dws, 0);
981 EXPORT_SYMBOL(dw_spi_suspend_host);
983 int dw_spi_resume_host(struct dw_spi *dws)
988 ret = start_queue(dws);
990 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
993 EXPORT_SYMBOL(dw_spi_resume_host);
995 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
996 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
997 MODULE_LICENSE("GPL v2");