1 // SPDX-License-Identifier: GPL-2.0
3 * Designware master SPI core controller driver
5 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
7 * Very loosely based on the Linux driver:
8 * drivers/spi/spi-dw.c, which is:
9 * Copyright (c) 2009, Intel Corporation.
12 #include <asm-generic/gpio.h>
21 #include <linux/compat.h>
22 #include <linux/iopoll.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 /* Register offsets */
28 #define DW_SPI_CTRL0 0x00
29 #define DW_SPI_CTRL1 0x04
30 #define DW_SPI_SSIENR 0x08
31 #define DW_SPI_MWCR 0x0c
32 #define DW_SPI_SER 0x10
33 #define DW_SPI_BAUDR 0x14
34 #define DW_SPI_TXFLTR 0x18
35 #define DW_SPI_RXFLTR 0x1c
36 #define DW_SPI_TXFLR 0x20
37 #define DW_SPI_RXFLR 0x24
38 #define DW_SPI_SR 0x28
39 #define DW_SPI_IMR 0x2c
40 #define DW_SPI_ISR 0x30
41 #define DW_SPI_RISR 0x34
42 #define DW_SPI_TXOICR 0x38
43 #define DW_SPI_RXOICR 0x3c
44 #define DW_SPI_RXUICR 0x40
45 #define DW_SPI_MSTICR 0x44
46 #define DW_SPI_ICR 0x48
47 #define DW_SPI_DMACR 0x4c
48 #define DW_SPI_DMATDLR 0x50
49 #define DW_SPI_DMARDLR 0x54
50 #define DW_SPI_IDR 0x58
51 #define DW_SPI_VERSION 0x5c
52 #define DW_SPI_DR 0x60
54 /* Bit fields in CTRLR0 */
55 #define SPI_DFS_OFFSET 0
57 #define SPI_FRF_OFFSET 4
58 #define SPI_FRF_SPI 0x0
59 #define SPI_FRF_SSP 0x1
60 #define SPI_FRF_MICROWIRE 0x2
61 #define SPI_FRF_RESV 0x3
63 #define SPI_MODE_OFFSET 6
64 #define SPI_SCPH_OFFSET 6
65 #define SPI_SCOL_OFFSET 7
67 #define SPI_TMOD_OFFSET 8
68 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
69 #define SPI_TMOD_TR 0x0 /* xmit & recv */
70 #define SPI_TMOD_TO 0x1 /* xmit only */
71 #define SPI_TMOD_RO 0x2 /* recv only */
72 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
74 #define SPI_SLVOE_OFFSET 10
75 #define SPI_SRL_OFFSET 11
76 #define SPI_CFS_OFFSET 12
78 /* Bit fields in SR, 7 bits */
79 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
80 #define SR_BUSY BIT(0)
81 #define SR_TF_NOT_FULL BIT(1)
82 #define SR_TF_EMPT BIT(2)
83 #define SR_RF_NOT_EMPT BIT(3)
84 #define SR_RF_FULL BIT(4)
85 #define SR_TX_ERR BIT(5)
86 #define SR_DCOL BIT(6)
88 #define RX_TIMEOUT 1000 /* timeout in ms */
90 struct dw_spi_platdata {
91 s32 frequency; /* Default clock frequency, -1 for none */
97 unsigned int freq; /* Default frequency */
100 unsigned long bus_clk_rate;
102 struct gpio_desc cs_gpio; /* External chip-select gpio */
105 u8 cs; /* chip select pin */
106 u8 tmode; /* TR/TO/RO/EEPROM */
107 u8 type; /* SPI/SSP/MicroWire */
110 u32 fifo_len; /* depth of the FIFO buffer */
116 struct reset_ctl_bulk resets;
119 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
121 return __raw_readl(priv->regs + offset);
124 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
126 __raw_writel(val, priv->regs + offset);
129 static int request_gpio_cs(struct udevice *bus)
131 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
132 struct dw_spi_priv *priv = dev_get_priv(bus);
135 /* External chip select gpio line is optional */
136 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
141 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
145 if (dm_gpio_is_valid(&priv->cs_gpio)) {
146 dm_gpio_set_dir_flags(&priv->cs_gpio,
147 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
150 debug("%s: used external gpio for CS management\n", __func__);
155 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
157 struct dw_spi_platdata *plat = bus->platdata;
158 const void *blob = gd->fdt_blob;
159 int node = dev_of_offset(bus);
161 plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
163 /* Use 500KHz as a suitable default */
164 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
166 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
169 return request_gpio_cs(bus);
172 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
174 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
177 /* Restart the controller, disable all interrupts, clean rx fifo */
178 static void spi_hw_init(struct dw_spi_priv *priv)
180 spi_enable_chip(priv, 0);
181 dw_write(priv, DW_SPI_IMR, 0xff);
182 spi_enable_chip(priv, 1);
185 * Try to detect the FIFO depth if not set by interface driver,
186 * the depth could be from 2 to 256 from HW spec
188 if (!priv->fifo_len) {
191 for (fifo = 1; fifo < 256; fifo++) {
192 dw_write(priv, DW_SPI_TXFLTR, fifo);
193 if (fifo != dw_read(priv, DW_SPI_TXFLTR))
197 priv->fifo_len = (fifo == 1) ? 0 : fifo;
198 dw_write(priv, DW_SPI_TXFLTR, 0);
200 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
204 * We define dw_spi_get_clk function as 'weak' as some targets
205 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
206 * and implement dw_spi_get_clk their own way in their clock manager.
208 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
210 struct dw_spi_priv *priv = dev_get_priv(bus);
213 ret = clk_get_by_index(bus, 0, &priv->clk);
217 ret = clk_enable(&priv->clk);
218 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
221 *rate = clk_get_rate(&priv->clk);
225 debug("%s: get spi controller clk via device tree: %lu Hz\n",
231 clk_disable(&priv->clk);
232 clk_free(&priv->clk);
237 static int dw_spi_reset(struct udevice *bus)
240 struct dw_spi_priv *priv = dev_get_priv(bus);
242 ret = reset_get_bulk(bus, &priv->resets);
245 * Return 0 if error due to !CONFIG_DM_RESET and reset
246 * DT property is not present.
248 if (ret == -ENOENT || ret == -ENOTSUPP)
251 dev_warn(bus, "Can't get reset: %d\n", ret);
255 ret = reset_deassert_bulk(&priv->resets);
257 reset_release_bulk(&priv->resets);
258 dev_err(bus, "Failed to reset: %d\n", ret);
265 static int dw_spi_probe(struct udevice *bus)
267 struct dw_spi_platdata *plat = dev_get_platdata(bus);
268 struct dw_spi_priv *priv = dev_get_priv(bus);
271 priv->regs = plat->regs;
272 priv->freq = plat->frequency;
274 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
278 ret = dw_spi_reset(bus);
282 /* Currently only bits_per_word == 8 supported */
283 priv->bits_per_word = 8;
285 priv->tmode = 0; /* Tx & Rx */
293 /* Return the max entries we can fill into tx fifo */
294 static inline u32 tx_max(struct dw_spi_priv *priv)
296 u32 tx_left, tx_room, rxtx_gap;
298 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
299 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
302 * Another concern is about the tx/rx mismatch, we
303 * thought about using (priv->fifo_len - rxflr - txflr) as
304 * one maximum value for tx, but it doesn't cover the
305 * data which is out of tx/rx fifo and inside the
306 * shift registers. So a control from sw point of
309 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
310 (priv->bits_per_word >> 3);
312 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
315 /* Return the max entries we should read out of rx fifo */
316 static inline u32 rx_max(struct dw_spi_priv *priv)
318 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
320 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
323 static void dw_writer(struct dw_spi_priv *priv)
325 u32 max = tx_max(priv);
329 /* Set the tx word if the transfer's original "tx" is not null */
330 if (priv->tx_end - priv->len) {
331 if (priv->bits_per_word == 8)
332 txw = *(u8 *)(priv->tx);
334 txw = *(u16 *)(priv->tx);
336 dw_write(priv, DW_SPI_DR, txw);
337 debug("%s: tx=0x%02x\n", __func__, txw);
338 priv->tx += priv->bits_per_word >> 3;
342 static void dw_reader(struct dw_spi_priv *priv)
344 u32 max = rx_max(priv);
348 rxw = dw_read(priv, DW_SPI_DR);
349 debug("%s: rx=0x%02x\n", __func__, rxw);
351 /* Care about rx if the transfer's original "rx" is not null */
352 if (priv->rx_end - priv->len) {
353 if (priv->bits_per_word == 8)
354 *(u8 *)(priv->rx) = rxw;
356 *(u16 *)(priv->rx) = rxw;
358 priv->rx += priv->bits_per_word >> 3;
362 static int poll_transfer(struct dw_spi_priv *priv)
367 } while (priv->rx_end > priv->rx);
372 static void external_cs_manage(struct udevice *dev, bool on)
374 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
375 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
377 if (!dm_gpio_is_valid(&priv->cs_gpio))
380 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
384 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
385 const void *dout, void *din, unsigned long flags)
387 struct udevice *bus = dev->parent;
388 struct dw_spi_priv *priv = dev_get_priv(bus);
396 /* spi core configured to do 8 bit transfers */
398 debug("Non byte aligned SPI transfer.\n");
402 /* Start the transaction if necessary. */
403 if (flags & SPI_XFER_BEGIN)
404 external_cs_manage(dev, false);
406 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
407 (priv->mode << SPI_MODE_OFFSET) |
408 (priv->tmode << SPI_TMOD_OFFSET);
411 priv->tmode = SPI_TMOD_TR;
413 priv->tmode = SPI_TMOD_RO;
416 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
417 * any data which breaks our logic in poll_transfer() above.
419 priv->tmode = SPI_TMOD_TR;
421 cr0 &= ~SPI_TMOD_MASK;
422 cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
424 priv->len = bitlen >> 3;
425 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
427 priv->tx = (void *)tx;
428 priv->tx_end = priv->tx + priv->len;
430 priv->rx_end = priv->rx + priv->len;
432 /* Disable controller before writing control registers */
433 spi_enable_chip(priv, 0);
435 debug("%s: cr0=%08x\n", __func__, cr0);
436 /* Reprogram cr0 only if changed */
437 if (dw_read(priv, DW_SPI_CTRL0) != cr0)
438 dw_write(priv, DW_SPI_CTRL0, cr0);
441 * Configure the desired SS (slave select 0...3) in the controller
442 * The DW SPI controller will activate and deactivate this CS
443 * automatically. So no cs_activate() etc is needed in this driver.
445 cs = spi_chip_select(dev);
446 dw_write(priv, DW_SPI_SER, 1 << cs);
448 /* Enable controller after writing control registers */
449 spi_enable_chip(priv, 1);
451 /* Start transfer in a polling loop */
452 ret = poll_transfer(priv);
455 * Wait for current transmit operation to complete.
456 * Otherwise if some data still exists in Tx FIFO it can be
457 * silently flushed, i.e. dropped on disabling of the controller,
458 * which happens when writing 0 to DW_SPI_SSIENR which happens
459 * in the beginning of new transfer.
461 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
462 (val & SR_TF_EMPT) && !(val & SR_BUSY),
463 RX_TIMEOUT * 1000)) {
467 /* Stop the transaction if necessary */
468 if (flags & SPI_XFER_END)
469 external_cs_manage(dev, true);
474 static int dw_spi_set_speed(struct udevice *bus, uint speed)
476 struct dw_spi_platdata *plat = bus->platdata;
477 struct dw_spi_priv *priv = dev_get_priv(bus);
480 if (speed > plat->frequency)
481 speed = plat->frequency;
483 /* Disable controller before writing control registers */
484 spi_enable_chip(priv, 0);
486 /* clk_div doesn't support odd number */
487 clk_div = priv->bus_clk_rate / speed;
488 clk_div = (clk_div + 1) & 0xfffe;
489 dw_write(priv, DW_SPI_BAUDR, clk_div);
491 /* Enable controller after writing control registers */
492 spi_enable_chip(priv, 1);
495 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
496 priv->freq, clk_div);
501 static int dw_spi_set_mode(struct udevice *bus, uint mode)
503 struct dw_spi_priv *priv = dev_get_priv(bus);
506 * Can't set mode yet. Since this depends on if rx, tx, or
507 * rx & tx is requested. So we have to defer this to the
508 * real transfer function.
511 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
516 static int dw_spi_remove(struct udevice *bus)
518 struct dw_spi_priv *priv = dev_get_priv(bus);
520 return reset_release_bulk(&priv->resets);
523 static const struct dm_spi_ops dw_spi_ops = {
525 .set_speed = dw_spi_set_speed,
526 .set_mode = dw_spi_set_mode,
528 * cs_info is not needed, since we require all chip selects to be
529 * in the device tree explicitly
533 static const struct udevice_id dw_spi_ids[] = {
534 { .compatible = "snps,dw-apb-ssi" },
538 U_BOOT_DRIVER(dw_spi) = {
541 .of_match = dw_spi_ids,
543 .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
544 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
545 .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
546 .probe = dw_spi_probe,
547 .remove = dw_spi_remove,