1 // SPDX-License-Identifier: GPL-2.0
3 * Designware master SPI core controller driver
5 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
7 * Very loosely based on the Linux driver:
8 * drivers/spi/spi-dw.c, which is:
9 * Copyright (c) 2009, Intel Corporation.
14 #include <asm-generic/gpio.h>
22 #include <dm/device_compat.h>
23 #include <linux/bitops.h>
24 #include <linux/compat.h>
25 #include <linux/iopoll.h>
28 /* Register offsets */
29 #define DW_SPI_CTRL0 0x00
30 #define DW_SPI_CTRL1 0x04
31 #define DW_SPI_SSIENR 0x08
32 #define DW_SPI_MWCR 0x0c
33 #define DW_SPI_SER 0x10
34 #define DW_SPI_BAUDR 0x14
35 #define DW_SPI_TXFLTR 0x18
36 #define DW_SPI_RXFLTR 0x1c
37 #define DW_SPI_TXFLR 0x20
38 #define DW_SPI_RXFLR 0x24
39 #define DW_SPI_SR 0x28
40 #define DW_SPI_IMR 0x2c
41 #define DW_SPI_ISR 0x30
42 #define DW_SPI_RISR 0x34
43 #define DW_SPI_TXOICR 0x38
44 #define DW_SPI_RXOICR 0x3c
45 #define DW_SPI_RXUICR 0x40
46 #define DW_SPI_MSTICR 0x44
47 #define DW_SPI_ICR 0x48
48 #define DW_SPI_DMACR 0x4c
49 #define DW_SPI_DMATDLR 0x50
50 #define DW_SPI_DMARDLR 0x54
51 #define DW_SPI_IDR 0x58
52 #define DW_SPI_VERSION 0x5c
53 #define DW_SPI_DR 0x60
55 /* Bit fields in CTRLR0 */
56 #define SPI_DFS_OFFSET 0
58 #define SPI_FRF_OFFSET 4
59 #define SPI_FRF_SPI 0x0
60 #define SPI_FRF_SSP 0x1
61 #define SPI_FRF_MICROWIRE 0x2
62 #define SPI_FRF_RESV 0x3
64 #define SPI_MODE_OFFSET 6
65 #define SPI_SCPH_OFFSET 6
66 #define SPI_SCOL_OFFSET 7
68 #define SPI_TMOD_OFFSET 8
69 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
70 #define SPI_TMOD_TR 0x0 /* xmit & recv */
71 #define SPI_TMOD_TO 0x1 /* xmit only */
72 #define SPI_TMOD_RO 0x2 /* recv only */
73 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
75 #define SPI_SLVOE_OFFSET 10
76 #define SPI_SRL_OFFSET 11
77 #define SPI_CFS_OFFSET 12
79 /* Bit fields in SR, 7 bits */
80 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
81 #define SR_BUSY BIT(0)
82 #define SR_TF_NOT_FULL BIT(1)
83 #define SR_TF_EMPT BIT(2)
84 #define SR_RF_NOT_EMPT BIT(3)
85 #define SR_RF_FULL BIT(4)
86 #define SR_TX_ERR BIT(5)
87 #define SR_DCOL BIT(6)
89 #define RX_TIMEOUT 1000 /* timeout in ms */
91 struct dw_spi_platdata {
92 s32 frequency; /* Default clock frequency, -1 for none */
98 unsigned int freq; /* Default frequency */
101 unsigned long bus_clk_rate;
103 struct gpio_desc cs_gpio; /* External chip-select gpio */
106 u8 cs; /* chip select pin */
107 u8 tmode; /* TR/TO/RO/EEPROM */
108 u8 type; /* SPI/SSP/MicroWire */
111 u32 fifo_len; /* depth of the FIFO buffer */
117 struct reset_ctl_bulk resets;
120 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
122 return __raw_readl(priv->regs + offset);
125 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
127 __raw_writel(val, priv->regs + offset);
130 static int request_gpio_cs(struct udevice *bus)
132 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
133 struct dw_spi_priv *priv = dev_get_priv(bus);
136 /* External chip select gpio line is optional */
137 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
142 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
146 if (dm_gpio_is_valid(&priv->cs_gpio)) {
147 dm_gpio_set_dir_flags(&priv->cs_gpio,
148 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
151 debug("%s: used external gpio for CS management\n", __func__);
156 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
158 struct dw_spi_platdata *plat = bus->platdata;
160 plat->regs = dev_read_addr_ptr(bus);
162 /* Use 500KHz as a suitable default */
163 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
165 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
168 return request_gpio_cs(bus);
171 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
173 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
176 /* Restart the controller, disable all interrupts, clean rx fifo */
177 static void spi_hw_init(struct dw_spi_priv *priv)
179 spi_enable_chip(priv, 0);
180 dw_write(priv, DW_SPI_IMR, 0xff);
181 spi_enable_chip(priv, 1);
184 * Try to detect the FIFO depth if not set by interface driver,
185 * the depth could be from 2 to 256 from HW spec
187 if (!priv->fifo_len) {
190 for (fifo = 1; fifo < 256; fifo++) {
191 dw_write(priv, DW_SPI_TXFLTR, fifo);
192 if (fifo != dw_read(priv, DW_SPI_TXFLTR))
196 priv->fifo_len = (fifo == 1) ? 0 : fifo;
197 dw_write(priv, DW_SPI_TXFLTR, 0);
199 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
203 * We define dw_spi_get_clk function as 'weak' as some targets
204 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
205 * and implement dw_spi_get_clk their own way in their clock manager.
207 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
209 struct dw_spi_priv *priv = dev_get_priv(bus);
212 ret = clk_get_by_index(bus, 0, &priv->clk);
216 ret = clk_enable(&priv->clk);
217 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
220 *rate = clk_get_rate(&priv->clk);
224 debug("%s: get spi controller clk via device tree: %lu Hz\n",
230 clk_disable(&priv->clk);
231 clk_free(&priv->clk);
236 static int dw_spi_reset(struct udevice *bus)
239 struct dw_spi_priv *priv = dev_get_priv(bus);
241 ret = reset_get_bulk(bus, &priv->resets);
244 * Return 0 if error due to !CONFIG_DM_RESET and reset
245 * DT property is not present.
247 if (ret == -ENOENT || ret == -ENOTSUPP)
250 dev_warn(bus, "Can't get reset: %d\n", ret);
254 ret = reset_deassert_bulk(&priv->resets);
256 reset_release_bulk(&priv->resets);
257 dev_err(bus, "Failed to reset: %d\n", ret);
264 static int dw_spi_probe(struct udevice *bus)
266 struct dw_spi_platdata *plat = dev_get_platdata(bus);
267 struct dw_spi_priv *priv = dev_get_priv(bus);
270 priv->regs = plat->regs;
271 priv->freq = plat->frequency;
273 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
277 ret = dw_spi_reset(bus);
281 /* Currently only bits_per_word == 8 supported */
282 priv->bits_per_word = 8;
284 priv->tmode = 0; /* Tx & Rx */
292 /* Return the max entries we can fill into tx fifo */
293 static inline u32 tx_max(struct dw_spi_priv *priv)
295 u32 tx_left, tx_room, rxtx_gap;
297 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
298 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
301 * Another concern is about the tx/rx mismatch, we
302 * thought about using (priv->fifo_len - rxflr - txflr) as
303 * one maximum value for tx, but it doesn't cover the
304 * data which is out of tx/rx fifo and inside the
305 * shift registers. So a control from sw point of
308 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
309 (priv->bits_per_word >> 3);
311 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
314 /* Return the max entries we should read out of rx fifo */
315 static inline u32 rx_max(struct dw_spi_priv *priv)
317 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
319 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
322 static void dw_writer(struct dw_spi_priv *priv)
324 u32 max = tx_max(priv);
328 /* Set the tx word if the transfer's original "tx" is not null */
329 if (priv->tx_end - priv->len) {
330 if (priv->bits_per_word == 8)
331 txw = *(u8 *)(priv->tx);
333 txw = *(u16 *)(priv->tx);
335 dw_write(priv, DW_SPI_DR, txw);
336 debug("%s: tx=0x%02x\n", __func__, txw);
337 priv->tx += priv->bits_per_word >> 3;
341 static void dw_reader(struct dw_spi_priv *priv)
343 u32 max = rx_max(priv);
347 rxw = dw_read(priv, DW_SPI_DR);
348 debug("%s: rx=0x%02x\n", __func__, rxw);
350 /* Care about rx if the transfer's original "rx" is not null */
351 if (priv->rx_end - priv->len) {
352 if (priv->bits_per_word == 8)
353 *(u8 *)(priv->rx) = rxw;
355 *(u16 *)(priv->rx) = rxw;
357 priv->rx += priv->bits_per_word >> 3;
361 static int poll_transfer(struct dw_spi_priv *priv)
366 } while (priv->rx_end > priv->rx);
372 * We define external_cs_manage function as 'weak' as some targets
373 * (like MSCC Ocelot) don't control the external CS pin using a GPIO
374 * controller. These SoCs use specific registers to control by
375 * software the SPI pins (and especially the CS).
377 __weak void external_cs_manage(struct udevice *dev, bool on)
379 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
380 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
382 if (!dm_gpio_is_valid(&priv->cs_gpio))
385 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
389 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
390 const void *dout, void *din, unsigned long flags)
392 struct udevice *bus = dev->parent;
393 struct dw_spi_priv *priv = dev_get_priv(bus);
401 /* spi core configured to do 8 bit transfers */
403 debug("Non byte aligned SPI transfer.\n");
407 /* Start the transaction if necessary. */
408 if (flags & SPI_XFER_BEGIN)
409 external_cs_manage(dev, false);
411 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
412 (priv->mode << SPI_MODE_OFFSET) |
413 (priv->tmode << SPI_TMOD_OFFSET);
416 priv->tmode = SPI_TMOD_TR;
418 priv->tmode = SPI_TMOD_RO;
421 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
422 * any data which breaks our logic in poll_transfer() above.
424 priv->tmode = SPI_TMOD_TR;
426 cr0 &= ~SPI_TMOD_MASK;
427 cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
429 priv->len = bitlen >> 3;
430 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
432 priv->tx = (void *)tx;
433 priv->tx_end = priv->tx + priv->len;
435 priv->rx_end = priv->rx + priv->len;
437 /* Disable controller before writing control registers */
438 spi_enable_chip(priv, 0);
440 debug("%s: cr0=%08x\n", __func__, cr0);
441 /* Reprogram cr0 only if changed */
442 if (dw_read(priv, DW_SPI_CTRL0) != cr0)
443 dw_write(priv, DW_SPI_CTRL0, cr0);
446 * Configure the desired SS (slave select 0...3) in the controller
447 * The DW SPI controller will activate and deactivate this CS
448 * automatically. So no cs_activate() etc is needed in this driver.
450 cs = spi_chip_select(dev);
451 dw_write(priv, DW_SPI_SER, 1 << cs);
453 /* Enable controller after writing control registers */
454 spi_enable_chip(priv, 1);
456 /* Start transfer in a polling loop */
457 ret = poll_transfer(priv);
460 * Wait for current transmit operation to complete.
461 * Otherwise if some data still exists in Tx FIFO it can be
462 * silently flushed, i.e. dropped on disabling of the controller,
463 * which happens when writing 0 to DW_SPI_SSIENR which happens
464 * in the beginning of new transfer.
466 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
467 (val & SR_TF_EMPT) && !(val & SR_BUSY),
468 RX_TIMEOUT * 1000)) {
472 /* Stop the transaction if necessary */
473 if (flags & SPI_XFER_END)
474 external_cs_manage(dev, true);
479 static int dw_spi_set_speed(struct udevice *bus, uint speed)
481 struct dw_spi_platdata *plat = bus->platdata;
482 struct dw_spi_priv *priv = dev_get_priv(bus);
485 if (speed > plat->frequency)
486 speed = plat->frequency;
488 /* Disable controller before writing control registers */
489 spi_enable_chip(priv, 0);
491 /* clk_div doesn't support odd number */
492 clk_div = priv->bus_clk_rate / speed;
493 clk_div = (clk_div + 1) & 0xfffe;
494 dw_write(priv, DW_SPI_BAUDR, clk_div);
496 /* Enable controller after writing control registers */
497 spi_enable_chip(priv, 1);
500 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
501 priv->freq, clk_div);
506 static int dw_spi_set_mode(struct udevice *bus, uint mode)
508 struct dw_spi_priv *priv = dev_get_priv(bus);
511 * Can't set mode yet. Since this depends on if rx, tx, or
512 * rx & tx is requested. So we have to defer this to the
513 * real transfer function.
516 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
521 static int dw_spi_remove(struct udevice *bus)
523 struct dw_spi_priv *priv = dev_get_priv(bus);
526 ret = reset_release_bulk(&priv->resets);
530 #if CONFIG_IS_ENABLED(CLK)
531 ret = clk_disable(&priv->clk);
535 ret = clk_free(&priv->clk);
542 static const struct dm_spi_ops dw_spi_ops = {
544 .set_speed = dw_spi_set_speed,
545 .set_mode = dw_spi_set_mode,
547 * cs_info is not needed, since we require all chip selects to be
548 * in the device tree explicitly
552 static const struct udevice_id dw_spi_ids[] = {
553 { .compatible = "snps,dw-apb-ssi" },
557 U_BOOT_DRIVER(dw_spi) = {
560 .of_match = dw_spi_ids,
562 .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
563 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
564 .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
565 .probe = dw_spi_probe,
566 .remove = dw_spi_remove,